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JPS61127140A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61127140A
JPS61127140A JP59248484A JP24848484A JPS61127140A JP S61127140 A JPS61127140 A JP S61127140A JP 59248484 A JP59248484 A JP 59248484A JP 24848484 A JP24848484 A JP 24848484A JP S61127140 A JPS61127140 A JP S61127140A
Authority
JP
Japan
Prior art keywords
post
posts
row
wire
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59248484A
Other languages
Japanese (ja)
Other versions
JPH0426544B2 (en
Inventor
Mineo Nishikawa
西川　峰夫
Nobuhisa Ishida
暢久 石田
Mitsuhiko Fukuda
福田　満彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP59248484A priority Critical patent/JPS61127140A/en
Publication of JPS61127140A publication Critical patent/JPS61127140A/en
Publication of JPH0426544B2 publication Critical patent/JPH0426544B2/ja
Granted legal-status Critical Current

Links

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/061—Disposition
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    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
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    • H01L2224/481—Disposition
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the occurrence of contact trouble of the wire with which an element and a post are connected together by a method wherein an insulating layer, covering the lead linking to the first column, is provided between the first and the second columns of the post. CONSTITUTION:An insulating layer 10 covering the lead 6 which is linked to a post 4 is provided between the columns of posts 4 and 5. According to this constitution, as a wire 9 is retained on the surface of the insulating layer 10, it does not come into contact with the post 4 and the lead 6. Moreover, as the wire 9 is prevented from contacting to the post 4 and the lead 6 even when the junction position of an element 2 is shifted, the requirement of the degree of accuracy of junction position can be alleviated. As a result, the yield of production of the device can also be improved.

Description

【発明の詳細な説明】 （産業上の利用分野） この発明は半導体装置特に基板上にダイボンディングさ
れた半導体素子とポストとをワイヤボンディングして構
成される半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a semiconductor device constructed by wire-bonding a semiconductor element die-bonded onto a substrate and a post.

（従来の技術） 半導体チップ、集積回路等の半導体素子からなる半導体
装置では、基板上に前記半導体素子をダイボンディング
するとともに、基板上のポストと前記半導体素子のボン
ディングパットとを金線のようなワイヤでワイヤボンデ
ィングによって互いに接続するようにしたものはよく知
られている。(Prior Art) In a semiconductor device consisting of a semiconductor element such as a semiconductor chip or an integrated circuit, the semiconductor element is die-bonded onto a substrate, and the post on the substrate and the bonding pad of the semiconductor element are bonded using a wire such as a gold wire. It is well known that wires are connected to each other by wire bonding.

一方この種半導体装置ではその半導体素子の高密度化の
ためにボンディングパットのピッチを小さく、場合によ
っては千鳥状に並べるとともに、基板上のポストを千鳥
状に並べることが行われている（実開昭５８−１０７８
４４号公報参照）、シかしこのようにポストを千鳥状に
配列した場合は、半導体素子のダイボンディングの際に
位置ずれを起したとき、ワイヤとリードとが接触し合う
恐れがある。On the other hand, in this type of semiconductor device, in order to increase the density of the semiconductor element, the pitch of the bonding pads is reduced, and in some cases they are arranged in a staggered manner, and the posts on the substrate are arranged in a staggered manner. 1978-1078
However, when the posts are arranged in a staggered manner in this manner, there is a risk that the wires and the leads may come into contact with each other when a positional shift occurs during die bonding of a semiconductor element.

これを図面によって説明すると、第４図において１は基
板、２は半導体素子とし、この半導体素子には複数のボ
ンディングパット３が設置されてあるものとする。図示
するボンディングパット３は千鳥状に配列されてある。To explain this with reference to the drawings, in FIG. 4, 1 is a substrate, 2 is a semiconductor element, and a plurality of bonding pads 3 are installed on this semiconductor element. The illustrated bonding pads 3 are arranged in a staggered manner.

４は第１の列のポスト、５は第２の列のポストで、前記
第１の列のポストは半導体素子２に向い合うように並び
、第２の列は第１の列よりも半導体素子２から離れて並
ぶようにしである。なお各ポストは基板１上に設置され
てある。4 is a first column of posts, 5 is a second column of posts, the posts of the first column are arranged to face the semiconductor device 2, and the second column has more semiconductor devices than the first column. They should be lined up apart from 2. Note that each post is installed on the substrate 1.

各列のポストは交互に並ぶことによって千鳥状に配列さ
れてある。６は第１の列の各ポスト４に連なるリード、
７は第２の列の各ポスト５に連なるリード、８は第１の
列のポスト４と一方の列の各ボンディングパット３とを
接続するワイヤ、９は第２の列のポスト５と他の列の各
ボンディングパットとを接続するワイヤで、いずれもワ
イヤボンディングされてある。The posts in each row are arranged in a staggered manner by alternating each other. 6 is a lead connected to each post 4 of the first row,
7 is a lead connected to each post 5 in the second row; 8 is a wire connecting the post 4 in the first row to each bonding pad 3 in one row; 9 is a wire connecting the post 5 in the second row to the other bonding pad 3; These are wires that connect each bonding pad in the row, and all are wire-bonded.

半導体素子２が基板１上の規定の箇所にダイボンディン
グされた場合は何等の問題はない、すなわちこの場合は
後記する第１図に示すように各ボンディングパット３と
これに接続されるポスト４゜５は互いに正しく向い合う
ようになり、したがってワイヤ９は第１の列のボスト４
或いはそのり一ド６をまたぐようなことはない。There is no problem when the semiconductor element 2 is die-bonded to a specified location on the substrate 1. In this case, as shown in FIG. 5 are now facing each other correctly, so that the wires 9 are attached to the posts 4 of the first row.
Or, there is no such thing as straddling Do 6.

しかし半導体素子２が規定の箇所よりずれてダイボンデ
ィングされたとすると、第４図に示すように第２の列の
ポスト５に接続されるワイヤ９は第１の列のポストまた
はそのリード６をまたぐようになる１通常この種ワイヤ
は後記する第２図にも示すように、ボンディングパット
とポストとの間を垂れ下がるようにして張られる。その
ため前記第２の列のポスト５に接続されるワイヤ９はこ
れが垂れ下がることによってこれがまたいでいる第１の
列のポスト４またはこれに連なるリード６に接触してし
まうことがある。However, if the semiconductor element 2 is die-bonded at a position shifted from the specified position, the wire 9 connected to the post 5 in the second row will straddle the post or its lead 6 in the first row, as shown in FIG. 1 Usually, this type of wire is stretched so as to hang between a bonding pad and a post, as shown in FIG. 2, which will be described later. Therefore, the wire 9 connected to the second row of posts 5 may hang down and come into contact with the first row of posts 4 that it straddles or the leads 6 connected thereto.

（発明が解決しようとする問題点） この発明は半導体素子とポストとを接続するワイヤの接
触による事故の発生を簡単な構成によって確実に回避す
ることを目的とする。(Problems to be Solved by the Invention) It is an object of the present invention to reliably avoid accidents caused by contact between wires connecting a semiconductor element and a post with a simple configuration.

（問題点を解決するための手段） この発明は基板上のポストの第１の列と第２の列との間
に、前記第１の列のポストに連なるリードを覆うように
絶縁層を設置したことを特徴とする。(Means for Solving the Problems) This invention provides an insulating layer between a first row of posts and a second row of posts on a substrate so as to cover the leads connected to the posts of the first row. It is characterized by what it did.

この発明を図によって説明する。なお第４図と同じ符合
を付した部分は同一または対応する部分を示す、第１図
の構成から理解できるように、この発明では第１のポス
ト４の列と第２のポスト５の列との間に絶縁層１０を設
置する。この絶縁層１０は第１の列のポスト４に連なる
リード６を覆うように設置されてある。This invention will be explained using figures. Note that parts with the same reference numerals as in FIG. 4 indicate the same or corresponding parts.As can be understood from the configuration of FIG. 1, in this invention, the first row of posts 4 and the second row of posts 5 An insulating layer 10 is placed between them. This insulating layer 10 is placed so as to cover the leads 6 connected to the posts 4 in the first row.

（作用） 第１図は半導体素子２が基板１上の規定位置にダイボン
ディングされたときの状態を示し、このときは各ワイヤ
８，９はそれぞれ互いに平行するようにしである。した
がって各ワイヤはポスト４゜５並びにこれに連なるリー
ド６．７の上方を通過するようなことは何等ない。(Function) FIG. 1 shows a state in which the semiconductor element 2 is die-bonded to a prescribed position on the substrate 1, and at this time, the wires 8 and 9 are parallel to each other. Therefore, each wire never passes over the post 4.5 and the leads 6.7 connected thereto.

しかし半導体素子２が第３図に示すように規定位置より
ずれてダイボンディングされた場合、ワイヤ９がポスト
４またはこれに連なるリード６の上方を通過するとして
も１、絶縁層１０が存在しているので、ワイヤ９はこの
絶縁層１０の表面に支持され、これをこえて下方に垂れ
下がるようなことはない。そしてこの絶縁層１ｏはポス
ト４に連なるリード６を覆っているので、ワイヤ９はポ
スト４にはもちろんリード６にも接触することはない、
のみならずこのように半導体素子のダイボンディング位
置がずれてもワイヤの接触が防止できることから、その
ダイボンディング位置の精度ゆるくすることもできるよ
うになる。However, if the semiconductor element 2 is die-bonded at a position shifted from the specified position as shown in FIG. Therefore, the wire 9 is supported by the surface of the insulating layer 10 and does not hang down beyond the surface. Since this insulating layer 1o covers the lead 6 connected to the post 4, the wire 9 does not come into contact with the post 4 or even the lead 6.
Furthermore, even if the die bonding position of the semiconductor element shifts, contact of the wire can be prevented, so that the accuracy of the die bonding position can be made looser.

（発明の効果） 以上詳述したようにこの発明によれば、第１の列のポス
トと第２の列のポストとの間に絶縁層を設置し、これに
よって半導体素子のボンディングパットからポストに向
かうワイヤが第２の列のポストまたはこれに連なるリー
ドに接触するのを簡単に防止することができるし、更に
半導体素子のダイボンディング位置を高精度とする必要
もなく、したがってそれだけ工程管理上、許容基準をゆ
るく認定できるので、工程の歩留まりが向上し、生産性
を高めることができるようになるといった効果を奏する
。(Effects of the Invention) As described in detail above, according to the present invention, an insulating layer is provided between the posts in the first row and the posts in the second row, and thereby the bonding pads of the semiconductor element are connected to the posts. It is possible to easily prevent the directed wire from coming into contact with the second row of posts or the leads connected thereto, and there is also no need to make the die bonding position of the semiconductor element highly accurate, which makes process control easier. Since the acceptance criteria can be certified loosely, the yield of the process can be improved and productivity can be increased.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の実施例を示す平面図、第２図は同断
面図、第３図は動作状態を示す平面図、第４図は従来例
を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention, FIG. 2 is a sectional view thereof, FIG. 3 is a plan view showing an operating state, and FIG. 4 is a plan view showing a conventional example.

Claims (1)

【特許請求の範囲】[Claims] 半導体素子のボンディングパットと基板上のポストとを
ワイヤで接続してなる半導体装置において、前記ポスト
を前記半導体素子側に沿って並ぶ第１の列と、前記第１
の列より前記半導体素子から離れている位置に並びかつ
前記第１の列のポストに対して千鳥状に配置されてある
第２の列とによって構成し、前記第１のポストと第２の
列のポストとの間に、前記第１の列のポストに連なるリ
ードを覆う絶縁層を設置してなる半導体装置。In a semiconductor device in which a bonding pad of a semiconductor element and a post on a substrate are connected with a wire, the posts are arranged in a first row along the semiconductor element side;
a second column arranged at a position farther from the semiconductor element than the column and arranged in a staggered manner with respect to the first column of posts, the first column and the second column An insulating layer is provided between the posts in the first row and covers leads connected to the posts in the first row.
JP59248484A 1984-11-24 1984-11-24 Semiconductor device Granted JPS61127140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59248484A JPS61127140A (en) 1984-11-24 1984-11-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59248484A JPS61127140A (en) 1984-11-24 1984-11-24 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS61127140A true JPS61127140A (en) 1986-06-14
JPH0426544B2 JPH0426544B2 (en) 1992-05-07

Family

ID=17178841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59248484A Granted JPS61127140A (en) 1984-11-24 1984-11-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61127140A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02303037A (en) * 1989-05-18 1990-12-17 Mitsubishi Electric Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02303037A (en) * 1989-05-18 1990-12-17 Mitsubishi Electric Corp Semiconductor device

Also Published As

Publication number Publication date
JPH0426544B2 (en) 1992-05-07

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