JP3255896B2 - Semiconductor device with chip-on-chip structure - Google Patents
Semiconductor device with chip-on-chip structureInfo
- Publication number
- JP3255896B2 JP3255896B2 JP26574199A JP26574199A JP3255896B2 JP 3255896 B2 JP3255896 B2 JP 3255896B2 JP 26574199 A JP26574199 A JP 26574199A JP 26574199 A JP26574199 A JP 26574199A JP 3255896 B2 JP3255896 B2 JP 3255896B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor
- parent
- semiconductor chip
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 69
- 239000000523 sample Substances 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、チップ・オン・
チップ構造の半導体装置に関する。The present invention relates to a chip-on-chip
The present invention relates to a semiconductor device having a chip structure.
【０００２】[0002]
【従来の技術】従来から、半導体チップ（親チップ）の
表面に他の半導体チップ（子チップ）の表面を対向させ
た状態で重ね合わせて接合したチップ・オン・チップ構
造の半導体装置がある。このようなチップ・オン・チッ
プ構造の半導体装置では、親チップおよび子チップの表
面にバンプが形成されていて、親チップのバンプに子チ
ップのバンプを接合させることにより、子チップが親チ
ップと所定間隔を開けた状態で接合され、かつ、親チッ
プおよび子チップ間の電気接続が達成される。2. Description of the Related Art Conventionally, there is a semiconductor device having a chip-on-chip structure in which a surface of a semiconductor chip (parent chip) is overlapped and joined with a surface of another semiconductor chip (child chip) facing the surface thereof. In such a chip-on-chip semiconductor device, bumps are formed on the surfaces of the parent chip and the child chip, and the child chip is bonded to the parent chip by bonding the bumps of the child chip to the bumps of the parent chip. The chips are joined at a predetermined interval, and the electrical connection between the parent chip and the child chip is achieved.
【０００３】[0003]
【発明が解決しようとする課題】親チップおよび子チッ
プは、互いに接合される前であれば、それぞれのバンプ
にテストプローブを押し当てて動作確認のためのテスト
を行うことができる。また、親チップと子チップとが接
合された後であっても、親チップの周縁付近に設けられ
た外部接続用のパッドにテストプローブを押し当てるこ
とにより、半導体装置全体の動作確認のためのテストを
行うことはできる。しかしながら、親チップと子チップ
とが接合された後に、親チップまたは子チップのみの動
作を確認することはできなかった。また、親チップと子
チップとの接続状態のみを確認することはできなかっ
た。Before the parent chip and the child chip are joined to each other, a test for confirming the operation can be performed by pressing a test probe against each bump. Further, even after the parent chip and the child chip are joined, by pressing the test probe against an external connection pad provided near the periphery of the parent chip, it is possible to confirm the operation of the entire semiconductor device. You can do tests. However, after the parent chip and the child chip have been joined, the operation of only the parent chip or the child chip cannot be confirmed. Further, it was not possible to confirm only the connection state between the parent chip and the child chip.
【０００４】そこで、この発明の目的は、上述の技術的
課題を解決し、第１の半導体チップと第２の半導体チッ
プとを接合した後であっても、各半導体チップ単体での
機能を確認するためのテストや第１の半導体チップと第
２の半導体チップとの接続状態のみを確認するためのテ
ストなどを行うことができるチップ・オン・チップ構造
の半導体装置を提供することである。Accordingly, an object of the present invention is to solve the above-mentioned technical problem, and to confirm the function of each semiconductor chip alone even after the first semiconductor chip and the second semiconductor chip are joined. It is an object of the present invention to provide a semiconductor device having a chip-on-chip structure capable of performing a test for performing the test and a test for confirming only a connection state between the first semiconductor chip and the second semiconductor chip.
【０００５】[0005]
【課題を解決するための手段および発明の効果】上記の
目的を達成するための請求項１記載の発明は、第１の半
導体チップと第２の半導体チップとが互いに表面を対向
させた状態で重ね合わせて接合されたチップ・オン・チ
ップ構造の半導体装置であって、上記第１の半導体チッ
プの表面において上記第２の半導体チップを接合するた
めに設定された接合領域内に形成され、上記第１の半導
体チップおよび上記第２の半導体チップを所定間隔を開
けた状態で結合するとともに、上記第１および第２の半
導体チップ間の電気接続を達成するためのバンプと、上
記第１の半導体チップの表面において上記バンプに接続
されて形成され、一端が上記接合領域の外方に引き出さ
れた導電性の延設部（好ましくは、バンプと同材料から
なるもの。）とを含み、上記延設部が第１の半導体チッ
プまたは第２の半導体チップのみの動作確認を行うこと
ができることを特徴とするチップ・オン・チップ構造の
半導体装置である。Means for Solving the Problems and Effects of the Invention According to the first aspect of the present invention, there is provided a semiconductor device comprising: a first semiconductor chip and a second semiconductor chip having surfaces facing each other; A semiconductor device having a chip-on-chip structure which is overlapped and joined, wherein said semiconductor device is formed in a joining region set for joining said second semiconductor chip on a surface of said first semiconductor chip, A bump for connecting the first semiconductor chip and the second semiconductor chip at a predetermined interval, and for establishing electrical connection between the first and second semiconductor chips; A conductive extension (preferably made of the same material as the bump), which is formed on the surface of the chip so as to be connected to the bump and has one end drawn out of the bonding region; Look, the extended portion is the first semiconductor chip
To check the operation of only the second semiconductor chip
It is a semiconductor device of chip-on-chip structure, wherein a can.
【０００６】この発明によれば、第１の半導体チップの
バンプには、一端が第２の半導体チップの接合領域外ま
で引き出された延設部が接続されている。これにより、
第１の半導体チップと第２の半導体チップとが接合され
た後であっても、延設部の接合領域の外方に引き出され
た部分にテストプローブを押し当てて、第１の半導体チ
ップまたは第２の半導体チップのみの動作確認を行うこ
とができる。また、第１の半導体チップと第２の半導体
チップとの接続確認を行うことができる。According to the present invention, the extending portion whose one end is drawn out of the bonding region of the second semiconductor chip is connected to the bump of the first semiconductor chip. This allows
Even after the first semiconductor chip and the second semiconductor chip have been joined, the test probe is pressed against a portion of the extension portion that is drawn out of the joining region, and the first semiconductor chip or The operation of only the second semiconductor chip can be confirmed. Further, the connection between the first semiconductor chip and the second semiconductor chip can be confirmed.
【０００７】なお、上記延設部は、上記バンプと一体に
形成されていることが好ましい。この場合、上記バンプ
が、上記接合領域の境界部に跨がった状態に形成され
て、当該バンプと上記第２の半導体チップとの接合部分
以外を上記延設部としてもよい。It is preferable that the extending portion is formed integrally with the bump. In this case, the bump may be formed so as to straddle a boundary portion of the bonding region, and a portion other than a bonding portion between the bump and the second semiconductor chip may be the extended portion.
【０００８】[0008]
【発明の実施の形態】以下では、この発明の実施の形態
を、添付図面を参照して詳細に説明する。図１は、この
発明の一実施形態に係る半導体装置の概略構成を示す図
解的な断面図であり、図２は、その平面図である。この
半導体装置は、第１の半導体チップとしての親チップ１
の表面１１に、第２の半導体チップとしての子チップ２
を重ね合わせて接合した、いわゆるチップ・オン・チッ
プ構造を有している。Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is an illustrative sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view thereof. This semiconductor device includes a parent chip 1 as a first semiconductor chip.
Child chip 2 as a second semiconductor chip on surface 11 of
Have a so-called chip-on-chip structure in which are overlapped and bonded.
【０００９】親チップ１および子チップ２は、たとえば
シリコンチップからなっている。親チップ１の表面１１
は、親チップ１の基体をなす半導体基板においてトラン
ジスタなどの機能素子が形成された活性表層領域側の表
面であり、最表面は、たとえば窒化シリコンで構成され
る表面保護膜で覆われている。この表面保護膜上には、
たとえば中央部に子チップ２の接合領域１２が設定され
ており、この接合領域１２には、子チップ２との接続の
ための複数個（この実施形態では６個）のバンプＢＭが
隆起して形成されている。バンプＢＭは、たとえば金、
プラチナ、銀、パラジウムまたはイリジウムなどの耐酸
化性の金属材料で構成されている。また、表面保護膜上
において接合領域１２の周囲には、外部接続用の複数の
パッド１３が露出して配置されている。The parent chip 1 and the child chip 2 are made of, for example, silicon chips. Surface 11 of parent chip 1
Is a surface on the active surface layer region side on which a functional element such as a transistor is formed on a semiconductor substrate serving as a base of the parent chip 1, and the outermost surface is covered with a surface protective film made of, for example, silicon nitride. On this surface protective film,
For example, a bonding region 12 of the child chip 2 is set at the center, and a plurality of (six in this embodiment) bumps BM for connection with the child chip 2 are raised in the bonding region 12. Is formed. The bump BM is, for example, gold,
It is made of an oxidation-resistant metal material such as platinum, silver, palladium or iridium. A plurality of pads 13 for external connection are exposed and arranged around the bonding region 12 on the surface protective film.
【００１０】子チップ２は、この子チップの表面２１を
親チップ１の表面１１に対向させた、いわゆるフェース
ダウン方式で親チップ１に接合されている。子チップ２
の表面２１は、子チップ２の基体をなす半導体基板にお
いてトランジスタなどの機能素子が形成された活性表層
領域側の表面であり、最表面は、たとえば窒化シリコン
からなる表面保護膜で覆われている。この表面保護膜上
には、親チップ１のバンプＢＭに対向する位置にそれぞ
れバンプＢＳが形成されている。バンプＢＳは、たとえ
ば金、プラチナ、銀、パラジウムまたはイリジウムなど
の耐酸化性の金属材料で構成されている。子チップ２
は、バンプＢＳがそれぞれ対向する親チップ１のバンプ
ＢＭに接続されることによって、親チップ１の表面１１
との間に所定間隔を保持した状態で支持されるととも
に、親チップ１と電気的に接続されている。The child chip 2 is joined to the parent chip 1 by a so-called face-down method in which the surface 21 of the child chip faces the surface 11 of the parent chip 1. Child chip 2
Surface 21 is a surface on the active surface layer region side on which a functional element such as a transistor is formed on a semiconductor substrate serving as a base of the sub chip 2, and the outermost surface is covered with a surface protective film made of, for example, silicon nitride. . On the surface protection film, bumps BS are formed at positions facing the bumps BM of the parent chip 1 respectively. The bump BS is made of an oxidation-resistant metal material such as gold, platinum, silver, palladium, or iridium. Child chip 2
Are connected to the bumps BM of the parent chip 1 facing each other, so that the surface 11 of the parent chip 1
And is electrically connected to the parent chip 1 while maintaining a predetermined interval between the two.
【００１１】親チップ１の各バンプＢＭには、バンプＢ
Ｍから側方に延びて接合領域１２外まで引き出された延
設部１４が一体に形成されている。言い換えれば、親チ
ップ１のバンプＢＭは、接合領域１２の境界部に跨がっ
た状態に長く形成されている。これにより、親チップ１
と子チップ２とが接合された後であっても、図１に示す
ように、延設部１４の接合領域１２の外方に引き出され
た部分にテストプローブＰを押し当てて、親チップ１ま
たは子チップ２のみの動作確認を行うことができる。ま
た、親チップ１と子チップ２との接続確認を行うことが
できる。Each bump BM of the parent chip 1 has a bump B
An extension 14 extending laterally from M and extending to the outside of the joining region 12 is integrally formed. In other words, the bump BM of the parent chip 1 is formed to be long over the boundary of the bonding region 12. Thereby, the parent chip 1
Even after the bonding of the parent chip 1 and the child chip 2, as shown in FIG. 1, the test probe P is pressed against a portion of the extension portion 14 pulled out of the bonding region 12, and Alternatively, the operation of only the child chip 2 can be confirmed. Further, the connection between the parent chip 1 and the child chip 2 can be confirmed.
【００１２】さらに、親チップ１の外部接続用パッド１
３にテストワイヤを接続するか、またはテストプローブ
を押し当てて、この半導体装置全体の動作確認を行うこ
ともできる。なお、外部接続用パッド１３は、バンプＢ
Ｍと直接には接続されておらず、この外部接続用パッド
１３にテストプローブＰを押し当てて子チップ２の動作
確認を行うことはできない。また、この半導体装置の完
成品においては、たとえば、親チップ１がリードフレー
ムのアイランドにマウントされ、外部接続用パッド１３
がボンディングワイヤによりリード端子に接続されてい
る。Further, the pad 1 for external connection of the parent chip 1
The operation of the entire semiconductor device can be confirmed by connecting a test wire or pressing a test probe to the semiconductor device 3. The external connection pad 13 is connected to the bump B
Since it is not directly connected to M, it is impossible to check the operation of the sub chip 2 by pressing the test probe P against the external connection pad 13. In a completed product of this semiconductor device, for example, the parent chip 1 is mounted on an island of a lead frame and the external connection pads 13 are mounted.
Are connected to the lead terminals by bonding wires.
【００１３】この発明の一実施形態について説明した
が、この発明は、他の形態で実施することもできる。た
とえば、親チップ１および子チップ２は、いずれもシリ
コンからなるチップであるとしたが、シリコンの他に
も、化合物半導体（たとえばガリウム砒素半導体など）
やゲルマニウム半導体などの他の任意の半導体材料を用
いた半導体チップであってもよい。この場合に、親チッ
プ１の半導体材料と子チップ２の半導体材料は、同じで
もよいし異なっていてもよい。Although one embodiment of the present invention has been described, the present invention can be embodied in other forms. For example, although the parent chip 1 and the child chip 2 are both chips made of silicon, in addition to silicon, a compound semiconductor (for example, a gallium arsenide semiconductor or the like)
A semiconductor chip using any other semiconductor material such as silicon or germanium semiconductor may be used. In this case, the semiconductor material of the parent chip 1 and the semiconductor material of the child chip 2 may be the same or different.
【００１４】その他、特許請求の範囲に記載された事項
の範囲内で、種々の設計変更を施すことが可能である。In addition, various design changes can be made within the scope of the matters described in the claims.
【図１】この発明の一実施形態に係る半導体装置の概略
構成を示す図解的な断面図である。FIG. 1 is an illustrative sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention.
【図２】上記半導体装置の平面図である。FIG. 2 is a plan view of the semiconductor device.
１ 親チップ（第１の半導体チップ） １１ 親チップの表面（第１の半導体チップの表面） １２ 接合領域 １４ 延設部 ２ 子チップ（第２の半導体チップ） ２１ 子チップの表面（第２の半導体チップの表面） ＢＭ バンプ Ｐ テストプローブ DESCRIPTION OF SYMBOLS 1 Parent chip (1st semiconductor chip) 11 Surface of parent chip (surface of 1st semiconductor chip) 12 Joining area 14 Extension part 2 Child chip (2nd semiconductor chip) 21 Surface of child chip (2nd surface) Semiconductor chip surface) BM Bump P Test probe
Claims (1)
とが互いに表面を対向させた状態で重ね合わせて接合さ
れたチップ・オン・チップ構造の半導体装置であって、 上記第１の半導体チップの表面において上記第２の半導
体チップを接合するために設定された接合領域内に形成
され、上記第１の半導体チップおよび上記第２の半導体
チップを所定間隔を開けた状態で結合するとともに、上
記第１および第２の半導体チップ間の電気接続を達成す
るためのバンプと、 上記第１の半導体チップの表面において上記バンプに接
続されて形成され、一端が上記接合領域の外方に引き出
された導電性の延設部とを含み、 上記延設部が第１の半導体チップまたは第２の半導体チ
ップのみの動作確認を行うことができる ことを特徴とす
るチップ・オン・チップ構造の半導体装置。1. A semiconductor device having a chip-on-chip structure in which a first semiconductor chip and a second semiconductor chip are overlapped and joined with their surfaces facing each other, wherein the first semiconductor chip is The first semiconductor chip and the second semiconductor chip are formed in a bonding area set for bonding the second semiconductor chip on the surface of the chip, and are bonded at a predetermined interval, A bump for achieving an electrical connection between the first and second semiconductor chips; and a bump formed on a surface of the first semiconductor chip so as to be connected to the bump, and one end thereof being drawn out of the bonding region. and includes a conductive extended portion of the guide, said extension portion is a first semiconductor chip or the second semiconductor switch
A semiconductor device having a chip-on-chip structure, capable of confirming the operation of only a chip.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26574199A JP3255896B2 (en) | 1999-09-20 | 1999-09-20 | Semiconductor device with chip-on-chip structure |
| KR1020000054905A KR100752884B1 (en) | 1999-09-20 | 2000-09-19 | Chip-on-chip semiconductor device |
| TW089119299A TW490789B (en) | 1999-09-20 | 2000-09-20 | Semiconductor device having chip-on-chip structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26574199A JP3255896B2 (en) | 1999-09-20 | 1999-09-20 | Semiconductor device with chip-on-chip structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001094037A JP2001094037A (en) | 2001-04-06 |
| JP3255896B2 true JP3255896B2 (en) | 2002-02-12 |
Family
ID=17421362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26574199A Expired - Fee Related JP3255896B2 (en) | 1999-09-20 | 1999-09-20 | Semiconductor device with chip-on-chip structure |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP3255896B2 (en) |
| KR (1) | KR100752884B1 (en) |
| TW (1) | TW490789B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007266078A (en) | 2006-03-27 | 2007-10-11 | Fujitsu Ltd | Semiconductor device, semiconductor device having chip-on-chip structure, and method for manufacturing semiconductor device |
| JP4910512B2 (en) | 2006-06-30 | 2012-04-04 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| KR102190382B1 (en) | 2012-12-20 | 2020-12-11 | 삼성전자주식회사 | Semiconductor package |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07211758A (en) * | 1994-01-14 | 1995-08-11 | Fujitsu Ltd | Method for manufacturing semiconductor device |
-
1999
- 1999-09-20 JP JP26574199A patent/JP3255896B2/en not_active Expired - Fee Related
-
2000
- 2000-09-19 KR KR1020000054905A patent/KR100752884B1/en not_active Expired - Fee Related
- 2000-09-20 TW TW089119299A patent/TW490789B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010039902A (en) | 2001-05-15 |
| JP2001094037A (en) | 2001-04-06 |
| TW490789B (en) | 2002-06-11 |
| KR100752884B1 (en) | 2007-08-28 |
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