JPS61125233A - High-speed dpcm circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a DI/CM circuit used in an image band compression device, particularly a 3-input 2-output digital-to-digital converter (hereinafter referred to as a 3-input 2-output D/D converter). ) and a high-speed DPCM circuit using an adder that adds these two outputs,
The present invention relates to a high-speed DPCM circuit that increases the calculation speed for prediction.

When performing band compression using the above-mentioned high-speed DPCM circuit, it is desirable that the calculation speed for prediction be high.

[Conventional technology]

Figure 2 shows high-speed DPCM when the prediction coefficient is 1/2 of the conventional example.
FIG. 2 is a block diagram of the circuit.

In the figure, 1 is a 3-input 2-output D/D converter, 2 is an adder, and 3.
7 is a delay element FF, 4 is a quantizer, 5 is an adder,
6, 8.9 indicates a multiplier that multiplies the prediction coefficient by 1/2.

D P CM 11 using 2-input subtractor for prediction
Instead of 11 paths, a 3-input 2-output D/D converter and an addition 1γ
There is a high-speed DPCM encoder for which the present applicant applied for a patent on August 30, 1980, in Japanese Patent Application No. 59-181061, as an example of a high-speed DPCM encoder.

This embodiment is shown in FIG. 2, which is considered as a conventional example.

In the case of FIG. 2, the DPCM signal output from the quantizer 4 is multiplied by the prediction coefficient 1/2 in the multiplier 8, and the 3-input 2-output D
The value inputted to /D conversion ill and output from FF7 one sampling period ago is multiplied by the prediction coefficient 1/2 in multiplier 9, and inputted to 3-input 2-output D/D converter l, The 3-input 2-output D/D converter outputs an IDPCM signal, realizing a high-speed DPCM circuit that is faster than a DPCM circuit converter that uses a 2-input subtracter for prediction.

[Problem that the invention seeks to solve]

However, in this case, the critical path that determines the processing speed is the 3-input 2-output D/D converter 1. Adder 2. This becomes a loop of the FF 3, the quantizer 41, and the multiplier 8, and if the operating speed of the multiplier 8 is slow, there is a problem that the calculation speed for prediction is slow.

[Means for solving problems]

The above problem is that the output side is multiplied by a prediction coefficient and then quantized (1). , the first multiplier multiplies the output of the first adder by a prediction coefficient, and this output is delayed by the first delay element. A predicted value detection loop that inputs the predicted value to the first adder and detects the predicted value; the first input is a signal obtained by dividing the PCM signal by the preil+coefficient; The output of the first delay element is inputted to the input of , and a second adder that adds the two outputs of each is connected to the output of a three-input two-output digital-to-digital converter that has two outputs. This problem is solved by the high-speed DI) CM circuit of the present invention, which delays DI (DI) by a second delay element and inputs this output to the quantizer.

[Effect]

In the present invention, instead of the quantizer 4 in FIG. 2, the output of the second delay element (FF3 in FIG. 2) of the conventional high-speed DPCM circuit is multiplied by a prediction coefficient and then a landscaped DPCM signal is generated. A quantizer with integrated functions is installed, and instead, the output of the quantizer and the value before one sampling period (F in Fig. 2) are installed.
PCM that does not multiply the prediction coefficient (output of F7) and also inputs it
The signal is divided by the prediction coefficient and input to a 3-input 2-output D/D converter, and if the operating speed of the multiplier is faster than the operating speed of the 3-input 2-output D/D converter, the critical path of the multiplier is The calculation speed for prediction is improved by the amount of delay.

〔Example〕

FIG. 1 is a block diagram of a high speed r) PCM circuit in the case of a prediction coefficient of 1/2 according to an embodiment of the present invention.

In the figure, 10 indicates a multiplier that divides by 1/2 of the prediction coefficient, and 11 indicates a quantizer that has an integrated function of emitting a quantized DPCM signal after multiplying by 1/2 of the prediction coefficient. The same code indicates the same function.

The difference between Fig. 1 and Fig. 2 is that a quantizer 11 is installed on the output of FF3 and is multiplied by 172, so instead, the output of quantizer 4 and the output of FF7 are l/
2 is not multiplied by -υ, and the input PCM signal is divided by 1/2 by the multiplier IO and inputted to the 3-input 2-output D/D converter 1.

By doing this, when the operating speed of the multiplier 6 is faster than the operating speed of the 3-input 2-output D/D converter 1, the critical path is the 3-input 2-output D/D converter 1, the adder 2. FF3
．． Since the loop consists of the quantizer II, the calculation speed for prediction can be increased by the delay of the multiplication H8 in FIG. 2 compared to the conventional example.

Although the above description has been made for the case where the prediction coefficient is 1/2, it is of course possible to increase the calculation speed for prediction in other cases as well.

Also, when the positions of FF 3 and quantizer 11 are reversed, when the delay of multiplier 6 is smaller than the sum of the delays of 3-input 2-output D/D converter 1 and quantizer 11, compared to the conventional example. The calculation speed for prediction can be improved by the delay of the multiplier 8 shown in FIG.

Alternatively, if l=' F 7 and the position of multiplier 6 are reversed, when the delay of multiplier 6 is smaller than the delay of quantizer 11, the prediction is made by the delay of multiplier 8 in FIG. 2 compared to the conventional example. The calculation speed for can be improved.

〔Effect of the invention〕

As explained in detail above, according to the present invention, there is an effect that the calculation speed for prediction can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a high-speed r') PCM circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional high-speed DPCM circuit. In the figure, l is a 3-input 2-output digital-to-digital converter, 2.5 is an adder, and 3.7 is an FF. 4.11 is a quantizer, and 6.8.9.10 is a multiplier.

Claims (1)

[Claims] The output side includes a quantizer integrating a function of generating a quantized DPCM signal after multiplication by a prediction coefficient, a first adder, a first multiplier, and a first delay element, and 1
multiplying the output of the first adder by a prediction coefficient with a multiplier;
A predicted value detection loop that delays this output with the first delay element and inputs it to the first adder together with the output of the quantizer to detect a predicted value, and a predicted PCM signal is input to the first input. The output of the quantizer is input to the second input, the output of the first delay element is input to the third input, and the signal divided by the coefficient is input to the second input, and the output of the first delay element is input to the third input.
A second adder that adds these two outputs is connected to the output of the three-input, two-output digital-to-digital converter, and this output is delayed by a second delay element, and this output is A high-speed DPCM circuit characterized in that the input is input to a converter.