JPH0239138B2 - SABUNFUGOKI - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed differential pulse code modulation (DPCM) encoder that is capable of increasing its operating speed. The DPCM encoder according to the present invention includes:
For example, it can be used in an image band compression device, etc.
When performing such band compression, it is strongly desired that the operating speed of the DPCM encoder can be increased.

[Prior art] The block configuration of the conventional DPCM encoder is
As shown in the figure. In FIG. 4, 1 is a subtractor, 2
is a delay element consisting of a flip-flop, 3 is a quantizer, 4 is an adder, and 5 is a prediction coefficient P (for example, 1/2)
A multiplier 6 is a delay element consisting of a flip-flop.

The operation of the DPCM encoder of FIG. 4 will be explained below. A subtracter 1 calculates the difference between an input PCM signal and a predicted value, this is delayed by a delay element 2, and quantized by a quantizer 3 to output a DPCM signal.
On the other hand, this DPCM signal is also input to adder 4,
The adder 4 adds the predicted value one sampling period before. A multiplier 5 multiplies the output of the adder 4 by a prediction coefficient P to obtain a predicted value, and a delay element 6 delays the predicted value to input the predicted value one sampling period earlier to the adder. and add it with the DPCM signal.

[Problem that the invention seeks to solve]

The conventional DPCM encoder has a problem in that its operating speed is determined by the critical loop of the delay element 2, quantizer 3, adder 4, multiplier 5, and subtracter 1, and the operating speed is slow. Particularly when dealing with image signals, one sampling period is, for example, about 100 nsec, so it is desired that the DPCM encoder be made even faster.

A high-speed DPCM encoder proposed in patent application 1985-8504 by the present applicant as a DPCM encoder that achieves this speed increase.
There is a DPCM encoder. The block configuration of this high-speed DPCM encoder is shown in FIG. In FIG. 5, blocks with the same reference numerals as in FIG. 4 have the same functions as the blocks in FIG. Differences from the conventional type shown in FIG.
The DPCM signal output from the 3-input 2-output D/D converter 7 is inverted through the multiplier 9 and input to one of the input terminals of the 3-input 2-output D/D converter 7. The output signal of the delay element 6 is inverted and guided through the multiplier 10 to one input terminal, and the PCM signal is input to the remaining input terminal. Note that the prediction coefficient of the multipliers 9 and 10 is P, and a specific value of P is, for example, 1/2.

In the DPCM encoder shown in Fig. 5, the quantizer 3
The output DPCM signal is sent to the multiplier 9 using the prediction coefficient P
is multiplied and input to the 3-input 2-output D/D converter 7, and the value one sampling period before, which is the output of the delay element 6, is multiplied by the prediction coefficient P in the multiplier 10 and input into the 3-input 2-output D/D converter 7.
It is input to the input 2 output D/D converter 7, and the difference between it and the PCM signal input to the 3 input 2 output D/D converter 7 is converted into 2 outputs, and this output is input to the adder 8. The signals are added and input to a quantizer 3 via a delay element 2, and a quantized DPCM signal is output. In the case of the DPCM encoder shown in FIG. 5, the critical paths that determine the operating speed are the delay element 2, the quantizer 3, the multiplier 9, the 3-input 2-output D/D converter 7, and the adder 8. Comparing with the conventional critical path shown in Figure 3, adder 8 and adder 4 have almost the same operating speed, and 3-input 2-output D/D converter 7 has a faster operating speed than subtracter 1. , the speed of the device can be increased.

Note that the encoder shown in FIG. 4 and the encoder shown in FIG. 5 operate in an equivalent manner in principle. That is,
The currently input PCM signal is a, the input signal to the delay element 2 is e, and the DPCA output from the quantizer 3 is
If the signal is c and the output signal of the delay element 6 is b, then
In Figure 4, the relationship is e=a-P(b+c)...(1), while in Figure 5, the relationship is e=a-Pxb-Pxc...(2), ( It is clear from equations 1) and (2) that both are equivalent circuits.

Although the DPCM encoder shown in FIG. 5 is faster than the one shown in FIG. 4, even higher speeds are desired.

Therefore, an object of the present invention is to further increase the speed of the DPCM encoder.

[Means for solving problems]

In order to solve the above-mentioned problems, as shown in the principle block diagram according to the present invention in FIG.
input terminals and two output terminals, a pulse code modulated signal is guided to the first input terminal, and the three
Performs full addition for each digit of the signals input from the input terminals, and for each digit, the carry output and the addition result are
The two output signals of the 3-input, 2-output digital-to-digital converter 101 and the 3-input, 2-output digital-to-digital converter are added for each digit, and the carry output of the addition result is a carry up by one digit. a first adder 102 that adds as an addition input;
quantizer 10 to which the addition output signal of the adder is guided.
3, generating a quantized differential pulse code modulation signal from the addition output signal as a first output signal;
a first output signal that delays the first output signal of the quantizer by one sampling period; a delay element 104; a second delay element 105 for delaying a second output signal of the quantizer by one sampling period; the output signal is a second input of the three-input two-output digital-to-digital converter; a loop including an adder that adds the output signal of the first delay element and a signal delayed by one sampling period after multiplying the output signal of the first delay element by a prediction coefficient; a predicted value detection loop 106 for calculating a predicted value, and a 3-input 2-output digital-to-digital converter which multiplies the output signal of the adder of the predicted value detection loop by the square of the prediction coefficient and then delays it by one sampling period. A circuit 107 is provided leading to a third input terminal of.

In a preferred embodiment of the present invention, the above-mentioned quantizer 103 can be implemented by either ROM, RAM or PLA.

[Effect]

The high-speed operation type DPCM encoder of the present invention has the function of reversing the arrangement order of the quantizer and delay element compared to the conventional type and further generating a quantized DPCM signal in the quantizer, and the quantization A function of multiplying the DPCM signal by a prediction coefficient is provided, so that its critical path is connected to the second delay element 105, 3 input 2.
The output is determined by the output D/D converter 101, the adder 102, and the quantizer 103.
Compared to the DPCM encoder shown in the figure, the multiplier 9 in the critical path is omitted, and as a result, the operating speed is increased by the delay time caused by the multiplier 9.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing a high-speed operation type DPCM encoder as an embodiment of the present invention. Second
In the figure, a 3-input, 2-output D/D converter 7 receives an 8-bit PCM signal at one of its input terminals and sends two output signals to an adder 8. Adder 8 sends its addition output signal to quantizer 11 . The quantizer 11 includes a quantization function section 111 that has a function of generating a quantized DPCM signal from the inputted addition output signal, and a multiplication function section 112 that multiplies the quantized DPCM signal by a prediction coefficient P. This quantizer 11 is, for example, a ROM or
It can be configured with a semiconductor storage device such as RAM, or a PLA (program logic array).

The quantized DPCM signal from the quantization function section 111 is guided to a delay element 12 consisting of a flip-flop that delays the input signal by one sampling period. On the other hand, the output signal from the multiplication function section 112 is guided to a delay element 13 consisting of a flip-flop which also delays the input signal by one sampling period. led to one of the input terminals. of delay element 12
The DPCM output signal is sent to a transmitting device (not shown) and is also guided to the addition input terminal of the adder 4.

A signal obtained by multiplying the output signal of the adder 4 by a prediction coefficient P by a multiplier 5 and delaying the value by one sampling period by a delay element 6 consisting of a flip-flop is led to the other addition input terminal of the adder 4. As a result, the adder 4 outputs a predicted value. The adder 4, multiplier 5, and delay element 6 constitute a predicted value detection loop. The predicted value from the adder 4 is multiplied by the prediction coefficient P ² in the multiplier 14 and then becomes 1.
The signal is led to the remaining input terminal of the 3-input, 2-output D/D converter 7 via a delay element 15 consisting of a flip-flop that delays the sampling period.

Figure 3 shows the 3-input 2-output D/D in Figure 2.
Detailed circuit configurations of converter 7 and adder 8 are shown. In FIG. 2, 7a to 7h and 8a to 8i are a 3-input 2-output D/D converter 7 and an adder 8, respectively.
This is a full adder that makes up the . In this example
The PCM signal is 8 bits A7-A0, and the 7-bit output signals from delay elements 13 and 15 are B6-B0 and C6-C0, respectively. 2 inputs 1
The output full adders 7a to 7h each receive the signals A0 to A7 at their carry inputs, and the inverted signals B6 to B0 and C6 to C0 to their two inputs, respectively. However, MSB full adder 7h
The signals of B6 and C6 are input to. Full adder 7a
The outputs of 7h to 7h are input to full adders 8a to 8i, however, one input of LSB full adder 8a is connected to ground, and an "H" level is applied to its carry input. Also, full adder 7a~
The carry output of 7h is input to full adders 8b to 8i, respectively. The carry outputs of full adders 8a to 8h are input to full adders 8b to 8i, respectively, and their outputs are input to quantizer 11.

Comparing the device of this embodiment described above with the device of FIG. 5 described above, the quantizer 11 of FIG. 2 integrates the functions of the quantizer 3 and multiplier 9 of FIG. be placed on the input side of the second
The difference is that the multiplier 14 shown in the figure is arranged on the input side of the delay element 15, and the prediction coefficient is ^P2 , and the functions of the multiplier 5 and the multiplier 10 of FIG. 5 are integrated.

With this configuration, the critical path of the DPCM encoder in FIG.
Output D/D converter 7, adder 8 and quantizer 1
1, and therefore the DPCM in Figure 5
Compared to the encoder, the multiplier 9 is omitted. As a result, the operating speed is increased by the delay time that would have occurred in the multiplier 9 when the operating speeds of the quantizer 3 and the quantizer 11 were considered to be the same.

Various modifications are possible in carrying out the invention. For example, in the device of this embodiment, the quantizer 11
and delay elements 12 and 13 consisting of flip-flops.
Although explained as separate blocks, the delay element 1 is not limited to this, for example, if a registered ROM that is integrated with a flip-flop is used, the delay element 1
It is not necessary to separately provide a quantizer for 2 and 13, and it is also possible to include the function in the quantizer.

〔Effect of the invention〕

According to the present invention, it is possible to further increase the operating speed of the DPCM encoder.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, and Fig. 2 is a high-speed operation type as an embodiment of the present invention.
A block diagram showing the DPCM encoder, Figure 3 is
A detailed block diagram of the 3-input 2-output D/D converter 7 and adder 8 in the figure, FIG.
Block Diagram of DPCM Encoder FIG. 5 is a block diagram of a high-speed operation type DPCM encoder previously proposed by the applicant of the present invention. 1... Subtractor 1, 2, 6, 12, 13, 15... Delay element, 3, 11... Quantizer, 4... Adder, 5,
9, 10, 14... Multiplier, 7... 3 inputs 2 outputs D/
D converter, 8...adder.

Claims (1)

[Claims] 1. Having three input terminals and two output terminals,
A pulse code modulation signal is introduced to the first input terminal, and the signals inputted from the three input terminals are fully added for each digit, and two outputs are produced for each digit: a carry output and an addition result. A 3-input, 2-output digital-to-digital converter 101 adds the two output signals of the 3-input, 2-output digital to digital converter for each digit, and the carry output of the addition result is a carry-addition of one digit higher. a first adder 102 that adds as input; a quantizer 103 to which the addition output signal of the first adder is guided; and a second output signal obtained by multiplying the quantized differential pulse code modulated signal by a prediction coefficient, the first output signal of the quantizer is delayed by one sampling period. a first delay element 104; a second delay element 105 for delaying the second output signal of the quantizer by one sampling period; an adder that adds the output signal of the first delay element and a signal delayed by one sampling period after multiplying the output signal of the first delay element by a prediction coefficient; Predicted value detection loop 1 to obtain a predicted value using a loop including
06, and a circuit that multiplies the output signal of the adder of the predicted value detection loop by the square of the prediction coefficient, delays it by one sampling period, and leads the signal to the third input terminal of the three-input, two-output digital-to-digital converter. 107, a differential encoder comprising: 2 The quantizer 11 is ROM, RAM, or
The differential encoder according to claim 1, which is configured by any one of PLA.