JPS61124982A - Pattern expansion - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a pattern enlarging method for enlarging and outputting pattern information stored in a storage means.

[Prior Art] Conventionally, when displaying or printing out different character patterns, patterns of desired character sizes are stored for each character type, and as needed, for example, in the case of headings, large patterns are stored. It was displayed or memorized as a pattern. Therefore, a large pattern storage area was required.

[Objective] The present invention has been made in view of the problems of the prior art described above, and provides a pattern enlarging method that can enlarge and output pattern information of different sizes by simply storing a pattern of a single shape. The purpose is to make suggestions.

Examples] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment according to the present invention, in which 1 is a CPU that controls the entire control, 2 is a page memory that stores patterned display information for one page, and 3 is a page Dynamic memory access controller (hereinafter referred to as DMAC) reads display information from the memory 2 and sets it in the latch register 5; 5 is a latch register that holds information read from the page memory 2; 6 is a latch register 5;
A P/S register 7 converts the parallel read information from the P/S register 6 into parallel to serial and outputs it, and 7 a horizontal clock (H3YNC) signal 12 that outputs the horizontal clock (H3YNC) signal 12 indicating the timing at which the output device 20 receives the display information from the P/S register 6. A clock generation circuit, 8 is an N-ary counter that divides the horizontal clock signal 12, 9 is an N-ary data register that holds the frequency division rate of the N-ary counter 8 and outputs it to the N-ary counter 8, and 10 is a P/S.
A shift clock output section 11 outputs the shift clock of the register 6, and a vertical clock generation circuit 11 outputs the row change timing of the image signal 14 to be outputted to the output device 20.

The operation of this embodiment will be described below with reference to the flowchart in FIG.

In the following explanation, a CRT display device is used as an output device, and one byte of display data is read out and set in the latch register 5.

First, in Sl, the CPU sets the first read address from the page memory 2 to the DMAC 5, and then in <32, it generates the 1's complement of this n according to the pattern enlargement magnification n.
Set in the hexadecimal data register. As a result, the N-adary counter 8 divides the frequency of the horizontal clock signal 12 into a period of 1/n, and the P/S register 6 shifts the set data according to this frequency-divided clock, resulting in a substantially horizontal The output changes every n clock signals, which means that the pattern information read from the page memory is substantially multiplied by 1 in the horizontal direction. This enlargement magnification is specified according to a specified value preset in a display map register (not shown) or the like.

Then, in S3, the DMAC 5 reads one byte of data from the page memory 2 according to the address value specified by the CPUI, and stores it in the latch register 5. And continuation<S4
Check whether there is output data in the P/S register 6 with
When there is no output data, the process advances to S5, and the data stored in the latch register 5 is set in the P/S register 6.

When the data in the latch register 5 is set in the P/S register 6, the DMAC 5 completes scanning for one line, and if the vertical clock signal 11 is not output from the vertical clock generation circuit 11 (S6 to N), the DMAC 5 automatically scans one line. Then, the pattern data at the next address of the page memory is read out and stored in the latch register 5 (S3), and waits until the P/S register 6 becomes empty (S4).

If there is data in the P/S register 6 in S4, the image information 14 is sequentially output in accordance with the shift clock from the shift clock output section 10 as shown in S7.

Further, when scanning of one line is completed in S6, that is, when the horizontal clock signal 12 is outputted for one line, this is detected by the vertical clock generation circuit 11, and the vertical clock signal (VSYNC) 13 is outputted to the output device 20. with DMAC
5 and cptri. Notification to the CPUI is performed by an interrupt request, and upon receiving this interrupt request, the CPU advances to step 310 and checks whether or not all output for one page has been completed. When the output for one page has been completed, the process returns to Sl and repeats the display of the same page. If the output device is a printer or the like, and the output data for the next page is stored in the page memory 2, Execute output of image data from the first address of the next page. If the output data of the next page is not stored, wait for the output data of the next page to be stored and execute the output process of this stored data. do it.

If the output for one page is not finished at 510, Sll
Check whether the same line of image data has been output for the number of enlargement factors or not, and if the image data for the same line has not been output for the number of enlargement factors, send the start address of the same line to the DMAC 5 again to repeat the same scan in the vertical direction. Set S
Return to 3.

If the vertical enlargement according to the enlargement magnification has been completed, the process advances to S13, and the start address of the next line is set in DMAC5, and in the subsequent S14, it is determined whether or not there is a change in the enlargement magnification from this line. If there is a change in magnification, the process returns to S2 to execute processing according to the new magnification.

In the above explanation, an example was explained in which the magnification is changed only for each line, but when changing the magnification in the middle of one line, the CPU instructs the DMAC 5 to read data for one line from the page memory 2. In this case, a specific address value for which the magnification should be changed is specified, and when the address value is accessed, the DMAC 5 outputs an interrupt request to the CPUI, and the enlargement magnification changing process is executed at this point.

FIG. 3 shows an enlarged example of the pattern according to this embodiment.

FIG. 3(A) shows the storage pattern in the page memory 2 before the enlargement process is executed. FIG. 3 shows an example in which "Z12" shown in FIG. CB),
An example enlarged three times in both the horizontal and vertical directions is shown in FIG. 3(C).

In the above embodiment, if the clock signal output from the horizontal clock generation circuit 7 to the N-ary counter 8 is the same as the horizontal clock signal 12, the enlargement factor will be an integral multiple of 1, but the clock signal to the N-ary counter 8 will be By setting the period to twice that of the horizontal clock signal 12, it is possible to automatically set the period to an integer multiple of the number of stations in the horizontal direction. For other magnifications, arbitrary magnifications can be set by similarly changing the clock cycle.

As explained above, according to this embodiment, only normal image patterns that are not enlarged are stored in the page memory 2, and the output to the output device is performed without adding any special pattern storage memory or the like. Any magnification can be set in stages, and the output magnification to the output device can also be changed using the N-ary counter 8.
This can be done without changing the storage pattern of page memory 2, etc. by simply changing the setting value for , and the number of scans of the same line in the vertical direction, and this can be particularly effective when enlarging a specific image area. .

[Effects] As explained above, according to the present invention, by simply storing pattern information of a single size in the storage means, it is possible to enlarge the pattern information to an arbitrary size and output it when reading from the storage means, Furthermore, a pattern enlarging method can be provided in which the enlargement magnification can be changed extremely easily.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment according to the present invention, FIG. 2 is a flowchart showing enlargement processing in this embodiment, FIG. 3(A) is a diagram showing a storage pattern before enlargement in this embodiment, FIGS. 3(B) and 3(C) are diagrams showing examples of enlarged patterns of this embodiment. In the diagram, 1...CPU, ? ...Page memory, 3...
・DMACl3...Latch register, 6...P/S
Register, 8... N-ary counter, 9... N-ary data register, 20... Output device. Patent applicant Canon Co., Ltd. Figure 1

Claims (2)

[Claims] (1) A pattern enlarging method in a pattern output device that outputs pattern information stored in a storage means pixel by pixel in synchronization with an output clock signal, the method comprising: outputting pattern information for each pixel read out from the storage means; A pattern enlarging method characterized in that the pattern information to be output is enlarged by making a change every predetermined number of outputs of the output clock signal according to an enlargement ratio. (2) The readout timing from the holding means for holding the pattern information read out from the storage means for each predetermined capacity is set every time a number of output clock signals are output corresponding to the enlargement ratio, and the number of output clock signals corresponding to the enlargement ratio is 2. A pattern enlarging method according to claim 1, characterized in that the holding means repeatedly outputs the holding pattern information.