JPS61116417A - Tree-value output circuit - Google Patents

Abstract

PURPOSE:To obtain a three-value output circuit which wakes the integrating circuit of a high load driving capacity high density with low power consumption by connecting each end of the PMOS and NMOS transistors for data input and for control input serially connected to an npn bipolar transistor and further, connecting these transistors. CONSTITUTION:To one end of two PMOS transistors MP2 and MN1 for data input and for control input serially connected, the base of the first npn bipolar transistor Q1 is connected, and to the other end, the collector is connected respectively, and to one end of NMOS transistors MN3 and MN4, the base of the second npn bipolar transistor Q2 is connected, and to the other end, the collector is connected respectively, and the emitter of the first npn bipolar transistor Q1 and the collector of the second npn bipolar transistor Q2 are connected, and the output terminal is obtained. When a control signal phi is a high level, the inverting output of an input signal DIN is given to an output terminal 10, input data DIN is shifted from the high level to the low level, and then, the electric potential of bases 5 and 6 is almost a ground electric potential and an output OUT goes to be a low level. Thus, the circuit has both a low power consumption characteristic of CMOS and a high speed characteristic of bipolar and high density is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a three-value output circuit, and particularly to a high-level output circuit,
3 low level output and high impedance state output
The present invention relates to a transistor integrated circuit that can operate at high speed, consume low power, and occupy a small area.

[Conventional technology]

Conventionally, a circuit as shown in FIG. 10 has been used as a ternary output circuit.

In FIG. 10, xl and x2 are CMOS inverters,
X3 is a 2-person NAND circuit, X4 is a 2-person NOR circuit,
M1 is a P-channel MOS transistor at the output stage, and M2 is an N-channel MO8 transistor at the output stage connected in series with M1. In normal operation, the control signal φ is at the 1 level, and the data DIN applied to the input 1 is propagated. D
When IN is at no-i level, two-man NAND circuit x3,
The outputs of the two-man power NOR circuit X4 both go to the no-low level, the output stage transistors M1 and M2 turn on, and the output OUT goes to the low level. On the other hand, data DI
When N is low level, two-man NAND circuit X3,
The outputs of the two-manpower NOR circuit X4 are both low level, and the output stage transistor M1 is on and M2 is off, so the output OUT is high level.

Also, when the control signal φ is set to low level, the two-man power NAN
The output of D circuit
Since the output of the R circuit X4 is fixed at a low level, both output stage transistors Ml and M2 are turned off, and the output O
UT goes into high impedance (H2) state.

However, the circuit configuration shown in Figure 10 requires an inverter, a NAND circuit, a NOR circuit, and an output stage transistor for each circuit, which has the drawback of increasing the number of elements. There are also drawbacks that hinder development. That is, in order to drive at high speed a portion where a heavy load capacitance is applied to the output end of an output circuit, a bus system, etc., it is necessary to increase the mutual conductance gm of the output transistor. To achieve this, the channel width of the transistor must be widened, and the NAND circuit and NOR circuit in the previous stage that drive this output transistor must also be widened to 9m, so the channel width of the transistor must be widened. The dimensions of will become large. As a result, the area occupied by the layout increases, which hinders higher density.

A circuit having a structure shown in FIG. 11 is a circuit in which the number of circuit elements is reduced compared to that in FIG. 10.

In FIG. 11, P-channel MO8 transistors M3, M
4 and N-channel MOS transistors M5 and M6 are connected in series, input data DIN1 is applied to the common gate of transistors M4 and M5, control signals φ and φ are applied to the respective gates of transistors M3 and M6, and the source side of transistor M4 and The output OUT is taken out from the drain side of M5. When the control signal φ is at level...output OU
Inverted data of input data DIH is output to T.

- when the control signal φ is low level, the transistor M
3. Since both M6 are turned off, the output OUT is manual data D. High impedance regardless of N (I(Z)
state.

The circuit configuration shown in Fig. 11 has only four transistors and a small number of elements, but even in this case, when a heavy load is applied to the output terminal, in order to drive at high speed, the transistor M
There is a drawback that the size of all transistors from 3 to M6 must be increased.

[Purpose of the invention]

The purpose of the present invention is to improve these conventional drawbacks, and to provide a high-density integrated circuit with low power consumption and high load driving capability even when a heavy load with wiring capacity is applied to the output end of the bus system, driver system, etc. The object of the present invention is to provide a three-value output circuit that can be converted into a three-value output circuit.

[Structure of the invention]

In order to achieve the above object, the ternary output circuit of the present invention has two PMOs connected in series, one for data input and one for control input.
One end of the S transistor is connected to the base of the first NPN bipolar transistor, and the other end is connected to the collector of the transistor, and one end of the two NMOS transistors connected in series for data input and control input. is connected to the base of a second npn bipolar transistor, the other end is connected to the collector of the transistor, or to the collector via an np diode, and the emitter of the first bipolar transistor and the second bipolar transistor are connected to each other.・The feature is that it is connected to the collector of the transistor and used as an output terminal.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a ternary output circuit showing a first embodiment of the present invention.

In FIG. 1, MPI and MP2 are P channel MO81
, transistor, MNI, MN2. MN3゜MNl is an N-channel MOS transistor, Ql.

Q2 is a pn bipolar transistor. In addition,
1 is a signal input terminal, 2 is a control signal φλ input terminal 3 is an inverted control signal ■ input terminal, 10 is a signal output terminal (OUT)
It is.

As shown in FIG. 1, in this embodiment, two PMOS transistors IVIP2. for data input and control input are connected in series. The base of an nPn bipolar transistor Q1 of ml is connected to one end of the MNI, and the collector of the nPn bipolar transistor Q1 of ml is connected to the other end, and two NMOS transistors MN3 .
The base of a second nPn bipolar transistor Q2 is connected to one end of MNl, and the collector of the second nPn bipolar transistor Q2 is connected to the other end, and the first nPn bipolar transistor Ql
emitter of and a second npn bipolar transistor Q
It is connected to the collector of No. 2 to serve as an output terminal.

Now, when the control signal φ is at the 1 level, the NMOS transistor and the PMOS transistor MPl are always on, so that the inverted output of the input signal DIN is provided to the output terminal 10. MOS transistors MNl and MNl are MOS transistors for discharging carriers stored in the bases of bipolar transistors Ql and Q2, and prevent through current from flowing from power supply VDD to transistors Ql and Q2 at the same time. Transistor Q1 is M
This is a transistor that amplifies the drain current of OS transistors MP1 and MP2, and has an emitter-follower type, increasing the driving ability when charging a load. Further, the transistor Q2 is a MOS transistor MN2. This is a transistor that amplifies the drain current of MN3, which increases the drive capability when discharging the load.

Now, consider the case where the input data DIN changes from high level to low level. When DIN is at a high level, transistors MHI and MN2 are both on and MP2 is off, so the bases 5 and 6 of transistors Q1 and Q2 are
The potential is approximately at ground potential, and the output OUT is at a low level. Next, when the input data DI'N changes from high level to low level, transistor MP2 turns on and MH
Since I and MN2 are both turned off, the t current passing through MPI and MP2 increases the potential at the base 5 of transistor Q1. As a result, the base-emitter voltage of the transistor Q1 is forward biased, so a base current flows, turning on the transistor Q1, charging the output load CJ together with the collector current, and raising the output OUT to a high level. Since this driving capability is (1+11 f e ) times the g□ of the MOS transistor, a significant improvement is expected. Furthermore, when the output OUT rises to a high level, the potential of the base 6 of the I-transistor Q2 rises due to capacitive coupling, but the transistor MN4 is always on, and the base accumulated carriers are discharged via MNl. Therefore, transistor Q2 remains almost in an off state. Therefore, through current is suppressed.

Next, when the input data DIN changes from low level to high level, transistor MP2 is turned off, MNl is turned on, and MN3 is turned on, so the potential of the base 5 of transistor Q1 becomes low level, which turns Ql off. , Q2 is turned on, and the output OUT is high level and low level.

At this time, the base current of transistor Q2 is the same as that of transistor MN2. Since it flows through the drain current of MN3, when the output load is discharged, the driving capacity becomes 9m (1+11fe) times that of the MOS transistor.

In order to operate the circuit shown in Figure 1 at high speed, bipolar
While increasing fT of transistors Ql and Q2,
It is necessary to keep the collector junction capacitance, emitter junction capacitance, and substrate-to-substrate capacitance low.

FIG. 2, FIG. 3, and FIG. 4 are block diagrams of three-value output circuits showing other embodiments of the present invention, respectively.

In both cases, the connection positions of the PMOS transistors MPI and MP2 or the connection positions of the NMOS transistors MN2 and MN3 are changed, but the circuit operation is almost the same as in FIG. That is, in FIG. 2, the transistor M
Pl is connected between MB2 and MNl, and in FIG. 4, transistor MN2 is connected between MN3 and MN4, and in FIG. 3, the connection positions of both have been changed.

FIG. 5 is a configuration diagram of a ternary output circuit showing still another embodiment of the present invention.

In FIG. 5, a first npn bipolar transistor is connected to one end of two PMOS transistors MPI and MP2 connected in series.
The base of transistor Q1 is connected to the collector to the other end, and two NMO3 transistors M are connected in series.
N2. At one end of MN3, connect the base of a second npn bipolar transistor Q2 between the other end and the collector.
A diode Dl is connected, and a first transistor Q
The emitter of the first transistor Q2 is connected to the collector of the second transistor Q2, and this is used as an output terminal.

Transistor MN3 is a MOS transistor for discharging carriers accumulated in the bases of transistors Q1 and Q2, and is connected to transistor Ql from power supply VDD.

This prevents a through current from flowing through Q2 at the same time.

Further, the diode D1 allows all of the collector current of MB2 to become the base current of the transistor Q1 when the transistor MP'2 is turned on. The transistor Q1 amplifies the drain currents of the transistors MPI and MP2, and increases the driving ability when charging a load.

In this case as well, consider the case where the input data DIN changes from high level to low level. When DIN is at the no-y level, the transistor MNl is on and MB2 is off, so the potentials of the bases 5 and 6 of the transistors Ql and Q2 are approximately the ground potential, and the output OUT is at the low level. Next, data DIN transitions from a high level to a low level, transistor MP2 is turned on, and MNl is turned off, so the current flowing from the power supply VDD through transistors MPI and MP2 increases the potential of the base 5 and the transistor Q1. The voltage between the base and emitter is set to negative, and Ql is turned on. The Q10 base current charges the output load capacitance tCL together with the collector current, raising the output OUT to the NO level.

In this way, Q
By adding l, the apparent gm becomes (1+hfe) times as much as 9□ with only a normal MOS transistor, so a significant improvement in current drive capability can be expected.

Furthermore, when the output OUT rises to the NO level, the potential of the base 6 of the transistor Q2 rises due to capacitive coupling, but since the transistor MN3 is always on, the base accumulated carriers are transferred through the transistor MN3. is discharged, so transistor Q2 remains substantially off. This completely prevents through current.

Next, when the input data DIN moves from the low level to the no-no level, the transistor MP2 turns off and MNl turns on, so first the potential at the base 5 of the transistor Q1 decreases and Ql turns off, causing the accumulation of output load CL. Part of the charge is transferred to the diode DI, transistor MNI, 'M
Since it becomes the base potential of the transistor Q2 via N2, Q2 is turned on and the output OUT changes from high level to low level. At this time, the base current of the transistor Q2 flows through the drain currents of the transistors MNl and MN2, so that when the output load is discharged, the driving capability is (l + hfe) times the gm of the MOS transistor. In order to operate this circuit at high speed, as in the case of FIG.
It is essential to keep the inter-substrate capacitance low.

6, 7, and 8 are diagrams each showing a modification of the circuit of FIG. 5.

Compared to FIG. 5, these are the PMOS transistor M
Although the connection positions of PI and MP2 or the connection positions of NMOS transistors MN22MN3 have been changed, the circuit operation is exactly the same as in FIG. 5.

FIG. 9 shows an experimental example of the present invention, and shows simulation results of delay time characteristics for one load capacitance CL in comparison with the conventional one.

In FIG. 9, A indicates the characteristics of the circuit shown in FIG. 10, B indicates the characteristics of the circuit shown in FIG. 11, and C indicates the characteristics of the circuit of the present invention shown in FIGS. 1 to 8. It is.

Here, fT of transistors Ql and Q2 is 3GH2
It is said that

As is clear from FIG. 9, compared to characteristics A and B of the conventional circuit using the 0M08 circuit, characteristic C of the circuit of the present invention shows less change in delay time due to changes in load capacitance. In other words, although the present invention is not as effective against light loads as the conventional system, it exhibits sufficient high speed performance against heavy loads.

Note that the present invention can be applied to switch elements such as digital space switch LSIs with m inputs and n outputs arranged in a matrix.

〔Effect of the invention〕

As explained above, the ternary output circuit according to the present invention is
By applying it to places where heavy loads such as wiring capacitance are applied at the output end of bus systems, driver systems, etc., it is possible to realize a circuit that combines the low power consumption of 0MO8 and the high speed of bipolar. It becomes possible to increase the density of integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a ternary output circuit showing one embodiment of the present invention, FIGS. 2 to 8 are block diagrams of a ternary output circuit showing other embodiments of the present invention, and FIG. is a gate delay characteristic diagram with respect to the load capacitance of the present invention, and FIGS. 10 and 11 are both configuration diagrams of a conventional CMO 83-value output circuit. MPI, MP2: PMOS transistor, MNl~
MN4: NMO8 transistor, Ql, Q2: np
n bipolar transistor, CL: output load capacitance,
DIN: input data signal, OUT': output data signal, φ: control signal, DI: Pn diode. Figure 9 Load capacity CLCpF] Figure 10 Figure 11

Claims (3)

[Claims] (1) One end of two series-connected PMOS transistors for data input and control input is connected to the base of the first NPN bipolar transistor, and the other end is connected to the collector of the transistor. One end of the two NMOS transistors for data input and control input is connected to the base of a second NPN bipolar transistor, and the other end is connected to the collector of the transistor, or to the collector via an np diode. A ternary output circuit further comprising: an emitter of the first bipolar transistor and a collector of the second bipolar transistor connected to each other to form an output terminal. (2) One end of the above two PMOS transistors is connected to the first
npn bipolar transistors are respectively connected to the drains of the source-grounded NMOS transistors, and one ends of the two NMOS transistors are connected to the drains of the source-grounded NMOS transistors along with the bases of the second npn transistors whose emitters are common. 2. The ternary output circuit according to claim 1, wherein the three-value output circuit is connected to the three-value output circuit. (3) One end of the above two NMOS transistors is connected to the base of the second NPN bipolar transistor whose emitter is grounded and the drain of the NMOS transistor whose source is grounded, and the other end is connected to the n end of the pn diode and the first NMOS transistor. The three-value output circuit according to claim 1, wherein the three-value output circuit is connected to the bases of npn bipolar transistors.