JPS6097770A - Picture processor - Google Patents

Abstract

PURPOSE:To obtain a picture processor coping with overflow of a memory by compressing a picture data, storing it to a picture memory, providing a detour circuit to the memory and selecting any of them for processing picture. CONSTITUTION:A digital picture data fed from a picture data input unit 10 is fed to a picture memory unit 11 having a picture memory storing/reproducing the digital picture. The picture memory unit 11 has a changeover switch bypassing the picture memory and a changeover switch selecting switching the bypass selectively so as to change over the main path and the bypass based on the command from a control unit 13. The digital picture data from the picture memory unit 11 is fed to a picture data output unit 12, where a picture is formed to a recording medium such as recording paper. The control is executed entirely based on the command from the control unit 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image processing device that stores/reproduces images using an image memory.

[Prior Art] Conventionally, image data supplied from an image data input unit such as a document reading device is stored in an image memory, and the data is reproduced from the image memory.
There is an image processing apparatus that causes an image data output unit such as a printer to make multiple copies of 14 images. In this type of device, when making such multiple copies, the process of reading the document and storing the image data in the image memory only needs to be done once, so the time required to set the document etc. is shortened.
This has the advantage of improving copying efficiency. Furthermore, when a stationary document is read multiple times, the 8Ir round trip of the optical system can be ignored, so there is an advantage that even higher speed copying becomes possible.

However, in such conventional image processing devices,
When a large amount of image data is handled, a large capacity image memory is required, which poses a problem in that the image processing apparatus cannot be constructed at a low cost.

Therefore, by applying the image data compression and expansion technology used in facsimile machines, etc., the image data can be compressed and stored in the image memory, and the stored image data can be expanded and played back. , the capacity of the image memory can be reduced.

However, in this case, the data compression rate differs depending on the type of image data, and for example, the amount of data will be large even if it is compressed, such as image data where black and white information appears repeatedly or image data that has been dithered for halftone reproduction. Regarding image data, it may become impossible to store all the data in the image memory used, or a so-called memory overflow may occur. Therefore, such memory overload
When a flow occurs, it is preferable that the image data supplied by the image data input unit be directly used for copying without going through the image memory.

[White Eyes] The present invention eliminates the conventional problems and reduces the capacity of the image memory by compressing image data, storing it in the image memory, and decompressing and reproducing the stored image data. In addition, it is equipped with a detection means for detecting the state of both image data, and a detour path that bypasses the image memory from the image data input unit and supplies the image data to the image data output unit, thereby preventing memory overflow. It is an object of the present invention to provide an image processing device that can perform image processing by selecting a detour route in such a case.

[Example] The present invention will be described in detail below with reference to one drawing.

FIG. 1 shows an example of the configuration of an image processing apparatus according to the present invention. Here, 1o is an image data unit that supplies digitized digital image data, and is, for example, a document reading device that reads a document, converts the read information into digital image data, and outputs it, or a character A device that has a generator and converts a document to be copied into digital image data and outputs it, a so-called word processor (document creation device), or the like can be used.

Reference numeral 11 denotes an image memory unit having an image memory for storing/reproducing digital images supplied from the image data input unit 10.

Reference numeral 12 denotes an image data output unit I which forms an image on a recording medium such as recording paper based on the digital image data supplied from the image memory unit 11, and is, for example, a printer such as a laser beam printer (LBP) or an inkjet printer. Alternatively, a facsimile device or the like that transmits and receives digital images to and from a remote location can be used.

Reference numeral 13 denotes a control unit l- (master CPU), which controls the transmission of image data between the units 10 to 12 in response to command signals supplied from the operation unit 14.

The operation unit 14 includes, for example, a keychain-type operation console. 15 is a display unit having an indicator such as a display or a lamp, and information related to control supplied by the control unit 13, such as image data output unit 1 and 2;
When making multiple copies of the same document, information on the number of copies that is currently being made, information on whether each unit is operating, information on whether it is in an inoperable state, error occurrence, etc. Displays information related to the operation of each unit, allowing the operator to understand the status.

As will be described later with reference to FIG. 2, the image memory unit 11 has a bypass path that detours around the image memory and a changeover switch that selectively switches between the bypass path and the main path and the bypass path based on a command from the control unit 13. It is possible to switch between routes. In addition, since this embodiment has a unit configuration, the system can be easily expanded, and can be provided in accordance with the demands of users, from low-priced and low-function to high-priced and high-function products, and maintenance management is also easy. Has characteristics.

FIG. 2 shows an example of the configuration of the image memory 11 shown in FIG. Here, 20 is an image data input unit) 10
This is an image data input terminal to which digital image data supplied from the terminal is input, and is connected to a switch SWI that selects the first path A and a switch SW2 that selects the second path B for transmitting the digital image data. 21 is an image data output terminal that outputs digital image data to the image data output unit (image data output unit) 12; Connect to circuit 34 and switch SWI.

24- is a 4727 circuit arranged between the switch SW2 and the compression circuit 33, and when the second path B is selected by the switch SW2, the circuit synchronizes the supplied digital image data with the image memory itself, which will be described later. Take.

25 is an interface circuit (1/F), which connects the CPU
Switching control signals for each switch swi to SW3 where 2fi is generated 1 Input/output control signals related to the image memory main body. The CPU 2B controls the entire image memory unit 11 according to a control program stored in the ROM 27. A RAM 28 stores control information as a working memory for the CPUs 2+3. 28 is an interface circuit (1/F), which sends commands from the operating unit 14 supplied via the control unit 13 shown in the first diagram to the CPU 2B.
and causes the CPU 28 to execute control corresponding to the command.

The compression circuit 33 is a circuit that performs compression processing on the digital image data sent from the buffer circuit 24. For example, if the modified Huffman encoding method used in facsimile machines is used as the compression method, image data can be processed at high speed in real time.

Compressed digital image data output by the compression circuit 33 is guided to the control circuit 30 and the detection circuit 35.

Reference numeral 31 denotes a dynamic RAM as an image memory main body, and a control circuit 30 controls storage/reproduction of digital image data in the RAM 31 based on a command signal transmitted from the I/F 25.

34 is an expansion circuit which performs expansion processing on the digital image data compressed by the compression circuit 33 and restores the original digital image data.

The detection circuit 35 is a circuit that counts the amount of information of the digital image data compressed by the compression circuit 33 using, for example, a counter, and detects whether or not the amount of information exceeds a predetermined amount of information. Alternatively, the content of the image data may be detected based on the run length of the digital image data before being compressed by the compression circuit 33, and the amount of data after compression may be determined based on this. When compressing digital image data and storing it in the image memory main body, the CPU 2fi refers to the detection signal generated by the detection circuit 35 and determines whether or not the data has been stored normally.

AI is a bypass path and switches SWI and SW
3 and bypasses I'lAM3]
form. That is, the first path A consists of the image data input terminal 20→switch SWI→bypass path 32→switch SW3→image data output terminal 21.

Further, the second path B is the image data input terminal 20→switch S 2 output switch 24→compression circuit 33→control circuit 30-
A digital dual-image storage path B1 consisting of RAM 31 and RA
M31 → control circuit 3o → extension circuit 34 → switch SW3
->A digital image reproduction path B2 consisting of an image data output terminal 21.

In this embodiment, the No. 48 standard for digital image data between the image data input unit 10, the image memory unit 11, and the image data output unit 12 in FIG. 1 is unified, and the image data input unit IO and the image data output unit 12 are Enables operation even when connected directly.

Therefore, when the image memory unit 11 shown in the second figure is arranged between the image data input unit 1o and the image data output unit 12 as shown in the first figure, the image data sent from the image data input unit 11O is While the received digital image data is stored in the image memory unit 11 via the path Bl, the first image data output unit 12 is also stored.
The image data output unit 12 can be operated by transmitting digital data via path A. In other words, the efficiency when outputting the same image data for multiple components to the image data output unit 12 can be increased. In addition, if an error occurs on the image memory date 1 and t-, for example, if the RAM 31 fails, or if the data to be compressed is, for example, 2 after dither processing (1/i signal and the compressed image data Even if the amount of digital image data is too large to be stored in the 1'lAM 31, the first path A can be selected and the digital image data can be supplied to the image data output unit 12, so that the operation as the image processing device δ can continue. can do.

The image memory unit 11 can be constructed by mounting commercially available elements. To describe a specific circuit implementation example, C
The PU 28 is an Intel 8-bit microprocessor 8085A, the ROM 27 and interface circuit 25 are Intel's 8355 with a built-in ROM and an I10 port, and the RAM 28 and interface circuit 29 are an Intel 8355 with a built-in ROM, an I10 port, and a counter circuit. You can also use Intel's 8155, which also has a built-in. In addition, the buff 2 buff circuit 24 includes
High-speed static memory, such as Intel's 214
8, 2148, etc. can be used, and 64 as RAM31
A K-bit dynamic RAM, such as Intel's 2164, can be used. Moreover, as the control circuit 30,
A dynamic RAM controller such as Intel's 8202A can be used. Standard Schottky TTL ICs can be used for switches SWI and SW2 and changeover switch SW3. When the above elements are used, the image memory unit 11 can be constructed with a small number of chips at a relatively low cost.

3(A) to (D) respectively show the switch states of the switches 5WI-9W3 disposed in the image memory unit 11, where 40 indicates the RAM 31, the control circuit 30,
/ Sympha circuit 24, compression circuit 33 and expansion circuit 34
This is an image memory system (hereinafter simply referred to as image memory) that comprehensively represents the following. In addition, in this figure, for ease of understanding, the control unit shown in Figures 1 and 2)
．． Illustrations of various parts such as the I/F 25 are omitted.

FIG. 3(A) shows an initial state such as when the power is turned on or when waiting to start copying. That is, in response to a command signal from the CPU 2B sent via the I/F 25, the switch
WI and SW2 are open, and switch SW3 is connected to contact a on the bypass path Al side.

FIG. 3(B) shows the situation when the first copy is made when making multiple copies of the same image. That is, in response to a command signal from the CPU 2B sent via the I/F 25, the switches SWI and SW2 are closed, and the switch SW3 is connected to the contact a on the side of the bypass path Al. Therefore, in this state, the digital image data supplied from the image data input unit) 10 is
The image is recorded in the image data output unit (12) via the first path A, and is transferred to the image memory 40 (via the path Bl).
R is supplied to R after being compressed by the compression circuit 33.
It is stored in AM31. At this time, the detection circuit 35 operates to detect memory overflow.

The switch changeover control shown in FIG. 3(A) is performed in response to the power being turned on, and the switch changeover control shown in FIGS. It will be done accordingly.

FIG. 3(C) shows that when the detection circuit 35 does not detect 1 memo or overflow, and the digital image data corresponding to +1 L is stored in the image memory 40, the same image is On the other hand, the state when copying the second and subsequent copies is shown. In other words, the switch S
WI and SW2 are open, and the switch 3 is connected to the contact b4 on the path B2 side. Therefore,
In this case, the reproduced digital image data is supplied from the image memory 40 to the image data output unit 121 a number of times corresponding to the desired number of copies, and is subjected to image recording processing.

FIG. 3(D) shows a situation where the detection circuit 35 strongly detects a memory overflow during copying and the image memory 401 cannot store one page's worth of digital image data. That is, in response to a command from CPυ26 sent via I/F 25, switch SWI is closed, switch SW2 is opened, and switch SW3 is connected to contact a on the path Al side. Therefore, in this case,
The image data manual unit 10 and the image data output unit 12 are connected only through the first path A, and the digital image data 1 bypasses the image memory 40 and is directly supplied to the image data output unit 12 to make the desired copy. It will be done.

Moreover, this situation occurs not only when memory overflow occurs, but also when, for example, RAM 31, control circuit 30
The present invention can also be applied to cases where an abnormality occurs, such as when it becomes impossible to store digital image data. Therefore, interruption of the copying operation can be prevented even in such an abnormal situation.

FIG. 4 shows an example of the control procedure by the ;fi control unit, 1-13 in the digital image processing apparatus of the present invention shown in FIG. 1 and FIG. It is. The control procedure in FIG. 4 will be explained below with reference to FIGS. 3(A) to 3(D).

First, when the power is turned on to the device shown in the first figure, initialization processing is performed on the display unit 15, I10 port, etc. in step SPl, and then the switches SWI to SW are initialized.
3 is initialized to the state shown in FIG. 3(A). Therefore, from the image data level (10) to the image memory level (11)
Since the signal path supplied to the image data output unit 12 is cut off and the signal is no longer supplied to the image data output unit 12, even if the image data input unit 10 or the image data output unit 7) 12 malfunctions, digital image data cannot be input. No output operation is performed.

Next, in step SP2, it is determined whether or not there is a command to start copying from the operation unit 14 shown in the first diagram, for example, whether there is an operation input of the copy start key, and if the determination is affirmative, step Proceed to SP3 and wait if the determination is negative.

In step SP3, prior to the copy operation, the detection circuit 35. Initializes the control circuit 30 and the like.

In step Sρ4, as shown in FIG. 3(B), 5WI-3W3 is replaced with JILJ so that the digital image data from the image data input unit 10 is directly supplied to the image data output unit 12 via path A. also be remembered.

In the next step SP5, the image data input unit 10 and the image data output unit )+2 are started to operate, and the image data output unit 12 directly receives the digital image data supplied from the image data input unit 10 via path A. Capture and record images.

In step SP8, the switch SW2 is closed so that the image memory 40 can store the digital image data, and image storage processing is started.
One page worth of digital image data supplied from 0 is stored in the image memory 40.

In step SP7, two image data person crab knit 1
It is determined whether or not digital image data for pages 0 to 1 has been supplied, and if the determination is affirmative, the process advances to step SP8.
On the other hand, if the determination is negative, the process waits until the process ends. For example, when LBP is used as the image data output unit 12, when an affirmative determination is made in step SP7, whether it is a copy of 1 sheet 1 or II&+didirection.
+-/F, and at step SP8, it is determined whether or not all of the digital image data for one page has been compressed and normally stored in the RAM 31 by referring to the detection contents of the detection circuit 35, i.e. , determine whether a memory overflow has occurred. Here, memory Φ over φ
If a flow has occurred, the process proceeds to step 5P20, and if no flow has occurred, it is assumed that normal storage processing has been performed and the process proceeds to step SP9.

Steps SP3 to 5P12 are control procedures when making multiple copies of the same document.

In step SP8, the operation of the image data person crab knit 10 is stopped. Here, image data entered crab knit 10
However, in the case of a document reading device, for example, the display unit 15 may display a message indicating that the next document can be set.

In the next step 5PIO, as shown in FIG. 3(C), switches 5WI-9W3 are changed to νJ to reproduce one page of digital image data stored in the image memory 40, and output the image data In step 5ptt following supply to step 12, the image data is stored in the RAM 31 and then supplied to the image data output unit 12 to start copying operations for the second and subsequent sheets, and the process proceeds to step SP+2.

In step 5P12, it is determined whether or not the desired number of copies have been completed, and if the copying has been completed, step 5P12 is performed.
The process advances to step 13, and if the determination is negative, the process waits until the copying is completed. Therefore, while it is determined in step 5P12 that the process is waiting for the completion of copying, one or more digital image data are being reproduced and supplied from the one-image memory 40 to the image data output unit 12.

In step 5P13, the operations of the image data input unit IO and the image data output unit 12 are stopped, and then in step 5P14, switches SWI to SW3 are switched as shown in FIG. 3(A) to make a series of copies. After completing the work, the process returns to standby step SP2 and waits until the next copy start instruction is received.

Next, processing steps 5P20 to 5 when it is determined in step SP8 that a memory overflow has occurred
Sρ22 will be explained.

In step 5P20, the switches 5WI-SW3 are switched as shown in FIG. 3 ([1), thereby separating the image memory 40 and making it irrelevant to the copying operation.

In the next step 5P21, the operations of the image data input crab unit 10 and the image data output crab unit 12 are started, and the digital image data from the image data input crab unit IO is sent to the image data output crab unit 1 via path A.
2, and one or more copies are made until it is determined in step 5P22 that the desired number of copies have been completed.

If it is determined in step 5P22 that the copying has been completed, the process advances to step 5P13 and the copying work is ended.

In the control procedure shown in FIG. 4, digital image data is stored in the image memory 40 in step SP8 even when the number of pieces is one. Since there is no need to reproduce the digital image data from step SP4, a procedure for determining the number of copies may be provided between steps SP3 and SP4, and the process may proceed to step 5P20, so that the digital image data is not stored in the image memory 40. In addition, the switches SWI and SW in Fig. 2
2 and the changeover switch SW3 can also be replaced with one three-circuit changeover switch.

[Effects] As described above, according to the present invention, there is a route passing through an image memory system including an image data compression circuit, a memory, and an expansion ID circuit, a detour route that bypasses the image memory system, and a detour route that bypasses the image memory system. a detection circuit that detects the state of image data;
Since the image forming apparatus is provided with a switching means for switching between the two paths according to the state of the apparatus, the memory capacity can be reduced and the copying operation can be performed even when the image memory overflows.

Furthermore, according to the present invention, since there are two transmission paths as described above, even when making multiple copies of the same original, the first copy is made via the detour route. It is possible to directly output image data using the image data supplied to the unit, and at the same time supply the same image data to the image memory and store it, so even in the case of the first copy, it is temporarily stored in the image memory and the internally generated data can be stored. Compared to conventional devices that copy based on image data, the working time can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of an image processing apparatus according to the present invention, and FIG. 2 is a block diagram showing an example of the configuration of an image memory unit thereof. 3(A) to 3(D) are block diagrams showing the states of each switch in the image memory unit shown in tf'r2, respectively, and FIG. 4 is a flowchart showing an example of the control procedure of the image processing apparatus of the present invention. be. 10... Image data input crab unit, 11... Image memory unit. 12... Image data output unit, 13... Control unit, 14... Operation unit, 15... Display unit, 20... Image data input terminal, 2nd... Image data output terminal, 26 ...CPU, 30...Control circuit, 31...RAM, 33...Compression circuit, 34...Decompression circuit, 35...Detection circuit, 40...Image memory system (image memory) , SWI, SW
2. SW3...SW4 f, A, B...route.

Claims (1)

[Claims] Compression means for compressing image data; storage means for storing the compressed image data; decompression means for decompressing the stored image data; and an image data output device from an image data input device. a first path for directly transmitting image data to the image data input device; a second path for transmitting image data from the image data input device to the image data output device via the compression means, the storage means, and the expansion means; An image processing device comprising: a detection means for detecting a state of portrait data in a storage means; and said first means depending on the content detected by said detection means. (Hereafter, margin)