JPS6083445A - Synchronization system for asynchronous signal - Google Patents

Abstract

PURPOSE:To simplify a synchronization program and to reduce a device in cost and size by adding a simple circuit to an electronic device consisting of a high- order and a low-order device to be synchronized with each other. CONSTITUTION:An interface 5 is provided with the 2nd intermediate clock generating circuit 56 for a clock generated with the clock of the high-order device 1 appearing in time zones of the phase differences among leading edges and trailing edges of the 1st intermediate clocks C1-C3 adjoining to one another in the 1st intermediate clock group and a synchronizing clock generating circuit 57 which generates a clock of 3 by NOTing one of adjacent clocks and ANDing the other in the 2nd intermediate clock groups E1-E3. Therefore, clocks F2 and F3 generated through a changeover switch 58 and switch circuits 581 and 582 become the same as internal control clocks D2 and D3 and synchronized by a clock A to set data and execute the instructions.

Description

DETAILED DESCRIPTION OF THE INVENTION lal Technical Field of the Invention The present invention relates to a method for synchronizing asynchronous signals of an interface between a higher-level device and a lower-level device of an electronic device.

lbl Behind the scenes of technology In recent years, electronic devices for information processing and communication systems are increasingly processing signals by digitizing them, and synchronization between devices plays an important role in processing timing. . When these systems form a unified system with one synchronization, all processing can be done with one synchronization signal, but when combining systems with different synchronization, it is necessary to deal with so-called asynchronization. It's coming.

(cl. Prior Art and Problems) Taking the main body and peripheral devices of an electronic computer as an example, how the conventional technology deals with asynchronization and its problems will be explained below.

In Figure 1, 1 denotes a computer main body (hereinafter referred to as main body) consisting of 11 central processing units, 12 main storage units (hereinafter referred to as MMU), 13 channel devices (hereinafter referred to as CH), etc. 2 indicates a peripheral device consisting of 21 input/output control devices (hereinafter referred to as 10C), 22 input/output devices (hereinafter referred to as IOD), etc., and 3 indicates a signal line connecting the main body 1 and the peripheral device 2. In the electronic computer system shown in Figures 7 and 7, the main body 1 is a host device, and the peripheral device 2 is a low-order device.

The main unit 1 and the peripheral device 2 each use different synchronization signals (hereinafter referred to as clocks), and the clock of main unit 1 is used as clock A.
2 The clock of peripheral device 2 is clock B, and clock B
The period of the clock A is made almost equal to the period of the clock A. However, clocks A and B have a phase shift as shown in FIG. 2; for example, clock B lags clock A by a time difference j.

The exchange of information between the main body 1♂ and the peripheral device 2 is processed in the ink face 5 (referred to as CH ink face) for the main body 1 located in 10C21 according to a command from the main body 1.First The LOD 22 in the figure is shown as one block 27, but in reality, a magnetic tape device, line blink, etc. and various I (JD) are used together, and these 10D
The periodic conditions related to the exchange of information at the interface 5 vary depending on the configuration and system conditions of operation between the configuration and the main body 1. This will be explained below using a specific example.

The execution of instructions in the interface 5 is performed by four clocks as shown in the time chart of FIG. In Figure 3, the horizontal axis is the time axis, and the instruction P is the clock B(7)6
Here is an example of how this could be accomplished with a cycle.

The clocks CI, C2, and C:3 are intermediate clocks formed using the clock B as a basic clock, and constitute a first intermediate clock group. From the first intermediate clock group, the clocks shown in FIG. 3 are as follows: 1) 1. D2. Form D3. The clocks DI, D2, and D3 are used for internal control of the interface 5 and are called internal control clocks.

The command P is taken out by a microprogram or lock B prepared in advance by the IQC 211 according to a command from the main body 1, and is executed by forming the various clocks shown in FIG. A buffer memory is used, and the handling of synchronization differs greatly depending on whether information is written to or read from the buffer memory using clock 8 or clock B.

For example, if clock D1 is used to analyze the command, D2 is used to analyze the data, and D3 is used to execute the ant command, then the set of N data and the execution of the command are executed in main unit 1.
When the data are closely related to the data, an error will occur unless the synchronization of reading and writing these contents from the buffer memory is based on clock 8.

When the synchronization of reading and writing information in the buffer memory is performed by the clock D, not shown in FIG.
2. There is no problem in setting one data and executing an instruction in D3, but when this is done using clock B, the lock D2. This requires an extremely troublesome procedure of interrupting the execution of D3, inserting double or triple buffers or registers in the middle of J, and performing the process after exchanging information and confirmation with the master body 1. As a result, programs become more complex and the time it takes to execute instructions increases.
First, the cost increases due to the increased amount of hardware, and the hardware requires space and cannot be miniaturized.
The purpose of this method is to synchronize asynchronous signals at one interface between a host device and a low-order device in an electronic device. do.

lel Structure of the Invention The present invention provides an electronic device that mutually exchanges information between a host device that operates based on one predetermined clock and a lower device that operates based on two clocks that have approximately the same period as the first clock. The synchronous synthesis of is an asynchronous interface in which the interface divides the frequency of the second clock by a predetermined number of clocks, and generates a first intermediate clock whose leading edge of the divided output is delayed by one cycle of the second clock. and a second clock formed by the first clock appearing in a time period corresponding to the phase difference between the leading edges and the phase difference between the trailing edges of mutually adjacent first intermediate clocks of the first intermediate clock group. 3 by means for forming an intermediate clock group and the logical negation of the second intermediate clock of one of the mutually adjacent second intermediate clocks of the second intermediate clock group and the other second intermediate clock. This invention has a means for forming a clock, and the third clock according to the invention is a synchronized clock that completely synchronizes the first clock of the upper device, and by applying the third clock to the lower device, the above-mentioned clock can be achieved. The purpose is achieved.

(f+ Embodiment of the Invention Fig. 4 (31 and (bl l) shows a time chart for forming a synchronized clock according to an embodiment of the invention, and Fig. 5 shows a system diagram of the circuit configuration of an embodiment of the invention. show.

The time chart in FIG. 4 1al has the horizontal axis as the time axis as in FIG. 3, and the cycle number B of clock B is shown at the top.
, B2...B6. Main unit 1 which is a host device
The timing of the clock A is assumed to be advanced by a time difference T as shown in FIG. 2, and is indicated by vertical dotted lines AI, A2, . . . , A6 at the bottom.

In FIG. 4 (al), as in the case of FIG. It forms clock group clocks CI, C2, C3 and internal control clocks DI, B2, B3.

The formed clock DI, D2. Among D3, Dl is 1
It is assumed that the command analysis can be processed within the interface 5, and B2 is a sector of N data.

Assuming that B3 is the execution of one instruction, these are D2. D3 requires processing exchange with main unit 1, which is a host device,
It is assumed that the buffer memory associated with this is controlled for information exchange by clock B. That is, it is assumed that the interface 5 is under an asynchronous condition.

Under the above-mentioned conditions, the execution of the six data sets and instructions must be converted to be performed in synchronization with the clock A. In the present invention, this conversion is carried out in a simple manner as described below. It can be carried out.

A delay-type flip-flop (hereinafter referred to as 1)-FF from the clock C1 of the first intermediate clock group and the clock A is
The clock E1 is formed using the clock E1, the clock E2 is formed using the D-FF from the clock B1 and the clock A, and the clock E2 is formed from the clock E2 and the clock A from the D-FF? A clock B3 is formed from this, and the clocks Iflx, E2 . Let B3 be the second intermediate cross group.

There is a clock A for the black and red B as shown in Fig. 4, 1al, and the clock A3 corresponds to the clock D2, and
6 correspond, clock E2 and clock E
The clock F for the clock A3 is logically ANDed with the negation of 3.
2 is formed, and the clock F3 for 6 is formed by the AND of clock E3 and the negation of clock E2. The clock F2. F'3
is synchronized with clock A to execute N data sets and N instructions I. By using these synchronized clocks, the above-mentioned error can be avoided.

FIG. 5 shows a system diagram of a circuit configuration of an embodiment of the present invention.

FIG. 5 mainly shows the circuit according to the present invention in the interface 5, and shows the clock F2. The circuit configuration for obtaining loop 3 is shown.

In FIG. 5, 51 is a first intermediate clock forming circuit, 52
53 is an internal control clock forming circuit, 53 is an interface timing circuit, 54 is a gate circuit, 55 is a buffer memory, C and the like are conventional circuit configurations, 56 is a second intermediate clock forming circuit, and 57 is a clock forming circuit. A synchronized clock forming circuit, 58 is a changeover switch, 581 and 582 are changeover circuits, and these are circuit configurations added according to the present invention.

Inkface Quimin circuit 53 has input 53-4
Input the clock of the upper device or the clock i3 of the lower device to the input 53 1, 2.3, and input the internal clock (clock, l) 1. i) 2, 1) 3) and synchronization control clocks (clocks F2, F3) to manually control the synchronous and asynchronous timing of the interface 5 and LOC 21, and output various signals of the interface 5 at the output 53-5. It also outputs an enable signal from the output 53-6, controls the gate circuit 54, and causes the gate circuit 54 to write information on commands and data supplied from the host device 1 via the signal line 3 into the buffer memory 55.

The buffer memory 55 temporarily stores instructions and data 9 from the main body 1, and the writing and reading timing is determined by the clock A or 13 according to the asynchronous conditions for synchronous generation, and the IO
It is connected to each circuit of C.

! The switching circuits 581 and 582 are circuits that can be used both synchronously and asynchronously in the circuit shown in FIG.
This is a circuit that performs asynchronous function switching. These circuits are switched by a changeover switch 58 to be synchronous when the switch is open, and asynchronous when the switch is closed.

When the buffer memory 55 is controlled by the clock B, the changeover switch 58 is closed (asynchronous), the clock B is output from the switching circuit 581, and the clock A is output from the switching circuit 582. Therefore, the interface Input 53-4 of chiming circuit 53 and buffer memory 5
Clock B is applied to input 55-1 of 5. Also,
Under this condition, the output clock D1 of the internal control clock generation circuit 52 is connected to the input 53-1 of the interface ψ timing circuit 53, and the input 53-2 . '53-3, the output clock F2 of the synchronized clock forming circuit 57. F
3 is connected.

The first intermediate clock forming circuit 51 always forms a first clock group using the clock B, and its output is input to the internal control clock forming circuit 52.

However, a portion of the clock C1 enters the second intermediate clock forming circuit 56. The second intermediate clock forming circuit 56 has three D
-FF, and in this example, the clock C1 of the switching circuit output 582 and the clock E2 of the output of the second 1)-FF and the clock E of the output of the third u-FF.
3 and input it to the synchronized clock forming circuit 57.

The synchronized clock forming circuit 57 is made up of an impark and an AND circuit, and the clock F2 is formed by the logical product of the negative gate of the clock E3 and the gate of the clock E3.
A clock F3 is formed by the logical product of the negation of and the clock F3.

When the buffer memo +155 is controlled by a clock person, the input of the ink face timing circuit 53 is kept as described above, and the changeover switch 58 is opened (synchronized).

The switching circuit 581 outputs the clock A, and the buffer memory 55 is controlled by the clock controller, and the switching circuit 582 outputs the clock B, which is input to the second intermediate clock forming circuit 56. Therefore, the output clock F2 . F3 is F2 in FIG. Obtained like F3,
This is clock D2. of the internal control clock. It can be seen that they are the same as D3.

As described above, in this embodiment, by adding a simple circuit to the conventional circuit, the synchronous and asynchronous conditions of the interface 5 can be handled by switching with a single switch.

Above σ) Implementation valley IJ is clocked by internal control clock]J
1°D2. In the case of three D3, even if the number increases further and many synchronous and asynchronous combinations are required, the number of D-I FFs in the second intermediate clock forming circuit 56 is increased and the synchronized clock forming circuit Of course, this can be handled by changing the combination of negation and logical product.
Furthermore, it goes without saying that the present invention can be applied not only to the above-mentioned electronic computer but also to a wide variety of electronic devices that require synchronization of upper and lower order devices.

Ig+ Effects of the Invention According to the present invention, in an electronic device consisting of a higher-order device and a lower-order device that require synchronization, it is possible to make the lower-order device the same kFt as the higher-order device by adding a simple circuit. By simplifying the synchronization program and eliminating the need for complicated hardware for synchronization that was previously required, cost reduction and equipment miniaturization can be realized.
The present invention is extremely effective in simplifying maintenance and increasing the reliability of the system by simplifying the system.

[Brief explanation of the drawing]

FIG. 1 shows a conceptual diagram of the upper and lower devices of an electronic device related to the synchronization of the present invention, taking the main body and peripheral devices of a computer as an example, and FIG. 2 shows the synchronization signals between the upper and lower devices. FIG. 3 shows a time chart of the formation of an internal control synchronization signal of an interface of a peripheral device to a computer main body, which is formed by a synchronization signal of a peripheral device that is asynchronous with the main body. FIG. 4 ial shows a time chart for forming a synchronization signal for synchronizing the internal control synchronization signal of the above-mentioned interface with the synchronization signal I of the main body of the computer as an embodiment of the present invention, and FIG. 4 TBL shows a circuit for implementing the present invention. FIG. 5 shows a time chart of the formation of a synchronization synchronization signal under synchronization conditions, and FIG. 5 shows a system diagram of the circuit configuration of the embodiment of the present invention. The same reference numerals indicate the same objects throughout the figures, 1 is the electric machine body, 2 is the peripheral device, 21 is the human control device (IOC), 5
3 is an interface, 3 is a signal line, 51 is a first intermediate clock forming circuit, 52 is an internal control clock forming circuit, 53 is an interface timing circuit, 54 is a gate, 55
is buffer memory. 56 is a second intermediate clock forming circuit, 57 is a synchronizing clock forming circuit, 58 is a changeover switch, and 581 and 582 are changeover circuits. Figure 1 Secret Figure 2 Figure 3 Figure 4 (θji Figure 4 r)

Claims (1)

[Scope of Claims] Synchronization of electronic devices that mutually exchanges information between a host device that operates using one predetermined clock and a lower device that operates using two clocks that have approximately the same period as the first clock. In the asynchronous interface, Rin includes means for forming a first intermediate clock group that lags the second clock by one cycle, and a means for forming a first intermediate clock group that lags the second clock by one period, and a means for forming a first intermediate clock group that is delayed by one cycle of the second clock, and a means for forming a first intermediate clock group that is delayed by one cycle of the second clock, and a means for forming a first intermediate clock group that is delayed by one cycle of the second clock, and The above 1 that appears in the time period of phase difference and trailing edge phase difference
means for forming a second intermediate clock group formed by the clocks of the second intermediate clock group;
1. A method for synchronizing asynchronous signals, comprising means for forming three clocks by logically negating one of the second intermediate clocks and logically multiplying the other second intermediate clock.