JPS6064461A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6064461A JPS6064461A JP58173365A JP17336583A JPS6064461A JP S6064461 A JPS6064461 A JP S6064461A JP 58173365 A JP58173365 A JP 58173365A JP 17336583 A JP17336583 A JP 17336583A JP S6064461 A JPS6064461 A JP S6064461A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- impurity
- concentration
- semiconductor device
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000009792 diffusion process Methods 0.000 claims description 80
- 239000012535 impurity Substances 0.000 claims description 37
- 230000015556 catabolic process Effects 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 1
- 238000002955 isolation Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は、単一基板上に形成され、年払化に適した、高
耐圧拡散層及び、抵抗層全形成する半導体装置に関する
〇
低不純物濃度シリコン基板上に形成された高不純、物＃
度プレナー型拡散層と基板間の接合の絶縁破壊耐圧に関
しては、従来より接合の曲率で決まることが知られてい
る。接合の曲率（は、１情は拡散層の深さに比例し、半
導体基板表面のイオン化不純物濃度にも影響される。そ
のため従来より、高耐圧プレナー型拡散層を形成するた
めに、拡散深さを深くすることによシ、接合の曲率半径
を太きくし、耐圧を向上させていた。又、拡散抵抗層に
関しては、従来より、高濃度不純物拡散層あるいは、Ｃ
ｕｏｓ集積半導体装置に於ては、ＷＥＬＬ拡散層を用い
ていた。こｆ′１等は次のような欠点を有している。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device formed on a single substrate and suitable for annual billing, in which a high breakdown voltage diffusion layer and a resistance layer are all formed. High impurity, substance #
It has been known that the dielectric breakdown voltage of the junction between the planar diffusion layer and the substrate is determined by the curvature of the junction. The curvature of a junction is proportional to the depth of the diffusion layer and is also affected by the ionized impurity concentration on the surface of the semiconductor substrate. By increasing the depth, the radius of curvature of the junction is increased, and the breakdown voltage is improved.In addition, as for the diffusion resistance layer, conventionally a high concentration impurity diffusion layer or a C
In the UOS integrated semiconductor device, a WELL diffusion layer was used. This f'1 etc. has the following drawbacks.
高耐圧プレナー型拡散層の拡散深さを深くすることは、
横方向拡散も大きくなり、接合の曲率半径も大きくする
が、拡散温度の高温化、又、拡散時間の長大化をまねく
。拡散温度の高温化は、拡散深さの制御性の感作を１ね
き、さらにシリコンウェハーのそりを増大させるなど、
好ましくない。Increasing the diffusion depth of the high-voltage planar diffusion layer is
Although the lateral diffusion also increases and the radius of curvature of the bond increases, this also increases the diffusion temperature and lengthens the diffusion time. Increasing the diffusion temperature impairs the controllability of the diffusion depth and also increases the warping of the silicon wafer.
Undesirable.
拡散時間の長大片は、生産性の劣イ［・を廿ねく。又同
一基板内に高耐圧部と借財圧部を有する回路等を形成す
る必要がある場合、低重圧部に不必要な拡散層がり余有
することになり、面積の増大をもたらし、経済性も悪イ
「干る。Large particles with long diffusion times result in poor productivity. Furthermore, if it is necessary to form a circuit or the like having a high-voltage section and a debt-pressure section on the same board, an unnecessary diffusion layer will be left in the low-voltage section, resulting in an increase in area and poor economic efficiency. I: “Dry.
高濃度不純物拡散抵抗層においては、抵抗値を大きくす
るには、面積が増大し、経済性が悪化する。さらに、重
圧−電流特性は、第１図に示すように、＃１ぼ直線とな
り、半導体集積回路のＷ力端子の静電気侭Ｆ％ ａ ｌ
ｉ ＯＥｌｌ集口回路出力端子のラッチアップ対策等に
用いた場合、抵抗値は下げられないので、出力抵抗は増
大することになる。In a high-concentration impurity diffused resistance layer, increasing the resistance value requires an increase in area, which deteriorates economic efficiency. Furthermore, as shown in Fig. 1, the heavy pressure-current characteristics are approximately straight line #1, and the static electricity of the W force terminal of the semiconductor integrated circuit is F% a l
When used as a latch-up countermeasure for the output terminal of the i OEll collector circuit, the resistance value cannot be lowered, so the output resistance will increase.
また耐圧も、拡散層と基板との接合制圧で決まってし甘
う。ＣＭＯ８集積回路におけるＷＢＬＬｆｃ用いた拡散
抵抗層は、基板と濃度的に非常に近いために、安定した
抵抗体を形成するためには、大面積化する必要があり、
さらに基板表面のイオン化不純物量にも大きな影酔を受
けてしまい、好ましくない。さらに、ＷＥＬＬは拡散深
さが、５〜１０μ慴程１１ｆと深いために、横方開拡が
りも大きく、それだけでも単純に広い面私か必要となる
。In addition, the breakdown voltage is determined by the bonding pressure between the diffusion layer and the substrate. The diffusion resistance layer using WBLLfc in a CMO8 integrated circuit is very close in concentration to the substrate, so in order to form a stable resistor, it is necessary to increase the area.
Furthermore, the amount of ionized impurities on the surface of the substrate also causes a large influence, which is undesirable. Furthermore, since the diffusion depth of the WELL is as deep as 5 to 10 micrometers (11 f), the lateral spread is also large, which simply requires a large area.
本発明は、かかる欠点を除去したものである。The present invention eliminates this drawback.
本発明は、シリコン単結晶基板上に形成された高濃度不
純物拡散層の周囲を、低飽度不純物層で囲、むことによ
シ、拡散接合１田の向上をさせることが出来、通常のプ
レナー拡散技術で容易に形成することが出来、高耐圧拡
散層と、高耐圧化の必要のない拡散層とを集積什する半
導体装置に於ては、高耐圧拡散Ｗのみを低濃度不純物拡
散層で囲うことにより、但・耐圧拡散層の面積拡大をま
ねかない。さらに、ＭＯ８Ｏ８型集積半導体装置て、低
濃度不純物拡散＃を素子分離に用いている場合、素子分
雛用不純物拡散工程で同時に形成出来ることによシ、工
程を全く増加させずに形成できる。The present invention can improve diffusion bonding by surrounding a high concentration impurity diffusion layer formed on a silicon single crystal substrate with a low saturation impurity layer. In a semiconductor device that can be easily formed using planar diffusion technology and integrates a high breakdown voltage diffusion layer and a diffusion layer that does not require high breakdown voltage, only the high breakdown voltage diffusion W is used as a low concentration impurity diffusion layer. However, by surrounding it with , the area of the voltage-resistant diffusion layer should not be increased. Furthermore, when a MO8O8 type integrated semiconductor device uses low concentration impurity diffusion # for element isolation, it can be formed at the same time as the element isolation impurity diffusion process, without increasing the number of steps at all.
又、Ｍｏｓ型集積半導体装置に於て、セルファライン構
造トランジスタ、あるいはオフセットゲート構造）ラン
ジスタを用いている場合、セルフ了ラインイオン打込み
、あるいは、オフセットイオン打込み工程で同時に低濃
度不純物拡散層が形成出来ることによシ、工程舎全く増
加させずに形成できる。In addition, when a self-line structure transistor or an offset gate structure transistor is used in a MoS type integrated semiconductor device, a low concentration impurity diffusion layer can be formed at the same time in the self-line ion implantation or offset ion implantation process. In particular, it can be formed without increasing the number of process buildings at all.
以上のように本発明の主目的は、製造工程追加やチップ
サイズ増加することなく、高耐圧工Ｏｉ提供するところ
にある。As described above, the main object of the present invention is to provide a high voltage resistance without adding any additional manufacturing steps or increasing the chip size.
また、本発明の別の効果としては、低濃度不純物拡散層
が容易にピンチ・オフすることにより、第２図に示すよ
うな非線形の重圧−電流特性を有する為に、電流制限抵
抗体として用いることが出来、金属電接をとり出すため
の画濃度不純物拡散層を低濃度不純物拡散層でおおうこ
とにより耐圧を向上させることが出来る。又、ＭＯ８型
集積半導体装置に於て、低濃度不純物拡散層を、素子分
１Ｆ６るいは、セルファライン、オフセットイオン打込
みに用いている場合、それぞれの工程をそのまま利用す
ることにニジ、全く工程の増加はない。Another effect of the present invention is that the low-concentration impurity diffusion layer can be easily pinched off and has a nonlinear heavy pressure-current characteristic as shown in Figure 2, so it can be used as a current-limiting resistor. By covering the image density impurity diffusion layer for taking out the metal electrical connection with a low concentration impurity diffusion layer, the breakdown voltage can be improved. In addition, in MO8 type integrated semiconductor devices, when a low concentration impurity diffusion layer is used for elemental 1F6, self-line, or offset ion implantation, it is not possible to use each process as is; There is no increase.
ピンチオフ特性を有する特性の抵抗体のため、オーブン
ドレインあるいは、オープンコレクタ出力に直列に接続
することで、出力保静抵抗となり、低電圧部分での出力
抵抗が非常に小さくすることが出来、かつ耐圧は高くす
ることが出来る。Since the resistor has a pinch-off characteristic, by connecting it in series to the oven drain or open collector output, it becomes an output holding resistance, and the output resistance in the low voltage section can be made extremely small. can be made higher.
以下、実゛施例に基づき本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail based on examples.
第３図に、本発明の高耐圧拡散層の構造模式図を示す。FIG. 3 shows a schematic diagram of the structure of the high voltage diffusion layer of the present invention.
半導体基板：６上に形成された高濃譲“不純物拡散層：
１の周囲を、低濃度不純物拡散層：２で囲うことによシ
、拡散層の曲率半径の最小値が見かけ上大きくなり、接
合耐圧の向上がはかれる。Semiconductor substrate: High concentration impurity diffusion layer formed on 6:
By surrounding 1 with the low concentration impurity diffusion layer 2, the minimum value of the radius of curvature of the diffusion layer becomes apparently larger, and the junction breakdown voltage can be improved.
第４図に、本発明のＬＯＯＯ８型ＣＭＯ８集積半導体装
置の素子分雛用不純物拡散層ケ用いた高耐圧拡散層の構
造模式図を示す。ここではｎ型半導体基板＝１４上に形
成されたｐ型ＷＥＬＬ：１３内に高濃度ｎ型不純物拡散
層：１１及び低濃度ｎ型不純物素子分離用拡散層＝１２
によシ高耐圧拡散層を形成している。FIG. 4 shows a schematic diagram of the structure of a high breakdown voltage diffusion layer using the impurity diffusion layer for element division of the LOOO8 type CMO8 integrated semiconductor device of the present invention. Here, a high concentration n-type impurity diffusion layer: 11 and a low concentration n-type impurity element isolation diffusion layer = 12 are formed in a p-type WELL: 13 on an n-type semiconductor substrate = 14.
A high-voltage diffusion layer is formed.
第５図に、本発明の低濃度不純物拡散層による電流制限
抵抗層の構造模式図を示す。ｐ型半導体基板：２５上に
形成さねた高濃度ｎ型不純物拡散層：２１をｗｉとして
、低＃＃′ｎ型不純物拡散層：２２により、第２図に示
す電圧−電流特性が得られる。又、高濃度ｎ型不純物拡
散層：２１の外側にも低濃Ｆｔｊｎ型不物拡散＃：２２
を入れることにより、耐圧も向上させている。FIG. 5 shows a schematic structural diagram of a current limiting resistance layer formed by a low concentration impurity diffusion layer of the present invention. With the high concentration n type impurity diffusion layer 21 formed on the p type semiconductor substrate 25 as wi, and the low ##'n type impurity diffusion layer 22, the voltage-current characteristics shown in Fig. 2 can be obtained. . In addition, a low concentration Ftjn type impurity diffusion layer #: 22 is also formed on the outside of the high concentration n type impurity diffusion layer: 21.
By adding , the pressure resistance is also improved.
本発明は、グレナー型拡散層の拡散層の拡散深さを深く
することなしに、従来のプレナー拡散技術を用い耐圧を
向上させることが出来、半導体集積装置において、耐圧
が低くてよい拡散層あるいは低くなくてはいけない拡散
層は、面積が増大することがないこと、１六ＭＯ８型集
積半導体装置に於ては、素子分離用低濃度拡散層あるい
は、オフセットゲートイオン打込み拡散層を用いること
により、工程の増加をまねかないこと、斥どすぐれた効
果を有する。The present invention makes it possible to improve the breakdown voltage using conventional planar diffusion technology without increasing the diffusion depth of the diffusion layer of the Grener type diffusion layer, and to improve the breakdown voltage of the diffusion layer or The area of the diffusion layer, which must be low, does not increase.In the 16 MO8 type integrated semiconductor device, by using a low concentration diffusion layer for element isolation or an offset gate ion implantation diffusion layer, It does not increase the number of processes and has an excellent effect on rejection.
また、本発明は、第２図に示す工うなピンチオフ特性を
有する拡散抵抗）−が、ＭＯ８型集積半導体装置に於て
容易に集積でき、トランジスタのオープンドレイン出力
に直列に接続することにより、オン抵抗層を介とんど増
大させることなしに耐圧が向上［７、出力保護抵抗とな
る、などすぐｉ−ｒた効果を有する・
塘だ、本発明の高耐圧拡散層で、第６図に示すオフセッ
トゲート構造ＭＯ８型トランジスタのドレインとして用
いることによシ、トランジスタの耐圧を向上させること
が出来る。Further, the present invention provides that a diffused resistor (having a pinch-off characteristic as shown in FIG. The high withstand voltage diffusion layer of the present invention improves the withstand voltage without increasing the resistance layer [7, and has immediate effects such as acting as an output protection resistor. By using it as the drain of an MO8 type transistor with an offset gate structure as shown, the withstand voltage of the transistor can be improved.
筐た本発明のピンチオフ特性を有する抵抗層で第７図に
示すように、ＣＭＯｆ３集積回路の入力抵抗４２に用い
ることにょＪ）、ＶｌｎにＶＤＤ以上の電圧が加わるよ
うな使用方法でもＶＡ＜：ＶＤＤとすることが出来るた
め、集積回路が破壊されにくくなる。又、プルアップ抵
抗等をつけることが出来るため、入力ゲートのフローテ
ィング状態がなくなる。As shown in FIG. 7, the resistor layer having the pinch-off characteristic of the present invention can be used as the input resistor 42 of the CMOf3 integrated circuit (J), and even in a usage method where a voltage higher than VDD is applied to Vln, VA<: Since it can be set to VDD, the integrated circuit is less likely to be destroyed. Furthermore, since a pull-up resistor or the like can be added, the floating state of the input gate is eliminated.
【図面の簡単な説明】
第１図は従来の拡散抵抗層の電流−電圧特性。
第２図は本発明のピンチオフ特性を有する低濃厚拡散抵
抗層の電流−電圧特性。第３図は本発明の高耐圧拡散層
の構造。第４図（ａ）、 （ｂ）は、ＬＯＣｏ Ｓ構造
の本発明による高耐圧拡散層の構造。第５図は本発明の
ピンチオフ特性を有する低濃度拡散抵抗層の構造。第６
図は本発明の高耐圧拡散層を、ＭＯ８型オフセットゲー
ト構造トランジスタに応用した構造。第７図は本発明の
低濃度拡散抵抗層を入力端子に応用した回路図。
１・・・高濃度拡散１ｉｆｔ ２・・・低濃度拡散層３
・・・コンタクト穴 ４・・・アルミ電極５・・・素子
分離拡散層
１１・・・ｎ型高濃度拡散１−
１２・・・ｎ型素子分離用低濃屋拡散層１３・・・ｐ型
ＷＥＬＬ
１５・・・ｐ型素子分離用拡散層
１６・・・ＬＯ（！Ｏ８酸化膜
１７・・・アルミ電極
２１．３１・・・ソース・ドレイン高＃度拡散１−２２
．３２・・・オフセットゲートイオン打込み低濃度拡散
層
６５・・・基板コンタクト用しｊ濃度拡散層３６・・・
ゲート
３７・・・ソース・アルミ電極
５８・・・ドレイン・アルミ電極
４１・・・入力端子
４２・・・ピンチオフ抵抗層
４３・・・人力保護ダイオード
４４・・・プルアップ・トランジスタ
６、１４．２５．３４ ・・・基 板
第 １１￥１ 第２い
名 ５１￥１
（１１） （胛
葛５図
第０口
名′７呪[Brief Description of the Drawings] Figure 1 shows the current-voltage characteristics of a conventional diffused resistance layer. FIG. 2 shows the current-voltage characteristics of the low concentration diffused resistance layer having pinch-off characteristics according to the present invention. FIG. 3 shows the structure of the high voltage diffusion layer of the present invention. FIGS. 4(a) and 4(b) show the structure of a high breakdown voltage diffusion layer according to the present invention having a LOCo S structure. FIG. 5 shows the structure of a low concentration diffused resistance layer having pinch-off characteristics according to the present invention. 6th
The figure shows a structure in which the high breakdown voltage diffusion layer of the present invention is applied to an MO8 type offset gate structure transistor. FIG. 7 is a circuit diagram in which the low concentration diffused resistance layer of the present invention is applied to an input terminal. 1...High concentration diffusion 1ift 2...Low concentration diffusion layer 3
...Contact hole 4...Aluminum electrode 5...Element isolation diffusion layer 11...N type high concentration diffusion 1-12...N type low density diffusion layer for element isolation 13...P type WELL 15...p-type element isolation diffusion layer 16...LO(!O8 oxide film 17...aluminum electrode 21.31...source/drain high degree diffusion 1-22
．． 32...Offset gate ion implantation low concentration diffusion layer 65...J concentration diffusion layer 36...
Gate 37... Source aluminum electrode 58... Drain aluminum electrode 41... Input terminal 42... Pinch-off resistance layer 43... Human power protection diode 44... Pull-up transistor 6, 14.25 .34 ... board No. 11 ¥1 2nd name 51 ¥1 (11)
Claims (1)
拡散層及び抵抗層において、金属とオーミック接合可能
な基板と逆極性の高濃度不純物拡散層の周囲を、該高濃
度不純物拡散層の不純物と同一極性で、不純物濃度が低
く、該基板不純物濃度より高い不純物濃度を有し、拡散
深さが、該高濃度不純物拡散層と同程度あるいは浅い恢
ｅ ｖ不純物拡ｖｉ層で囲むことを特徴とする半導体装
置。 （２）前１ｅ低濃度拡散層の両端に前記高濃度拡散層を
形成することを特徴とする半導体装置。 （３）特許請求の範囲第２項に記載された低濃度拡散層
の一端あるいは両端に、特許請求の範囲第１項に記載さ
れた低濃度拡散層で囲まれた高濃度拡散層を形成するこ
とをＩ￥ｆ徴とする半導体装置。 （４１特許請求の範囲第１項、第２項及び第５項に記載
された低濃度不純物拡散層を、ＭＯ８型集積半導体装置
の素子分前用不純物拡散層を用いることを％徴とする半
導体装置。 （５）特許請求の範囲第１項、厭２項及び第３項に記載
さｉまた低濃度不純物拡散層を、ＭＯ８型集１導体装置
に１セルフアライン構造トランジスタに用いられるセル
ファライン不純物イオン打込みにより形成、あるいは、
オフセットゲートオＷ造トランジスタに用いられるオフ
セット不純物イオン打込みによシ形成すること全特徴と
する半導体装＠０[Claims] (11) In a high breakdown voltage diffusion layer and a resistance layer formed on a silicon crystalline semiconductor substrate, the high concentration An impurity expansion layer that has the same polarity as the impurity in the impurity diffusion layer, has a low impurity concentration, has an impurity concentration higher than the substrate impurity concentration, and has a diffusion depth similar to or shallower than the high concentration impurity diffusion layer. (2) A semiconductor device characterized in that the high concentration diffusion layer is formed at both ends of the first low concentration diffusion layer (1e). (3) As set forth in claim 2. A semiconductor device characterized in that a high concentration diffusion layer surrounded by the low concentration diffusion layer according to claim 1 is formed at one end or both ends of the low concentration diffusion layer. ( 41 A semiconductor device characterized in that the low concentration impurity diffusion layer described in claims 1, 2 and 5 is used as an impurity diffusion layer for an element of an MO8 type integrated semiconductor device. (5) The low-concentration impurity diffusion layer described in Claims 1, 2, and 3 may be used as a self-aligned impurity ion layer used in a self-aligned structure transistor in an MO8 type conductor device. Formed by driving, or
Semiconductor device @0 which is completely characterized by being formed by offset impurity ion implantation used in offset gate-off transistors
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58173365A JPS6064461A (en) | 1983-09-20 | 1983-09-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58173365A JPS6064461A (en) | 1983-09-20 | 1983-09-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6064461A true JPS6064461A (en) | 1985-04-13 |
Family
ID=15959044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58173365A Pending JPS6064461A (en) | 1983-09-20 | 1983-09-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6064461A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5694664A (en) * | 1979-12-27 | 1981-07-31 | Fujitsu Ltd | Semiconductor element |
-
1983
- 1983-09-20 JP JP58173365A patent/JPS6064461A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5694664A (en) * | 1979-12-27 | 1981-07-31 | Fujitsu Ltd | Semiconductor element |
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