JPS6047629B2 - Memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory control system, and more particularly to a main-memory control system in a shared main memory multiprocessor system.

Conventionally, in a main memory shared type multiprocessor system, as shown in FIG. 1, memory control units (hereinafter referred to as MCU) 4, 5,
6 are connected, and one main memory 100 is shared by these multiple MCUs.

Typically, main memory consists of several memories that can operate independently.
units (in Figure 1, two memory units 7,
10), and these memories are transferred from the MCU.
Since it is multi-connected to units 7 and 10, when accessing the same memory unit,
The main memory 100 can be accessed simultaneously from a plurality of MCUs. However, if multiple MCUs (e.g.
When CUs 4 and 5) make access requests to the same memory unit (for example, 7), only the access request that arrived first is accepted, and the next access request is accepted until the access processing is completed. Requests are made to wait.
Therefore, there is a risk that the waiting time will be longer and the processing capacity will be lowered. On the other hand, in order to improve the reliability of the main memory, a method is proposed in which part or all of the address space of the main memory is multiplexed into multiple memory units 7, 8, and 9, as shown in FIG. was suggested.

In FIG. 2, MCUs 4, 5, and 6 are connected to each processor or channel 1, 2, and 3, respectively, and memory units 7 to 10 of the main memory are multi-connected by MCUs 4, 5, and 6, respectively.

The lower diagram of memory units 7 to 10 shows the concept of the real address space of the main memory. The real address space 11 of the main memory is divided into two spaces 12 and 13, of which the real address space 12 is It has a triplex configuration, and the real address space 13 has a non-multiplexed configuration. That is, only a part of the address space of the main memory is multiplexed by three memory units 7, 8, and 9. In the system shown in FIG. 2, for example, when the MCU 4 makes an access request to the multiplexed real address space 12, all memory units 7, 8, and 9 are accessed simultaneously, so one memory ◆An advantage is that even if a unit fails, processing can continue normally if other memory units are normal.

However, when the MCUs 4 and 5 access the real address space 312 at the same time, only the access request that arrives instantaneously earlier, or the access request with a higher priority when they are simultaneous, is accepted, and all memory units 7 and 8 are accessed.
, 9, the other access request has to wait until the above four access processes are completed.

Note that when a plurality of MCUs access the real address space 13, the method is exactly the same as the method shown in FIG.

An object of the present invention is to eliminate such conventional drawbacks by performing access processing in parallel when a real address space multiplexed by a plurality of memory units is accessed simultaneously from a plurality of MCUs. The object of the present invention is to provide a memory control method that improves the processing capacity of a shared memory multiprocessor system and eliminates errors in read information to improve reliability.

In the memory control method of the present invention, an MCU that has received an access request to a multiplexed address space first selects a memory unit that is not performing access processing, and then
In the case of a read request, only one memory unit is accessed to eliminate access contention and increase processing power, while in the case of a write request, the data is updated as quickly as possible. After performing access processing on all of the previously selected memory units, the memory units that are being accessed by other MCUs are also accessed immediately when the processing is completed. In particular, this feature prevents data that has not been updated from being read.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a main part logic circuit diagram of an MCU showing an embodiment of the present invention.

In the present invention, processors 1, 2, 3 and MCU 4,
The connections of 5 and 6 and the structure of the main memory address space are as follows:
This is exactly the same as FIG. 2, except for the internal configuration of the MCU and its control operation.

However, the number of memory units and MCUs, and the connections between MCUs and CPUs or MCUs and channels are not limited to the configuration shown in FIG. 2, and may be applied to other system configurations. In Figure 3, 14
is a register that holds the access address sent from the CPU or channel, 15 is a decoder, 16 to 22
is AND gate, 23-25 is NAD gate, 26-3
5 is σR gate, 36-39 is N″0R gate, 40-
42 is an inverter, 43 to 45 are flip-flops, 4
6 is a control mechanism for accessing the memory unit 10;

MCU and 6 also have a similar configuration. Signal line 47 is MC
U4 is a signal line for selecting the memory unit 7, and the logic level "1" indicates that it is being selected.

Similarly, signal lines 48 and 49 are signal lines for the MCU 4 to select memory units 8 and 9, respectively. These signal lines are also connected to MCU and 6. MCU5
, 6, the signal lines 50, 5 corresponding to the signal line 47 are similarly connected.
1, signal lines 52 and 53 corresponding to the signal line 48, and signal lines 54 and 55 corresponding to the signal line 49 are connected to the memory unit and other MCUs. Also, memory unit 7~
10, there are signal lines 56 to 10 that report that the read or write operation in the memory unit has been completed.
59 are connected separately to each MCU. Note that in FIG. 3, signal lines between the MCUs 5 and 6 and between the MCUs 5 and 6 and the memory unit are omitted. less than,
The operation will be explained using MCU4 as an example.

When the CPU or channel 1 receives a request to access a real address belonging to the real address space 13 that is not multiplexed, the control mechanism 46 receives the address in the register 14 and decodes the upper bits of the address in the decoder 15. Performs an access operation to the unit 10.

The control mechanism 46 is connected to the other MCUs 5 and 6 by the memory unit 10.
Begin accessing after confirming that it is not currently being accessed. If another MCU is accessing, wait for its completion before starting the access. When the CPU or channel 1 receives a request to access a real address belonging to the triplexed real address space 12, the flip-flops 43 provided corresponding to the memory units 7, 8, and 9
, 44, 45 are set to ゜゜1゛ by the output of the decoder 15.

On the other hand, whether or not other MCUs are accessing memory units 7-9 is input to N()R gates 36-38 via signal lines 50-55. Flip-flop 43, 44
, 45 and the outputs of N'0R gates 36, 37, and 38 are ANDed by AND gates 17, 18, and 19, respectively. It is input to AND gates 20, 21, and 22. M.C.
When U4 accepts read access, signal line 60
becomes "0", and in this case, the inverter 41 and the 0R gate 31 inhibit the AND gate 21 from becoming "1" when the output of the AND gate 17 is 66r', and the NO
The R gate 39 and the 0R gate 32 indicate that when the output of the AND gate 17 or 18 is 4r', the AND gate 22 is
6F' (However, AND gate 21
(This will not be set to ゜゛0'' when or 22 is already ``1゛''). Also, while accepting read access, 0
R gates 33 to 35, inverter 42, N. 2 of AND gates 20-22 by AND gates 23-25
It is prohibited for more than one to become "1". Now, the operation in the case of read access to the real address space 12 will be explained.

If the MCUs 5 and 6 are not accessing the memory unit 7, this is known because the output of the NOR gate 36 becomes 1', and the output of the AND gate 17 becomes 1'.

Therefore, the outputs of the AND gates 21 and 22 are ゜゛0゛ regardless of the states of the AND gates 18 and 19, and only the AND gate 20 outputs 66F.
The output of 0R gate 35 is "0" and the output of NAND gate 23 is "1". Memory unit 7 is selected and accessed. When the reading is finished in the memory unit 7, an end signal is reported through the signal line 56, and the flip-flops 43 to 45 are all reset to 640° via the 0R gate 30, the AND gate 16, and the 0R gates 27 to 29 (now the readout is completed). Since it is an access, the output of the inverter 40 is "1", and the AND
Gate 16 is open). At this time, 0R gate 26
The output of 0 also becomes 6°0, and it is reported to the CPU and channel that the next access will be accepted. MCU
5 or 6 is accessing memory unit 7,
When the memory unit 8 is not being accessed by any MCU, the output of the AND7 gate 17 is 60', and the output of the AND gate 18 is 1'. For this reason A
The output of the ND gate 20 is "0", and the output of the AND gate 22 is also "0" regardless of the state of the N-width gate 9. Only the AND gate 21 outputs "1" and selects and accesses the memory unit 8. If another MCU finishes accessing the memory unit 7 while accessing the memory unit 8, the output of the AND gate 17 becomes "1". 1゛, the output of the inverter 41 becomes ``0'', but A
Since the output ("1") of the ND gate 21 is input to the 0R gate 31, the N1 gate 21 maintains the state of "1". Also, the output of the AND gate 21 is ゜“
Since it is 1゛, the output of 0R gate 35 is 1゛, NAN
The output voltage of the D gate 23 is "0", and the N1 gate 20 never becomes "1". When the end signal is sent from the memory unit 8 via the signal line 57, the flip-flop 43 is output as described above. .about.45 are all reset to "0" and wait for the next access request. The operation is similar when memory units 7 and 8 are being accessed by another MCU and memory unit 9 is open. Next, in the case of writing to explain the operation when performing write access to a real address belonging to the real address space 12, N, AND
Since the outputs of gates 23 to 25 and 0R gates 31 and 32 are all "゜1゛," AND gates 17, 18, 1
If 9 is ゜“1゛, the corresponding AND gate 2
0, 21, and 22 immediately become "1".

Therefore, writing can be performed simultaneously on all memory units among memory units 7 to 9 that are not accessed by other MCUs. For example, while MCU 5 or 6 is accessing memory unit 8, memory unit 7
, 9 are not accessed by the defective MCU (AND gates 17 and 19 are 1゛, AND gate 18 is
When the write processing end signal is sent from memory unit 7 or 9, both AND gates 20 and 22 become "1" and start writing to memory units 7 and 9 at the same time. (For write access, the signal line 60 is 1, the inverter 40 is 0, and the AND gate 16 is closed.) Only the corresponding flip-flop 43 or 45 is reset to 0, and the flip-flop 44 is reset. do not. M.C.
When U or 36 finishes accessing the memory unit 8, the AND gates 18 and 21 become ``1'' and start writing to the memory unit 8. When writing is finished in all memory units 7 to 9, the flip-flop 43 to 45 reach 4, and report to the CPU and channel that the next access will be accepted via the 0R gate 26.FIG. 4 shows an example of the operation in the embodiment shown in FIG. FIG.

It is assumed that the MCUs 4, 5, and 6 receive requests for access to the real address space 12 at times 61, 62, and 63, respectively.

Further, it is assumed that the time required for access processing is the same for both reading and writing. Figure 4a shows each MCU
This is a case in which the memory units 7, 8, and 9 start accessing the different memory units 7, 8, and 9 immediately upon receiving the access request. FIG. 4b shows a case where the MCU 4 accepts a write access request and the MCUs 5 and 6 accept a read access request. MCU4 is time 61
Immediately after that, writing to all memory units 7, 8, and 9 starts. Since all memory units of MCU5 and MCU6 are being accessed when an access request is received, MCU14 is
Reading starts after waiting until time 64 when the access processing from . In Fig. 4c, MCUs 4 and 5 read out,
This is a case where the MCU 6 receives a write access request. MCU4 and MCU5 immediately start reading, and MCU6
When the access is accepted, writing is immediately started to the memory unit 9 which is vacant. After that, when memory unit 7 finishes the access processing at time 64 and memory unit 8 finishes the access process at time 65, it starts writing to memory units 7 and 8, and ends writing to all memory units at time 68. . Note that FIG. 4d shows an example of the operation of the conventional system, in which reading of the access request from the MCU 5 is delayed from time 62 to 64, and processing of the access request from the MCU is delayed from time 63 to 67. FIG. 5 is a main logic circuit diagram in an MCU showing another embodiment of the present invention.

In Figure 5, when the MCU accepts a read access request to a multiplexed address space and reads from one memory unit that has that address, an uncorrectable error occurs in the read information. When this happens, one or more of the multiplexed memory units is automatically accessed again to improve reliability.

The difference between FIG. 5 and FIG. 3 is that error check circuits 74, 75, and 76 such as CRC circuits are connected to read signal lines 71, 72, and 73, respectively.
4, 75, and 76, as in the past, for example, 2-bit error detection and 1-bit error correction are performed, and when a 2-bit error that cannot be corrected is detected, the output ゛0゛ is output, and when it is correct, 1 When the bit error is corrected, the output ゛゛1゛ is given to the 0R gate 30 and the 0R gates 27, 28, and 29.

That is, in FIG. 3, the access processing end signal is input to the 0R gate 30, but in FIG. When the correct data is not available from the memory unit, the flip-flop 43
~45, only the flip-flops corresponding to that memory unit are reset, and the memory units corresponding to other flip-flops that are not reset can be switched and accessed again.

As explained above, according to the present invention, multiple memories
Accesses from multiple MCUs can be processed at the same time in the real address space configured by multiplexing units, so processing performance is reduced due to access contention on the main memory in multiprocessor systems with shared main memory. In addition, when there is an error in the read data that cannot be corrected, other memory
Since the unit is read, the reliability of main memory can be improved.

[Brief explanation of the drawing]

1 and 2 are block diagrams of a conventional shared main memory multiprocessor system, FIG. 3 is a main logic circuit diagram of a memory control section showing an embodiment of the present invention, and FIG. 4 is a block diagram of a conventional shared main memory multiprocessor system. The operation time chart in the figure and FIG. 5 are main part logic circuit diagrams of a memory control section showing another embodiment of the present invention. 1, 2, 3: processor (CPU) or channel,
4, 5, 6: Memory control unit, 7-10: Memory unit, 11, 12, 13: Real address space, 14: Register, 15: Decoder, 16-22: AND gate, 23
~25: NAND gate, 26~35: 0R gate, 3
6-39: NOR gate, 40-42: Inverter, 4
3 to 45: Flip flop, 46: Memory access control mechanism to unit 10, 47 to 60: Signal line, 6
1-70: Time, 71-73: Read signal line, 74-
76: Check circuit.

Claims (1)

[Scope of Claims] 1. In a multiprocessor system having a plurality of memory control units and a main memory shared by the memory control units and configured by multiplexing a part or the whole with a plurality of memory units, first means for selecting a memory unit that has not been accessed by the memory control unit; and when the access request is a read request, selecting and reading one of the memory units selected by the first means; and when the access request is a write request, writing to all memory units selected by the first means and writing to memory units not selected by the first means. A memory control system characterized by having a third means for writing after waiting for the completion of access processing by another memory control unit. 2. In a multi-processor system having a plurality of memory control units and a main memory shared by the memory control units and partially or entirely multiplexed with a plurality of memory units,
Memory that is not accessed by other memory controllers
a first means for selecting a unit; and when an access request is a read request, a memory selected by the first means;
a second means for selecting and reading one of the units; and a second means for writing to all the memory units selected by the first means when the access request is a write request; A third means waits for the end of the access processing of another memory control unit to write to a memory unit that is not selected by the second means, and a third means reads from one memory unit by the second means. A memory control system comprising a fourth means for re-accessing one or more multiplexed memory units when an uncorrectable error occurs in the output information.