JPS6257050A - Common memory device - Google Patents

Abstract

PURPOSE:To improve throughput of the entire titled device by providing a latch circuit at each processor and reading the priority of the read request of a priority decision circuit from the wire request to eliminate waiting at the contention of request. CONSTITUTION:The priority discrimination circuit is provided to a common memory cell 1 and the priority of the read request is placed higher than the write request. When the read request by a CPU 1 and the write request by a CPU 0 take place simultaneously, a read request signal and a write request signal from each processor are inputted to the priority decision circuit in the cell 1. The priority decision circuit places the priority of the read request of the CPU 1 according to the preset priority. Thus, the request of the CPU 1 is processed with priority and the write request of the CPU 0 is latched in a write data latch circuit 7 and an address latch circuit 6 in the latch circuit 2. Thus, the CPU 0 goes to the next processing step without keeping the waiting state to improve the throughput of the entire device.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a shared memory device configured such that one shared memory can be accessed by a plurality of processors.

2. Description of the Related Art In the past, a plurality of processors were directly connected to a shared memory, and write and read operations were executed as they were each time a write request or read request was received from each processor.

Problems to be Solved by the Invention When using the conventional shared memory device as described above, regardless of writing and reading from a processor, when another processor occupies the shared memory, other processors The processor has to wait until the processor it occupies completes its operation, resulting in a problem of reduced throughput during access contention.

Means for Solving the Problems In order to solve the above problems, the present invention provides a shared memory device configured such that one shared memory can be accessed by a plurality of processors. A latch circuit is provided for temporarily latching data and address information, and a priority determination circuit is provided for monitoring write/read requests from each processor and granting access permission to each processor according to a predetermined priority order. The priority of the priority determination circuit is set to a read request higher than a write request.

Data and address information output from each processor at the time of an operational write or read request are once latched into respective latch circuits. The priority determination circuit monitors write and read requests from all processors, and when a write request and a read request conflict, the processor that has made the read request is given priority over the write request and is first sent to the memory. Access is permitted and read 1 to operations are executed with highest priority regardless of the priority of the processor.

With the above configuration, the throughput of the entire apparatus can be improved for the following reasons. In other words, when reading data from memory, the processor cannot proceed to the next step until the data is completely captured, but when writing data, the process can proceed to the next step as long as the written data is output outside the processor. Is possible. Therefore, if the data and address information output by each processor are once latched in the latch circuit as described above, the processor that has made the write request will have the data and address information latched regardless of the state of the shared memory cell. Once completed, you can proceed to the next step. Therefore, when a write request and a read request from each processor conflict, the processor that made the write request temporarily latches the data and address information in the latch circuit and proceeds to the next step. By immediately granting access to the shared memory cell to the processor that has found it, "waiting" will not occur in the operation of each processor at the time of contention. In this way,
By processing write requests with the highest priority regardless of the priority of the processor, the throughput of the entire device can be improved.

Embodiment Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the latch circuit portion of the shared memory device of the present invention, in which 1 is a shared memory cell, and 2 to 5 are data provided between the shared memory cell 1 and each processor CPU0 to CPU3, respectively. and a latch circuit for latching address information. The internal structure of each latch circuit 2 to 5 is the same, and an address latch circuit 6 that temporarily latches write or read adds from each processor;
It consists of a write data launch circuit γ that temporarily launches write data from each processor, a read data latch circuit 8 that temporarily latches read data from the shared memory cell 1, and a control circuit 9 for operation control.

FIG. 2 is a block diagram of the priority determination circuit, and 21 is a write request signal (W) from each processor CPU0 to CPU3.
RgQo ) to (WREQ3) and read request signal (R
R/W request latch circuit that once latches REQO) to (RREQ3); 22 is a Zoriality encoder that gives a predetermined priority to write requests and read requests from each processor; 23 is a decision made by the Zoriality encoder 22; This is a decoder that outputs access permission signals (RO) to (R3) and (WO) to (W3) according to the priority order. In the above, if the priority order of access to the shared memory of each processor is set as follows: 1) Processor CPU0 2) Processor CPUl 3) Processor CPU2 4) Processor CPU3 Write and read priority for all processors The order is set as follows, and the priorities 1) to 8) are set and stored in the priority encoder 22 in the priority determination circuit.

1) Read processor CPU0 2) Read processor CPUI 3) Read processor CPU2 4) Read processor CPU3 5) Write processor CPU0 6) Write processor CPU1 7) Write processor CPU2 8) Write processor CPU3 Writing In the above configuration, first, as an example, the processor CPU
The operation when there is a read request from I will be described.

A read request signal (RREQ+,
) and the read address is output, the read address is once latched by the address launch circuit 6 in the latch circuit 3. At the same time, the read request signal (RREQI) is latched by the R/W request latch circuit 21 of the priority determination circuit. Priority encoder 22 and decoder 23
receives the read request signal (RREQ l ), and immediately outputs the access permission signal (R1) for the read operation of the processor CPUI on the condition that there is no write/read request from other processors, and this access permission signal (R1) is given to the control circuit 9 in the latch circuit 3. When the control circuit 9 receives the access permission signal (R1),
The read address latched in the address latch circuit 6 is given to the shared memory cell 1, and the data stored at the address is read out. This read data is launched into the read data latch circuit 8 in the latch circuit 3 and then sent to the processor CPUI.
The read operation ends.

Also, to describe the operation when there is a data write request from processor CPU0, processor CPU0
When the write request signal (WRFQo), write data, and write address are output from the write address, the write data and the write address are once latched by the write data latch circuit γ and the address latch circuit 6 in the latch circuit 2, respectively.

At the same time, the write request signal (WREQo) is latched by the R/W request launch circuit 21 of the priority determination circuit.

The priority encoder 22 and the decoder 23 receive the write request signal (WRgQo) and issue an access permission signal (for the write operation of the processor CPU0) on the condition that there is no write/read request from other processors.
WO) immediately. This access permission signal (WO
) is given to the control circuit 9 in the latch circuit 2. When the control circuit 9 receives the access permission signal (WQ), the write address latched in the address latch circuit 6 and the write data latched in the write data latch circuit 7 are given to the shared memory cell 1, and the address location is The data is written to .This completes the write operation by processor CPU0.

Next, when a read request by the processor CPUI and a write request by the processor CPU0 occur simultaneously, a read request signal (RR
EQ, ) and a write request signal (WREQo) are input to the yw request latch circuit 21 of the priority determination circuit. These read request signal (RREQ+) and write request signal (WR
The priority encoder 22 that received the EQo)
Determine which request has the higher priority.

That is, in the case of the present invention, writing of all processors.

As mentioned above, the read priority is set in ranks 1) to 8) with read requests higher than write requests, so the read request signal (RREQ+) is higher than the write request signal (WREQ6). priority. Therefore, when a write request and a read request conflict as described above, the access permission signal (R1) for the read request of the processor CPUI having a higher priority is outputted from the decoder 23 first. This access permission signal (R)
) is output, the latch circuit 3 executes the read operation described above. On the other hand, the lower ranking processor CPU
0 cannot immediately shift to a write operation, but the write data and write address output by the processor CPU0 are once latched by the write data latch circuit 7 and address launch circuit 6 in the latch circuit 2, respectively. Therefore, the processor CPU0 can proceed to the next processing step without continuing the "waiting" state for the write operation at the stage of outputting the write data and the write address to the outside. Therefore, even if there is a conflict between a write request and a read request, the processor that made the write request can proceed to the next processing step immediately after outputting the write data and write address, and the throughput will be reduced by going into a "waiting" state like in the past. This will prevent a decrease in

When the read operation of the processor CPUI is completed, the decoder 23 outputs an access permission signal (WO) for the write operation of the processor CPU0, and the latch circuit 2
receives this access permission signal (WO) and executes the data write operation described above.

Effects of the Invention The present invention has the structure 9 operation as explained above. A latch circuit is provided for each processor to -H launch the data and address information output by each processor, and a read request is issued in the priority determination circuit. Since the configuration is configured such that both write requests and requests are set to a higher priority and access permission is granted according to the priority, even if write/read requests from each processor conflict, each processor's operation will be in a "waiting" state. This eliminates the occurrence of the problem, and has the excellent effect of improving the throughput of the entire device compared to conventional shared memory devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a circuit configuration of a latch circuit portion of a shared memory device according to the present invention, and FIG. 2 is a block diagram showing an example of a circuit configuration of a priority determination circuit portion of a shared memory device according to the present invention. be. CPU0-CPU3: Processor, 1: Shared memory cell, 2-5: Latch circuit, 21: R/W request latch circuit, 22: Zoriality encoder, 23: Decoder.

Claims (1)

[Claims] In a shared memory device configured such that one shared memory can be accessed by multiple processors, a latch circuit is provided between the shared memory cell and each processor to temporarily latch data and address information, and a latch circuit is provided between the shared memory cell and each processor. A priority determination circuit is provided that monitors write/read requests and grants access permission to each processor according to a predetermined priority order, and the priority determination circuit sets read requests higher than write requests. A shared memory device characterized by: