JPS6041332A - Equalizing circuit of transmission line - Google Patents
Equalizing circuit of transmission lineInfo
- Publication number
- JPS6041332A JPS6041332A JP14935483A JP14935483A JPS6041332A JP S6041332 A JPS6041332 A JP S6041332A JP 14935483 A JP14935483 A JP 14935483A JP 14935483 A JP14935483 A JP 14935483A JP S6041332 A JPS6041332 A JP S6041332A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- agc
- transmission line
- control signal
- characteristic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/04—Control of transmission; Equalising
- H04B3/14—Control of transmission; Equalising characterised by the equalising network used
- H04B3/143—Control of transmission; Equalising characterised by the equalising network used using amplitude-frequency equalisers
- H04B3/145—Control of transmission; Equalising characterised by the equalising network used using amplitude-frequency equalisers variable equalisers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Networks Using Active Elements (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はPCMベースバンド伝送方式において伝送路と
して市内ケーブル等の2線式ケーブルを用いた時の伝送
路等化回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission line equalization circuit when a two-wire cable such as a local cable is used as a transmission line in a PCM baseband transmission system.
一般にPCMベースバンド伝送方式では伝送路損失のβ
特性(Jfは周波数)を補償するために等化増幅器系に
おいて等化増幅器出力の尖頭値を検出し、これを制御信
号としてβ特性の自動利得制御(以後Jf A G C
と記す)を施しており。In general, in the PCM baseband transmission system, the transmission path loss is β
In order to compensate for the characteristic (Jf is frequency), the peak value of the equalizing amplifier output is detected in the equalizing amplifier system, and this is used as a control signal to automatically control the β characteristic (hereinafter referred to as Jf A G C
) has been applied.
伝送路符号としてバイポーラ符号を用いているのが通常
である。ここで市内ケーブル等の周波数特性は200〜
300 kHz 以上の領域でJtの損失特性を示すた
め、従来の伝送速度が数Mb/sのような伝送方式でL
伝送路等化としては前述のように、/7 A G Cだ
けを施してやれば充分であったが近年数百k b/ s
程度の低速度な伝送方式が実施される場合には、伝送路
の等化帯域は数に、lz−数百kHz となる。さて前
述の市内ケーブルは200〜300kHz以下の周波数
領域で、−It特性と異った平担な損失特性を示すため
、本例のように低速度な伝送方式の場合では、従来から
のJfAGCだけでは低域部分の等化がなされない為、
等化波形に大きな符号量干渉となって表われる問題があ
る。Bipolar codes are normally used as transmission path codes. Here, the frequency characteristics of city cables etc. are 200~
Since the loss characteristic of Jt is exhibited in the region of 300 kHz or higher, L
As mentioned above, it was sufficient to apply only /7 AGC to equalize the transmission path, but in recent years, the number of hundreds of kb/s has increased.
When a relatively low-speed transmission system is implemented, the equalization band of the transmission line is approximately 1z-several hundred kHz. Now, since the above-mentioned city cable exhibits a flat loss characteristic different from the -It characteristic in the frequency range of 200 to 300 kHz or less, in the case of a low-speed transmission method like this example, the conventional JfAGC Because the low frequency part is not equalized by just
There is a problem that appears as large code amount interference in the equalized waveform.
本発明の目的は等化設計上極めて設計しやすい手段で前
述問題点を解決する伝送路等化回路を提供する事にある
。SUMMARY OF THE INVENTION An object of the present invention is to provide a transmission line equalization circuit that solves the above-mentioned problems by means that are extremely easy to design in terms of equalization design.
本発明の伝送路等化回路は1等化出力から尖頭値検出制
御信号発生回路を経て帰還接続された第1の利得制御回
路を有し、該等化出力から符号量干渉検出制御信号発生
回路を経て帰還接続された第2の利得制御回路を有し、
該第2の利得制御回路カコンデンサとダイオードの並列
接続により入力されるアクティブフィルタにて構成され
、かつダイオードを前記符号量干渉検出制御信号発生回
路にてインピーダンス制御を施すように構成した事を特
徴とする。The transmission line equalization circuit of the present invention has a first gain control circuit which is feedback-connected from the equalized output via the peak value detection control signal generation circuit, and generates a code amount interference detection control signal from the equalized output. a second gain control circuit connected in feedback through the circuit;
The second gain control circuit is composed of an active filter inputted by a parallel connection of a capacitor and a diode, and the diode is configured to perform impedance control in the code amount interference detection control signal generation circuit. shall be.
第1図に従来の伝送路等化回路ブロック図を示す。1は
等化増幅器、2は尖頭値検出をしてAGC制御信号を作
る尖頭値検出・制御信号発生回路。FIG. 1 shows a block diagram of a conventional transmission line equalization circuit. 1 is an equalizing amplifier, and 2 is a peak value detection/control signal generation circuit that detects peak values and generates an AGC control signal.
11は伝送路信号の入力端子、12に等化出力端子、1
3は等化増幅器のAGC制御信号入力端子である。等化
増幅器では前述のように入力端子13からのAGC制御
信号をもとにJf A a c動作を行っているが、低
域部の平担な利得制御(以後フラン)AGCと記す)を
施していないので周波数低域部の等化偏差による符号量
干渉が等化出力に表われる。11 is an input terminal for a transmission line signal, 12 is an equalization output terminal, 1
3 is an AGC control signal input terminal of the equalizing amplifier. As mentioned above, the equalizing amplifier performs the Jf AC operation based on the AGC control signal from the input terminal 13, but it also performs flat gain control (hereinafter referred to as Fran AGC) in the low frequency range. Therefore, code amount interference due to equalization deviation in the low frequency range appears in the equalized output.
次に本発明に゛よる伝送路等化回路の基本構成のブロッ
ク図を第2図に示す。3は各タイムスロットの符号量干
渉を検出しフラン)AGCの制御新婦を作る符号量干渉
検出・制御信号発生回路、4は匠AGC回路、5はフラ
ットAGC回路、14はフラットAGC制御信号入力端
子である。Next, a block diagram of the basic configuration of a transmission line equalization circuit according to the present invention is shown in FIG. 3 is a code amount interference detection/control signal generation circuit that detects code amount interference in each time slot and creates AGC control circuit, 4 is a Takumi AGC circuit, 5 is a flat AGC circuit, and 14 is a flat AGC control signal input terminal. It is.
本発明の実施例を第3図にて詳細に説明する。An embodiment of the present invention will be explained in detail with reference to FIG.
数百kb/s のバイポーラ符号伝送の場合、伝送速度
をf。とすると1等化波形スペクトラムはスペクトラム
の大部分がf/2の近傍に分布する事は周知の事実であ
り、従りて回路2の尖頭値検出制御信号発生部では等化
波形スペクトラムのf。/2近傍部分を検出している事
が分る。また前述の如く市内ケーブルは200〜300
kl(z以上で77特性を示すため、AGC制御回路2
およびAGC回路4によって*fo/♀以上の領域にお
いて尖頭値検出の、/fAG’C制御を施す。一方、f
0/2以下の領域におけるフラン)AGO制御の制御領
域は一%/7 A a c領域と重複しない事が制御特
性の設計及び解析上ばかりか、動作上複雑な帰還ループ
を持たずに安定動作を得るためにも、最適な設計である
。フラットAGC回路5はこうように設計する。フラン
)AGC回路5の周波数特性を第4図に示す。すなわち
、フラン)AGC回路5[f /2 以下で制倖11信
号によりフラットな利得変化を示し、またf。72以上
では伝送路等化として周知のロール・オフ等化をも兼ね
備えている。In the case of bipolar code transmission of several hundred kb/s, the transmission rate is f. It is a well-known fact that most of the spectrum of the 1-equalized waveform spectrum is distributed near f/2. Therefore, in the peak value detection control signal generation section of circuit 2, the f . It can be seen that the area near /2 is detected. Also, as mentioned above, the local cable is 200 to 300
kl (Since it exhibits 77 characteristics above z, the AGC control circuit 2
Then, the AGC circuit 4 performs /fAG'C control to detect the peak value in the region of *fo/♀ or more. On the other hand, f
The control area of AGO control in the range of 0/2 or less does not overlap with the 1%/7 A a c area, which not only improves control characteristic design and analysis, but also ensures stable operation without complicated feedback loops. This is the optimal design to obtain the following. The flat AGC circuit 5 is designed as follows. FIG. 4 shows the frequency characteristics of the AGC circuit 5. That is, the AGC circuit 5 (Fran) exhibits a flat gain change due to the control signal 11 below [f/2; 72 or higher also includes roll-off equalization, which is well known as transmission path equalization.
この動作は第3図中のダイオードD1に流す電流を変化
させてそのインピーダンスを制御する事により実現でき
る。なおダイオードp1を抵抗に置き換えた回路は周知
のアクティブフィルタである。This operation can be realized by changing the current flowing through the diode D1 in FIG. 3 to control its impedance. Note that the circuit in which the diode p1 is replaced with a resistor is a well-known active filter.
このようにして符号量干渉検出制御信号発生回路3にて
AGC回路5のダイオードD1のインピーダンス制御を
施す事により低周波域におけるフラン)AGC動作を実
現し、また尖頭値検出制御信号発生回路2にて従来より
使われているJfAGC回路4を制御する事によ!1l
fo/2以上の周波数域にて”fAGC特性を実現して
おり、周波数域でフラン)AGC動作領域とJfAGC
動作領域が重複する事なく実現している。In this way, by controlling the impedance of the diode D1 of the AGC circuit 5 in the code amount interference detection control signal generation circuit 3, AGC operation in the low frequency range is realized, and the peak value detection control signal generation circuit 2 By controlling the JfAGC circuit 4 conventionally used in the! 1l
AGC operating area and JfAGC are realized in the frequency range above fo/2.
This is achieved without overlapping operating areas.
本発明によれば、伝送路等化としてJ′jAGC特性と
低周波域におけるフラン)AGC特性の両特性を兼ね備
えた伝送路等化回路を極めて設計しやすい回路構成にて
実現する事ができる。According to the present invention, it is possible to realize a transmission line equalization circuit having both the J'j AGC characteristic and the Furan) AGC characteristic in the low frequency range with a circuit configuration that is extremely easy to design.
第1図は従来例を示すブロック図、第2図は本発明の基
本構成を示すブロック図、第3図は本発明の実施例を示
す回路図、第4図は第3図中の7ラツ)AGC回路の周
波数特性を示す特性図である。
1・・・・・・等化増幅器、′2・・・・・・尖頭値検
出制御信号発生回路、3・・・・・・符″号間干渉検出
・制御信号発生回路、4・・・・・・J’j A a
c回路、訃・・・・・フラン)AGC回路、11・・・
・・・伝送路信号入力端子、12・・・−・・等化出力
端子、13・・−・・・JTAGC制御信号入刃端子、
14・・・・・・フラン)AGC制御信号入力端子。
キー田
ン
茅Z7Fig. 1 is a block diagram showing a conventional example, Fig. 2 is a block diagram showing the basic configuration of the present invention, Fig. 3 is a circuit diagram showing an embodiment of the present invention, and Fig. 4 is a block diagram showing the 7 circuits in Fig. 3. ) is a characteristic diagram showing the frequency characteristics of the AGC circuit. 1... Equalization amplifier, '2... Peak value detection control signal generation circuit, 3... Intersymbol interference detection/control signal generation circuit, 4...・・・J'j A a
c circuit, death...furan) AGC circuit, 11...
...Transmission line signal input terminal, 12...--Equalization output terminal, 13...--JTAGC control signal input terminal,
14...Franc) AGC control signal input terminal. Keetan Kaya Z7
Claims (1)
続された第1の利得制御回路を有し、該等化出力から符
号量干渉検出制御信号発生回路を経て帰還接続された第
2の利得制御回路を有し。 該第2の利得制御回路がコンデンサとダイオードの並列
接続により入力されるアクティブフィルタにて構成され
、ダイオードに前記符号量干渉検出制御信号発生回路に
てインピーダンス制御を施すように構成した事を特徴と
する伝送路等化回路。[Scope of Claims] A first gain control circuit is connected in feedback from the equalized output via the peak value detection control signal generation circuit, and the feedback is connected from the equalization output via the code amount interference detection control signal generation circuit. and a second gain control circuit connected thereto. The second gain control circuit is composed of an active filter inputted by a parallel connection of a capacitor and a diode, and the impedance control of the diode is performed by the code amount interference detection control signal generation circuit. transmission line equalization circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14935483A JPS6041332A (en) | 1983-08-16 | 1983-08-16 | Equalizing circuit of transmission line |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14935483A JPS6041332A (en) | 1983-08-16 | 1983-08-16 | Equalizing circuit of transmission line |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6041332A true JPS6041332A (en) | 1985-03-05 |
Family
ID=15473292
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14935483A Pending JPS6041332A (en) | 1983-08-16 | 1983-08-16 | Equalizing circuit of transmission line |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6041332A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4755771A (en) * | 1986-03-12 | 1988-07-05 | Oki Electric Industry Co., Ltd. | Equalizing circuit |
FR2683695A1 (en) * | 1991-11-12 | 1993-05-14 | Carpentier Claude | Method and device for dynamic equalisation |
EP1585279A3 (en) * | 2004-04-09 | 2008-08-27 | Fujitsu Limited | Receiver circuit comprising equalizer |
-
1983
- 1983-08-16 JP JP14935483A patent/JPS6041332A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4755771A (en) * | 1986-03-12 | 1988-07-05 | Oki Electric Industry Co., Ltd. | Equalizing circuit |
FR2683695A1 (en) * | 1991-11-12 | 1993-05-14 | Carpentier Claude | Method and device for dynamic equalisation |
EP1585279A3 (en) * | 2004-04-09 | 2008-08-27 | Fujitsu Limited | Receiver circuit comprising equalizer |
US7508892B2 (en) | 2004-04-09 | 2009-03-24 | Fujitsu Limited | Receiver circuit comprising equalizer |
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