JPS6039835A - Flattening of surface of substrate - Google Patents
Flattening of surface of substrateInfo
- Publication number
- JPS6039835A JPS6039835A JP14652283A JP14652283A JPS6039835A JP S6039835 A JPS6039835 A JP S6039835A JP 14652283 A JP14652283 A JP 14652283A JP 14652283 A JP14652283 A JP 14652283A JP S6039835 A JPS6039835 A JP S6039835A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- groove
- film
- flattening
- polishing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims description 24
- 238000005498 polishing Methods 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 18
- 238000002955 isolation Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000011049 filling Methods 0.000 claims description 6
- 239000004744 fabric Substances 0.000 claims description 2
- 239000003082 abrasive agent Substances 0.000 claims 2
- 230000002093 peripheral effect Effects 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- -1 5i02 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
- Element Separation (AREA)
- Weting (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
［技術分野］
この発明は、基板表面の溝を溝周辺部を含めて埋込み材
料で埋めた後、埋込み材料の表面を機械的研摩によって
堅坦化する上で有効な技術に関するもので、たとえば、
半導体基板の一面に溝を掘り、その溝を絶縁物で埋める
ことによってアイソレーション領域を構成する場合（以
下、溝掘り分離構造という）に利用して有効な技術に関
するものである。[Detailed Description of the Invention] [Technical Field] The present invention is an effective method for filling grooves on the surface of a substrate, including the periphery of the groove, with an embedding material, and then hardening the surface of the embedding material by mechanical polishing. Regarding technology, for example,
The present invention relates to a technique that is effective when forming an isolation region by digging a trench in one surface of a semiconductor substrate and filling the trench with an insulator (hereinafter referred to as trench isolation structure).
［背景技術］
溝掘り分離構造は、高集積な半導体集積回路装置におけ
る素子間分離技術として知られてνする（たとえば、日
経エレク＋−ロニクス、１９８２年３月２９日号、ｐ９
０〜Ｌｏｔ参照）。ただ、これを実用化する場合、溝を
埋める埋込み材料の表面平坦化力（一つの課題になると
考えられる。というのは、溝をポリシリコンあるいは二
酸化シリコンなどの絶縁物で埋めようとする場合、溝幅
が狭１１所は表面力〜平垣な状態に埋めることができる
が、溝幅が広い所、特に深さに比べて幅が広い所には埋
込み材料の表面に大きなくぼみが生じ、したがって、溝
部分以外の余分な埋込み材料をエッチバックした後でも
大きなくぼみはほとんどそのまま残ってしまうからであ
る。[Background Art] The trench isolation structure is known as an element isolation technology in highly integrated semiconductor integrated circuit devices (for example, Nikkei Electronics, March 29, 1982 issue, p. 9).
0~Lot). However, if this is to be put into practical use, the surface flattening ability of the buried material that fills the trenches may become an issue. The 11 places where the groove width is narrow can be filled with a surface force to a flat wall, but where the groove width is wide, especially where the width is wider than the depth, large depressions will occur on the surface of the embedding material, and therefore, This is because even after the excess filling material other than the groove portion is etched back, most of the large depressions remain as they are.
表面の平坦化という点からすると、余分な埋込み材料を
機械的研摩、たとえばポリシングによって除去する方が
良いとされている（後藤、他：高性能バイポーラメモリ
の素子間分離技術、ＩＥＤＭ８２． ｐ５８〜６１）。From the point of view of flattening the surface, it is said that it is better to remove excess embedded material by mechanical polishing, such as polishing (Goto, et al.: Inter-element isolation technology for high-performance bipolar memory, IEDM82. p58-61). ).
しかし１本発明者の実験および検討によれば、機械的研
摩によって、たとえば表面から２μｍ程度の厚さを高精
度に（たとえば±０．１μｒｎ）ウェーハ全面にわたっ
て研摩することはきわめて困難であることが判明した。However, according to the inventor's experiments and studies, it is extremely difficult to polish the entire wafer to a thickness of about 2 μm from the surface with high precision (for example, ±0.1 μrn) by mechanical polishing. found.
［発明の目的コ
この発明の目的は、前記余分な埋込み材料を機械的研摩
によって高精度に研摩することができる基板表面の平坦
化技術を提供することにある。[Object of the Invention] An object of the present invention is to provide a technique for flattening the surface of a substrate by which the excess embedding material can be polished with high precision by mechanical polishing.
この発明の前記ならびにそのほかの目的と新規な特徴は
、この明ＭＡ書の記述および添伺図面から明らかになる
であろう。The above-mentioned and other objects and novel features of the present invention will become clear from the description of this Meiji MA and the accompanying drawings.
［発明の概要］
この出願において開示される発明のうち代表的なものの
概要を簡単に説明すれば、下記のとおりである。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.
すなわち、余分な埋込み材料を機械的研摩によって除去
するに際し、溝以外の基板表面部分に、埋込み材料より
も研摩スピードの遅い耐摩耗性の層を形成し、その耐摩
耗性の層を機械的研摩に対してストッパとして利用する
ことによって、研摩精度の向上を図るものである。In other words, when removing excess embedded material by mechanical polishing, a wear-resistant layer is formed on the surface of the substrate other than the grooves, and the polishing speed is slower than that of the embedded material, and this wear-resistant layer is then mechanically polished. By using it as a stopper, polishing accuracy is improved.
［実施例］
以下に、この発明を半導体集積回路装置における溝掘り
分離構造に適用した実施例を用いて詳しく説明する。[Example] The present invention will be described in detail below using an example in which the present invention is applied to a trench isolation structure in a semiconductor integrated circuit device.
（第１図を参照して）
まず、Ｐ型のシリコン半導体基板１−の表面に、熱酸化
処理により二酸化シリコン膜（Ｓ ｉ ０２膜）２、そ
の上に化学的気相成長法（ＣＶＤ法）によって耐摩耗性
の層であるシリコンナイトライド膜（Ｓｉ３Ｎ４膜）３
を形成した後、それら膜３，２をパターニングすること
によって、溝を形成すべき部分を選択的にエツチングし
除去する。この場合、上層のＳｉ３Ｎ４膜３は溝形成に
対するマスクとして用いるだけでなく、後の機械的研摩
に対するストッパとして利用するものである。したがっ
て、膜３としては、機械的研摩において用いる研摩剤（
たとえば、５ｉ０２の粉末）よりも高い硬度のものを選
ぶべきであり、しかも、溝形成後においても残存し、研
摩に対するストッパ−になり得るような充分な厚さにす
べきである。１ｉｉＪ摩耗性の層３としては、Ｓｉ３Ｎ
４のほかＴａ２０５などを用いることもできる。なお、
下層の二酸化シリコン膜２は基板１のシリコンとシリコ
ンナイトライド膜とが直接接触することによるストレス
軽減のためのもので、通常、上層の膜３よりは薄く形成
される。(Refer to FIG. 1) First, a silicon dioxide film (S i 02 film) 2 is deposited on the surface of a P-type silicon semiconductor substrate 1- by thermal oxidation treatment, and a chemical vapor deposition (CVD) film is deposited thereon. ) is a wear-resistant layer of silicon nitride film (Si3N4 film) 3
After forming the films 3 and 2, the portions where the grooves are to be formed are selectively etched and removed by patterning the films 3 and 2. In this case, the upper Si3N4 film 3 is used not only as a mask for groove formation, but also as a stopper for later mechanical polishing. Therefore, as the film 3, the abrasive used in mechanical polishing (
The hardness should be higher than, for example, 5i02 powder), and it should be thick enough so that it remains after groove formation and can act as a stop for polishing. 1iiJ abrasive layer 3 is Si3N
In addition to 4, Ta205 or the like may also be used. In addition,
The lower silicon dioxide film 2 is used to reduce stress caused by direct contact between the silicon of the substrate 1 and the silicon nitride film, and is usually formed thinner than the upper film 3.
次に、反応性イオンエツチングなどの高指向性のドライ
エツチング技術を用いて基板１のシリコンを除去するこ
とによって、深さ１〜３μｍ程度の溝４１．４２を形成
する。なお、５ｉＯ２１１慎２、Ｓｉ３Ｎ４膜３を形成
した後、その上にさらにＣＶＤ法により５ｉ０２膜を堆
積し、このＣＶＤ−８ｉ ０２膜、Ｓ ｉ ３ Ｎ４膜
３．５ｉ０７膜２をパターニングした後、最上部のＣＶ
Ｄ−３ｉ ０２膜をマスクにして基板Ｓｉｌをエツチン
グし溝４］−９４２を形成しても良い。この方法によれ
ば、エツチング時にＳ ｉ ３ Ｎ４ ｖ３の膜厚が減
少するのを防ぐことができる。Next, trenches 41 and 42 having a depth of approximately 1 to 3 .mu.m are formed by removing silicon from the substrate 1 using a highly directional dry etching technique such as reactive ion etching. Note that after forming the 5iO2 film 2 and the Si3N4 film 3, a 5i02 film is further deposited thereon by the CVD method, and after patterning the CVD-8i 02 film and the Si3N4 film 3.5i07 film 2, the final step is performed. CV at the top
The groove 4]-942 may be formed by etching the substrate Sil using the D-3i02 film as a mask. According to this method, it is possible to prevent the film thickness of S i 3 N4 v3 from decreasing during etching.
（第２図を参照して）
溝４３−，４２の形成後、イオン打込み法によって溝４
１．４２の底部にＰ型不純物のボロンを導入し、ついで
アニールすることによってＰ＋型のチャネルストッパ領
域５を形成する。そして、溝４１．４２の表面を酸化し
て５ｉ０２からなる絶縁膜６を形成してから、ＣＶＤ法
によってポリシリコンからなる埋込み材料７を基板１の
表面全体に堆積する。埋込み材料７の堆積量は、溝４１
−２４２の深さ分は少なくとも必要である。ＣＶＤ法は
被覆性が良いので、幅の狭い溝４１の部分の表面はほと
んど平坦になるが、“幅の広い溝４２０部分の表面には
くぼみ８が生じる。(Refer to Figure 2) After forming the grooves 43- and 42, the groove 4 is formed by ion implantation.
A P+ type channel stopper region 5 is formed by introducing boron as a P type impurity into the bottom of 1.42 and then annealing. Then, the surfaces of the trenches 41 and 42 are oxidized to form an insulating film 6 made of 5i02, and then a filling material 7 made of polysilicon is deposited over the entire surface of the substrate 1 by CVD. The amount of deposited material 7 is
-242 depth is required at least. Since the CVD method has good coverage, the surface of the narrow groove 41 portion becomes almost flat, but the depression 8 is formed on the surface of the wide groove 420 portion.
（第３図を参照して）
前述したとおり、くぼみ８の影響をそれほど受け、ず、
埋込み材料７の表面を平坦化するには、反応性イオンエ
ツチングなどよりも機械的研摩による方が良い。そこで
、ここではＳｉシリコンウェハーの鏡面研摩などと同様
な方法を用いる。すなわち、研摩布からなる回転円盤に
研摩剤を細潰させて回転することによって研摩を行なう
方法である。研摩剤としては、埋込み材料７のポリシリ
コンよりも高い硬度をもつが、耐摩耗性の層３をなすＳ
ｉ３Ｎ４よりも低い硬度をもつｓ；ｏ２Ｊ粉末を用いる
。さらに、ポリシリコンの研摩スピードを上げるためＫ
ＯＨ等のアルカリ性エツチング液を加えても良い。この
場合ポリシリコン、５ｉ０２、Ｓｉ３Ｎ４の各研摩スピ
ードの比はたとえば２４：６：１である。したがって、
研摩スピードの遅い層３を研摩に対するストッパとして
機能させることができ、そのため基板１の表面全体にわ
たり高精度に研摩することができる。なお、研摩が終了
した時点でＳｉ３Ｎ４膜３が残存するようにし、後述す
るポリシリコン酸化時の耐酸化性マスクとする。(Refer to Figure 3) As mentioned above, the effect of the depression 8 is not so great,
In order to flatten the surface of the embedding material 7, mechanical polishing is better than reactive ion etching or the like. Therefore, a method similar to mirror polishing of Si silicon wafers is used here. That is, this is a method in which polishing is carried out by crushing the abrasive into a rotating disk made of abrasive cloth and rotating the disk. As an abrasive, S, which has a higher hardness than the polysilicon of the embedding material 7, but which forms the wear-resistant layer 3, is used.
s;o2J powder, which has a hardness lower than i3N4, is used. Furthermore, in order to increase the polishing speed of polysilicon, K
An alkaline etching solution such as OH may be added. In this case, the polishing speed ratio of polysilicon, 5i02, and Si3N4 is, for example, 24:6:1. therefore,
The layer 3 having a slow polishing speed can function as a stopper for polishing, and therefore the entire surface of the substrate 1 can be polished with high precision. It should be noted that the Si3N4 film 3 remains after the polishing is completed, and is used as an oxidation-resistant mask during polysilicon oxidation, which will be described later.
（第４図を参照して）
表面の研摩処理を終えた後、熱酸化によりポリシリコン
７の表面をＳｉＯ□膜９に変えポリシリコン７を封じ込
める。この時Ｓｉ３Ｎ４膜３はアクティブエリア１０が
酸化されるのを防ぐ役割をする。ついでＳｉ３Ｎ４膜３
をエツチングし除去する。これにより、アイソレーシミ
ン工程を終え。(See FIG. 4) After finishing the surface polishing treatment, the surface of polysilicon 7 is changed into SiO□ film 9 by thermal oxidation to confine polysilicon 7. At this time, the Si3N4 film 3 serves to prevent the active area 10 from being oxidized. Then Si3N4 film 3
Etch and remove. This completes the isolation shimin process.
以後はアクティブエリア１０に公知の方法によりＭＯＳ
ＦＥＴなどの半導体素子をたとえば第５図のように形
成することができる。なお、埋込み材料７としては５ｔ
０２などの他の無機絶縁材料を用いることもでき、その
場合、前記膜９は不要である。 ′
［効果］
（１）溝掘り分離構造において余分な埋込み材料を機械
的研摩によって除去するに際し、溝以外の基板表面部分
に、埋込み材料よりも研摩スピードの遅い耐摩耗性の層
が存在するので、その層が機械的研摩に対するストッパ
として機能する。したがって、基板の表面全体にわたり
高精度な研摩をすることができる。After that, MOS is placed in the active area 10 by a known method.
A semiconductor element such as an FET can be formed as shown in FIG. 5, for example. In addition, the embedding material 7 is 5t.
Other inorganic insulating materials such as 02 may also be used, in which case said membrane 9 is not required. ' [Effects] (1) When removing excess embedded material in a grooved separation structure by mechanical polishing, there is a wear-resistant layer on the surface of the substrate other than the grooves, which is polished at a slower speed than the embedded material. , that layer acts as a stop for mechanical polishing. Therefore, highly accurate polishing can be performed over the entire surface of the substrate.
（２）また、この平坦化技術から、基板の表面の溝の幅
を自由に設定することができ、設計自由度の大きい溝掘
り分離構造が可能である。(2) Furthermore, this planarization technique allows the width of the grooves on the surface of the substrate to be freely set, making it possible to create a grooved isolation structure with a large degree of freedom in design.
以上、この発明を実施例に基づき具体的に説明したが、
この発明は前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲で種々変更可能であることはいう
までもない。たとえば、前記実施例では、溝４１．４２
以外の基板表面部分を全体的に覆うように耐摩耗性の層
３を設けているが、層３を部分的に設けることができる
。This invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof. For example, in the embodiment, grooves 41, 42
Although the wear-resistant layer 3 is provided so as to entirely cover the surface portion of the substrate other than the above, the layer 3 can be provided partially.
［利用分野］
この発明は、半導体の関係のみならず、基板−面の溝を
埋める埋込み材料の表面の平坦化法として広範囲に適用
することができる。[Field of Application] The present invention can be widely applied not only to semiconductors but also as a method for flattening the surface of a buried material for filling trenches on a substrate surface.
テ
第１図〜第４図はこの発明の一実施例を示す工程図であ
る。
１・・・基板（半導体基板）、２・・・二酸化シリコン
膜、３・・・耐摩耗性の層（シリコンナイトライド膜）
、４１．４２・・・溝、５・・・チャネルストッパ領域
、６・・・絶縁膜、７・・・埋込み材料、８・・・くぼ
み、９・・・二酸化シリコン膜、１０・・・アクティブ
エリア、１１・・・ソース・ドレイン層、１２・・・グ
ー１−電極（ポリシリコン）、１３・・・酸化シリコン
層、１４・・・第１パツシベーシヨン膜、１５・・・配
線層、１−６・・・ファイナルパッシベーション膜。
第 １ 図
第 ２ 図
第 ３ 図
第 ４ 図
第 ５２図1 to 4 are process diagrams showing an embodiment of the present invention. 1... Substrate (semiconductor substrate), 2... Silicon dioxide film, 3... Wear-resistant layer (silicon nitride film)
, 41.42... Groove, 5... Channel stopper region, 6... Insulating film, 7... Buried material, 8... Hollow, 9... Silicon dioxide film, 10... Active Area, 11... Source/drain layer, 12... Goo 1-electrode (polysilicon), 13... Silicon oxide layer, 14... First passivation film, 15... Wiring layer, 1- 6...Final passivation film. Figure 1 Figure 2 Figure 3 Figure 4 Figure 52
Claims (1)
た後、埋込み材料の表面を機械的研摩によって平坦化す
る方法であって、前記溝以外の基板表面部分に、前記埋
込み材料よりも研摩スピードの遅い耐摩耗性の層を形成
し、その耐摩耗性の層を前記機械的研摩に対してストッ
パとすることを特徴とする基板表面の平坦化方法。 ２、前記機械的研摩は研摩布と研摩剤によるものであり
、そこで用いる研摩剤の硬度が耐摩耗性の層のそれより
も低い特許請求の範囲第１項に記載の基板表面の平坦化
方法。 ３、前記基板は半導体素子形成のための半導体基板であ
り、前艷溝の部分が素子間の電気的分離のためのアイソ
レーション領域に相当する特許請求の範囲第１項に記載
の基板表面の平坦化方法。 ４、前記溝には、深さよりも幅の方が大きいものが含ま
れる特許請求の範囲第３項に記載の平坦化方法。[Claims] 1. A method of filling a groove on a substrate surface, including the peripheral portion of the groove, with a embedding material, and then flattening the surface of the embedding material by mechanical polishing, the method comprising: A method for planarizing a substrate surface, comprising forming a wear-resistant layer whose polishing speed is slower than that of the embedding material, and using the wear-resistant layer as a stopper against the mechanical polishing. 2. The method for flattening a substrate surface according to claim 1, wherein the mechanical polishing is performed using an abrasive cloth and an abrasive agent, and the hardness of the abrasive agent used therein is lower than that of the wear-resistant layer. . 3. The substrate surface according to claim 1, wherein the substrate is a semiconductor substrate for forming a semiconductor element, and the front groove portion corresponds to an isolation region for electrically separating between elements. Flattening method. 4. The flattening method according to claim 3, wherein the groove includes a groove having a width larger than a depth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14652283A JPS6039835A (en) | 1983-08-12 | 1983-08-12 | Flattening of surface of substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14652283A JPS6039835A (en) | 1983-08-12 | 1983-08-12 | Flattening of surface of substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6039835A true JPS6039835A (en) | 1985-03-01 |
Family
ID=15409550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14652283A Pending JPS6039835A (en) | 1983-08-12 | 1983-08-12 | Flattening of surface of substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6039835A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6394655A (en) * | 1986-10-09 | 1988-04-25 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS647548A (en) * | 1987-01-09 | 1989-01-11 | Philips Nv | Manufacture of semiconductor device |
| JPH01224950A (en) * | 1988-03-04 | 1989-09-07 | Fuji Xerox Co Ltd | Manufacture of optical recording medium |
| US4876216A (en) * | 1988-03-07 | 1989-10-24 | Applied Micro Circuits Corporation | Semiconductor integrated circuit manufacturing process providing oxide-filled trench isolation of circuit devices |
| JPH0376118A (en) * | 1989-08-17 | 1991-04-02 | Shin Etsu Handotai Co Ltd | Manufacture of substrate for semiconductor element formation |
| JPH03148155A (en) * | 1989-10-25 | 1991-06-24 | Internatl Business Mach Corp <Ibm> | Formation of dielctric filling separation trench |
| US5736462A (en) * | 1995-05-15 | 1998-04-07 | Sony Corporation | Method of etching back layer on substrate |
-
1983
- 1983-08-12 JP JP14652283A patent/JPS6039835A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6394655A (en) * | 1986-10-09 | 1988-04-25 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS647548A (en) * | 1987-01-09 | 1989-01-11 | Philips Nv | Manufacture of semiconductor device |
| JPH01224950A (en) * | 1988-03-04 | 1989-09-07 | Fuji Xerox Co Ltd | Manufacture of optical recording medium |
| US4876216A (en) * | 1988-03-07 | 1989-10-24 | Applied Micro Circuits Corporation | Semiconductor integrated circuit manufacturing process providing oxide-filled trench isolation of circuit devices |
| JPH0376118A (en) * | 1989-08-17 | 1991-04-02 | Shin Etsu Handotai Co Ltd | Manufacture of substrate for semiconductor element formation |
| JPH03148155A (en) * | 1989-10-25 | 1991-06-24 | Internatl Business Mach Corp <Ibm> | Formation of dielctric filling separation trench |
| US5736462A (en) * | 1995-05-15 | 1998-04-07 | Sony Corporation | Method of etching back layer on substrate |
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