JPS6038881A - Semiconductor nonvolatile memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION We have heretofore proposed a Puncb-Through injection type memory as a low program voltage, highly integrated, non-volatile ordered memory. FIG. 1 shows a cross-sectional view of a typical example of the PunCh-Through injection type memory. In the case of an N-type memory, a source region 2 which is an N+ type carrier supply region and a drain region 3 which is a carrier absorption region are provided separately on the surface of a P-type semiconductor substrate 1, and the source region 2 and the drain region 3 are separated from each other. A first channel region and a second channel region are provided in the channel region between them, a selection gate electrode 5 is provided on the first channel region via a selection game oxide film 7, and a gate oxide film 6 is provided on the second channel region. This is a structure in which a floating gate electrode 4 is provided via a. The floating gate electrode 4 has strong capacitive coupling with the drain region 3 via the gate oxide film 6ft, and the potential of the floating gate electrode 4 is mainly connected to the drain region 3.
is controlled by the potential of

Information is read from the fact that the conductance of the channel region between the source and drain regions changes depending on the electron density in the floating gate electrode 4.

To write information, that is, to inject electrons into the floating gate electrode 4, Punch-Through, which will be explained next, is used.
Use the injection method.

If the distance 1p between the source region 2 and the floating gate electrode 4 shown in FIG. , and the surface depletion layer 3a of the second channel region intersect, forming a space charge region near the first channel region. The potential of this space charge region decreases as the reverse bias applied to the drain region 3 increases, and electrons flow from the source region 2, which is a carrier supply region, to the drain region 3, which is a carrier absorption region. So-called Punch-
The Tough phenomenon takes place. The surface potential of the second channel region is approximately 52θ compared to the potential of the space charge region.
When the potential barrier between the semiconductor substrate 1 and the gate oxide film 6 becomes lower than V (one voltage of the potential barrier between the semiconductor substrate 1 and the gate oxide film 6), some of the electrons flowing out from the source region 2 due to the punch-'rbrougb phenomenon may enter the floating gate electrode 4. can. for example,! p = 1 μm 1 substrate concentration NA = 1016
atoms ・tyn-” Punch when the surface potential of the second channel region is 7V lower than that of the substrate 1.
ThrOf injection occurs.

Punch Tbv of our proposed structure as above
-ough injection memory is characterized in that the implantation is mainly performed at the tip of the floating gate electrode 4 on the source region side;
Since the injection direction is different from the unch throughb direction, the electron injection efficiency is low, which limits the reduction of the programming voltage.

The present invention can be applied to the conventional Punch Thru as described above.
This invention overcomes the drawbacks of the gh injection type memory and provides a punch through injection type semiconductor nonvolatile memory with high injection efficiency.

The punch through injection type memory of the present invention will be explained in detail with reference to FIGS. 2 to 5.

FIG. 2 is a sectional view of a first embodiment of the semiconductor nonvolatile memory of the present invention. First, the structure will be explained. The case of an N-type semiconductor nonvolatile memory will be explained. A P-type semiconductor substrate 11Vc having a step formed therein, a source region 12 serving as a carrier supply region and a drain region 13 serving as a carrier absorption region are provided via the step region, and an oxide film 16 is formed across the step region and the drain region 15. A floating gate electrode 14 is provided through the gate electrode. In the case of the first embodiment of the present invention shown in FIG. 2, a strong capacitive coupling is formed between the floating gate electrode 14 and the drain region 13 so that the potential of the floating gate electrode 14 can be controlled by the voltage of the drain region 13.

For reading information in the first embodiment, the floating gate electrode 14
The punch-through voltage between the source and drain regions differs depending on the electron density in the region, which is read out.

Next, information is written, that is, electron injection into the floating gate electrode 14 is performed by Puncb Thr between the source and drain regions.
It is done by raising ough. Punch Thro
It is necessary to apply a voltage to the drain region 13 at which the ugh injection occurs. By applying a reverse bias to the drain region 13, a depletion layer 13a is formed in the implanted region adjacent to the floating gate' or pole 14. Depletion in source region 12 @
12a and the depletion layer 13a of the injection region overlap, a space charge region force is formed in the space charge formation region between the source region 12 and the injection region, and punch through occurs.

The conditions for ``punch through injection'' (when no erase voltage is applied between the source region 12 and the substrate 11) can be expressed as follows.

Here, VA; potential difference lp between the potential of the source region 12 and the surface potential of the injection region; distance Wp from the source region 12 to the stepped surface; width of the depletion layer Δψ between the source region 12 and the substrate 11; Space charge due to potential of injection region fb tM Decrease in potential of region 2φf; φfU
This is the Fermi level of the substrate 11. In order for the P-hidden substrate 11 to be reversed, a value of 2φf is required as Δφ.

From equation (1), j! p=1 prn,, NA=1[1
"atDmB°/1n-'.

If Vh = 77, Pu as shown by arrow B in Figure 2
ncb-Throughb injection occurs.

If the structure of the present invention is used, electron injection into the free gate electrode 14 is performed over a wide area of the second channel region, so that PuncB Thro with extremely high injection efficiency can be achieved.
It becomes ugh injection type memory.

In the case of the Punch Through injection memory in which the substrate of the present invention has a step and an injection region is provided in the step region, the potential of the space charge formation region includes not only the potential of the injection region but also the potential outside the semiconductor surface of the space charge formation region. There is a possibility that the person's shadow may be revealed.

In the first embodiment of the present invention shown in FIG. 2, in order to eliminate such instability, a P-type bacteria concentration region 19 is formed on the semiconductor surface.
It is set in 7. Punch
The Throughb phenomenon occurs inside the substrate 11. Therefore, the Punch Tbrougb phenomenon can occur without being influenced by the external potential of the semiconductor. Figure 6 shows Punc.
This is a band diagram showing how the hThrough phenomenon occurs between the source and drain regions and electrons are injected into the floating gate electrode 14. When the potential of the space charge formation region decreases by △φyu2φf, punch ThrO
ugll happens.

Next, FIG. 4 shows a sectional view of a second embodiment of the present invention.

The second embodiment is a further improvement of the first embodiment, and is a memory provided with a selection gate electrode 25t for controlling the potential of the space charge forming region.

When reading information from a memory, in addition to the method of the first embodiment of the present invention, it is also possible to detect the conductance between the source and drain regions by inverting the channel region under the selection gate electrode 25. It can be carried out. In addition, in the write state, the selection gate electrode 25v is set so that the surface of the semiconductor substrate in the space charge formation region is not inverted.
c Apply voltage. The Punch Tbrough phenomenon mostly occurs inside the semiconductor substrate.

Next, FIG. 5 shows a sectional view of a third embodiment of the present invention.

ml and the memory of the second embodiment, the potential of the floating gate electrode was controlled by the potential of the drain region. In the memory of the third embodiment shown in FIG.
In order to control the potential of 4, a control electrode 59'fc is provided on the floating gate electrode 54 via a two-layer film 68.

The drain region 33 and the floating gate electrode 34 are formed to have weak capacitive coupling.

In the memory according to the third embodiment of the present invention, the potential of the implanted region changes depending on the potential of the drain region 53 and the potential of the control gate electrode 69. Reading from the memory is performed by detecting the conductance between the source and drain regions when a constant voltage is applied to the selection gate electrode 35 and the control gate voltage $i39. Floating goo 1: Tochi 6
When electrons enter 4, the conductance decreases. Next, memory writing is performed by applying a voltage to the selection gate electrode 55 that does not invert the semiconductor surface of the space charge type bottom region, applying a large programming voltage to the drain region 33 and the control gate electrode 39, and applying a large programming voltage to the source region. Punch Thr by forming a space charge region between the filter 2 and the injection region.
Perform a deep injection. The source region 32 crosses the potential peak of the space charge region, enters the injection region of the step region, is accelerated within the depletion layer of the injection region, and enters the floating gate.

As described above, by forming an injection region in the stepped region of the surface of the Punch Through injection type semiconductor nonvolatile memory of the present invention, it has become possible to inject electrons into the floating gate electrode in a planar manner. Therefore, the semiconductor non-volatile memory of the present invention, the conventional PunQbThrough
Compared to injection type memory, injection efficiency is higher, resulting in highly integrated, low program voltage semiconductor non-volatile memory.

Although an N-type memory transistor is used in the explanation of the present invention,
It can also be applied to P-type memory transistors. Also,
The term "semiconductor substrate" refers to a semiconductor region in the claims, and includes a semiconductor layer provided on one insulating film.

Further, the selection of writing/reading of the memory cell of the present invention includes the source region, the substrate, and the control ill gate electrode.

Selection of the drain region 1 can be easily made possible by controlling the potential of the gate electrode. In the case of writing, it is necessary to prevent a space charge region from being formed in the space charge formation region for unselected memory cells.

[Brief explanation of drawings]

The first quotient is a plan view of a conventional punch Tbrougb injection type semiconductor injection type semiconductor motovolatile memory, and FIGS.
FIG. 3 is a cross-sectional view of first to fifth embodiments of the h-injection memory. FIG. 5 is a band structure diagram along arrow BvC in FIG. 2. 1.11, 21.31...P-type semiconductor substrate 2.12,
22, 32... Source-resistant region 3.13, 23.33.
...N+ drain region 4.14, 24.34...Floating gate electrode 5.25.35...Selection gate electrode 6.7. B, 16.1 B, 26, 27.2B. 36.37.38...Insulating film and above Applicant: Hirobu Yoda, Director of the Agency of Industrial Science and Technology Applicant: Dainicho Kogoso Co., Ltd./III Figure 2a Figure 3

Claims (4)

[Claims] (1) A first semiconductor region of a first conductivity type with a step region provided on the surface thereof, and a conductivity type opposite to the first conductivity type provided respectively on the surface of the first semiconductor region via the step region. a second N-type carrier supply region and a carrier absorption region; an implantation region provided on the surface of the @1 semiconductor region of the step region so as to be continuous with the carrier absorption region; a first control gate electrode provided on the floating gate electrode via a second insulating film to control the potential of the floating gate electrode; The carriers are the first semiconductor region in which a gear in the supply region operates as the injection region in a high energy state by being drawn into the space charge region by the potential of the injection region controlled by the potential of the carrier absorption region; 1. A semiconductor non-volatile memory, wherein a portion of the semiconductor non-volatile memory is implanted into the floating gate electrode after reaching the surface and exceeding an energy barrier between the first insulating film and the implantation region. (2) A diffusion layer of a first conductivity type having an impurity concentration higher than that of the first semiconductor region is provided on the surface of the space charge forming region.
Semiconductor nonvolatile memory described in Section 1. (3) A second control gate electrode for controlling the potential of the space charge forming region is provided on the space charge region via a sixth gate insulating film.
The semiconductor nonvolatile memory according to item 1 or 2. (4) The semiconductor nonvolatile memory according to any one of claims 1 to 6, wherein the carrier absorption region and the first control gate region are a common region.