JPS6028271A - Vertical type mosfet - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vertical FF MOsFE-rG with reduced on-resistance and reduced threshold voltage.

(Prior art and its problems) As this type of vertical MO8FET, for example, Adolp
h'31ict+ar station, 1981 Acade
mic press (3an Francisco)
rFicld Effect and B related to issuance
ipolar power transistor P
139 of hysicsJ (270p ~ 305p)
has been disclosed.

FIG. 1 shows an example of such a vertical MO8FET. This vertical MO8FET is made by preparing a semiconductor substrate 3 in which an N-type epitaxial layer 2 is formed on an N0-type silicon wafer 1, A goo I-electrode film 6 made of polysilicon is formed on one main surface 4 of this semiconductor substrate 3 via a gate oxide film 5, and then a P-type well region 8 is formed through a source window 7 opened in the gate electrode film 6. and N÷ type source regions 9 are sequentially formed by double diffusion in a self-aligned manner, and by utilizing the lateral diffusion of the 1] type well region 8 and the N type source region 9, the remaining after the diffusion of the source region 4 is formed. A channel portion CI-1 is formed on the surface of the P well region 8.

However, in such a conventional vertical MO8FET, the threshold voltage VTH of the FET is determined by the impurity concentration (the highest impurity concentration) at the source junction surface of the P-well region 8.
When the impurity concentration is increased to lower the resistance of the drain high-resistance layer (epitaxial layer) 2 in order to lower the on-resistance of The depletion layer (indicated by the dotted line in the figure) extending from the gate voltage O
However, once the source region 9 is reached, there is a problem in that a current flows due to pan de-through as shown by the arrow in the figure, which is the so-called chichi tunnel effect.

(Object of the Invention) An object of the present invention is to provide a vertical MOS F E 1- that has low on-resistance and low threshold voltage VTH.

(Structure of the Invention) In order to achieve the object of -F, the present invention provides a main electrode (
The surface of the second conductivity type well region located between the semiconductor substrate of the first conductivity type, which is one of the source electrode or the drain electrode, and the first conductivity type well region, which is the other of the main rri electrode, is attached to the substrate surface. In addition to forming it at an angle to the
The goo 1 to electrode are arranged along the surface of this second conductivity type well region with an insulating film interposed therebetween.

(Description of Embodiments) FIG. 2 is a cross-sectional view of a vertical MOS FET according to the present invention. In the figure, the same components as those in the conventional example are marked with the same reference numerals, and the explanation thereof will be omitted.

As shown in the figure, in this vertical MOS FET, the surface of the P well region 9, which is the source region, and the N-type epitaxial layer 2, which is the drain region. , a slope 1 inclined with respect to the main surface 4 of the base body.
0 is formed, and the gate electrode film 6 is formed on this slope 1.
0 with an insulating film 5 interposed therebetween. Note that CH is a channel section.

Next, the manufacturing process of this vertical MO8FET will be explained with reference to FIG.

First, in the first step, as shown in Figure 3(a), N
A semiconductor substrate 3 having an N-type epitaxial layer 2 is prepared on a green silicon wafer 1, and one main surface 4 of the semiconductor substrate 3 is etched by about 3 μ01 to form a slope 10.

Next, in a second step, a gate oxide film 5 and a gate electrode film 6 made of polysilicon are sequentially laminated on one main surface side of the base 3 as shown in FIG. 3(b).

Next, in the third step, the insulating film 5 and the gate electrode film 6 are removed by etching leaving only necessary portions as shown in FIG. 3(C).

Next, in the fourth step, as shown in FIG. 3(d),
Using the gate electrode film 6 made of polysilicon as a mask,
A P single region 8 is formed by diffusion to a depth of approximately 4 μm.

Next, in the fifth culm, as shown in FIG. 3(e), using a predetermined resist as a mask, a P + 1 small area 11 for electrode extraction is formed in the medium heat part of the P well area 8 by about 0.5 mm. ~1
μmFi! Diffusion formation occurs at a depth of 300°.

Next, in a sixth step, as shown in FIG. 3(f), an N+ well region 9, which will become a resource region, is formed by double diffusion using the gate electrode film 6 as a mask.

Next, in the seventh step, as shown in FIG. 3 (9), an interlayer insulating film 12 made of phosphor glass is formed on the surface of the base 3 by CVD or the like, and then a contact hole 13 is formed by 1 jt.
Form one mouth.

Next, in the eighth step, as shown in FIG. 3(h), an A, EL electrode layer 14 is formed by vapor deposition on the surface of the substrate 3 layered above.

In the vertical MO8FET manufactured by the above process,
The horizontal diffusion of impurities differs between horizontal diffusion and diagonal downward diffusion even if the surface concentration is the same, and the diagonal diffusion is wider, so for the well concentration that gives the same VTH, horizontal lateral diffusion is different. The lateral well area becomes wider. Therefore, it is important to increase VTH even for a train layer with a high impurity concentration, where an effective channel can only be formed to the extent that the drain depletion layer reaches the source region even at a gate voltage of 0 when double-diffused in the horizontal direction. The effective channel length can be increased without causing the so-called channel effect.

Next, FIG. 4 is a diagram showing another example of the manufacturing process of the vertical MO3FET according to the present invention. In this embodiment method, a thick oxide film is formed using a silicon partial oxidation (LOCO8) technique, and a part called a bird's beak formed at that time is used as the slope, and the thick oxide film is 2 well and source regions on the mask! ! ! It is designed to perform diffusion in a self-aligned manner, and a channel can be formed without shifting its position with respect to the slope.

First, in the first step, as shown in Fig. 4<a>, N+
A semiconductor substrate 3 having an N-type 1 bitaxial layer 2 is prepared on a silicon wafer 1, and a thin 3i 02 film (not shown) is formed on the upper surface of the substrate in correspondence with the diffusion portion of the well and source regions, and a CvD film is further formed on it. A Si 3N4 film 20 is formed by the following steps.

Next, in the second step, as shown in FIG. 4(b), the surface of the semiconductor substrate 3 is oxidized to a thickness of about 2 μm, thereby forming a thick 5i layer on the portion not covered with the 3isN+ film 20.
Grow O221. This thick S! A slope 29 called a bird's beak is formed around 0221.

Next, in the third step, as shown in FIG. 4(C), Si
The 3N4 film 20 is removed, and P-type impurities are diffused to a thickness of about 4 μm by ion implantation using the thick 5tO 221 as a mask to form a P well region 22.

Next, in the fourth step, as shown in FIG.
In order to remove the contact 1- of the P well region 22, a high temperature P native impurity diffusion region 23 is formed.

Next, in the fifth step, as shown in FIG. 4(e),
Using 5iO221 as a mask, N-type impurities are diffused to a depth of about 0.5 μm to form an N+ well 22 that will become a source region.
form.

Next, in the sixth step, as shown in FIG. 4(f),
St 0221 was completely removed by etching, and Goo 1-
3i 02 crotch 24. A polysilicon film 25 that will become a negative electrode is sequentially formed by thermal oxidation, CVD, or the like.

Next, in the seventh step, as shown in FIG. 4(q),
After removing the necessary portions of the Si02 film 24 and polysilicon film 25 by etching, a PSG l1ff 26, which will serve as an interlayer insulating film, is formed on the entire surface by CVD, and then a contact hole 27 is formed with a width '?'. I-ru.

Next, in the eighth step, as shown in FIG. 4(h),
An A f layer 28 that will become a source electrode is formed on the entire surface of the substrate 3 by vapor deposition.

In the vertical MO8FET obtained by the above process, L
Since the well region and source region are diffused using the thick oxide film after forming the C slope 1a1 using OGO8 technology as a mask, the slope and channel length can be formed in self-alignment, thereby reducing chip size. The effect of being able to make it smaller is 1q.

(Effects of the Invention) As is clear from the description of each embodiment above, according to the vertical MO8FET according to the present invention, the vertical MO8FET is determined by the impurity concentration of the junction surface between the well region and the source region.
The short channel effect can be suppressed without changing the threshold voltage of T, and a vertical MO8FE'T- with low on-resistance and low threshold voltage can be obtained.

[Brief explanation of the drawing]

FIG. 1 is an element cross-sectional view showing the channel part of a conventional vertical MOS F E'r, and FIG.
A cross-sectional view of the J cord showing the channel part of OS FET,
Figure 3 shows f! when the slope is formed by etching.
The process diagram does not show an example of the A construction process, and Figure 4 shows the slope at LOCO.
8 is a process diagram showing an example of the manufacturing process of a platform in which a channel is formed in a self-aligned manner with respect to a slope. 1... Silicon wafer 2... Epitaxial layer 3... Semiconductor base 4... 1 main surface of base 5... Goo 1 to oxide film 6... Goo 1 to electrode film 8...P Well region 9...N10 region serving as a source 10.29...Slope CH...Channel portion Patent applicant Nissan Motor Co., Ltd. Figure I Figure 2

Claims (1)

[Claims] (1) a semiconductor substrate of a first conductivity type that becomes one of the main electrodes (source electrode or drain electrode);
a well region of a second conductivity type provided on the main surface side; a well region of a first conductivity type provided in the well region of the second conductivity type and serving as the other main electrode; one of the main electrodes; A vertical MO8 comprising a gate electrode disposed on the surface of the substrate with an insulating film interposed between the semiconductor substrate of the first conductivity type and the well region of the first conductivity type, which is the other main electrode.
FET; the surface of the second conductivity type well region located between the first conductivity type semiconductor substrate serving as one of the main electrodes and the first conductivity type well region serving as the other main electrode; A vertical MO8FET characterized in that the slope is inclined with respect to the surface, and the gate electrode is arranged along the slope with an insulating film interposed therebetween.