JPS6027280A - Still camera using solid-state image pickup device - Google Patents

Abstract

PURPOSE:To prevent blooming by applying a bias voltage to a layer of the other conduction type during an exposure time but not applying it during a read time of picture element signals. CONSTITUTION:An image pickup cell array 12 of an MOS solid-state image pickup device 10 consists of a layer, which is formed on a semiconductor substrate of one conduction type and on the other conduction type, and a layer which is formed on a layer of the other conduction type and forms an optical carrier generation area and is one conduction type. The bias voltage which reduces the potential barrier formed by the layer of the other conduction type is applied to the layer of the other conduction type during the exposure time but is not applied during the read time of picture element signals by a control circuit 22, and thus, a video signal without blooming is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a still camera using a solid-state imaging device, and particularly to a still camera using a MOS type solid-state imaging device.

MOS-type solid-state imaging devices are often used in which image sensing cells are arranged two-dimensionally and video signals are read out by specifying vertical and horizontal addresses in this two-dimensional array.

This is typically a metal oxide film semiconductor structure, and more generally a metal insulating film semiconductor (Mis) structure, but here the term "NO5 type" will be used to include all of these. do.

Such an MO8 type solid-state imaging device is advantageously applied as an imaging element to a so-called electronic camera that records video signals on a magnetic recording medium such as a magnetic disk.

In general, solid-state imaging devices have the drawback of blooming phenomenon. As is well known to those skilled in the art, blooming in the MO349 solid-state imaging device occurs when a certain two-dimensional array of imaging cells is irradiated with strong incident light, and photoelectrons that are excessively excited in that cell are adjacent to it. This is caused by overflowing to other cells or vertical signal paths. As a result, in the image produced for 1 f, a row of 11 bright points appears in the vertical direction of the screen centering on the pixel of the strong incident light.

In order to suppress this blooming, for example, a bias voltage is applied to a portion corresponding to the base region of a vertical transistor formed from the optical carrier accumulation region of the imaging cell to the semiconductor substrate of the device structure, and excess carriers are discharged to the substrate. Measures are generally taken to prevent this.

However, in the conventional technology, this bias is always applied, that is, not only when photocharge M is accumulated, but also when photocharge is read out. This results in a black level offset in the signal.

The charge pumping phenomenon occurs when the MOS switches used as horizontal and vertical readout gates are pulse-driven. This is a phenomenon in which a portion of the liquid flows into the substrate due to the bias of the vertical transistor mentioned above, rather than being returned to the drain region.

As is well known, fixed pattern noise is caused by the spike noise generated when the MOS switch as a horizontal readout gate is turned on and off, which varies depending on the stray capacitance between the gate and source and between the gate and drain. This noise is mixed into the video signal as a fixed noise that cannot be removed by the low-pass filter in the circuit.However, in general, this can be canceled out by the integrating circuit as long as it appears approximately evenly in the II: negative l114 polarity. However, if a charge pumping phenomenon occurs by applying a bias to the vertical transistor as described above,
This IF negative/negative polarity spike becomes unbalanced and cannot be canceled out even when integrated.

Further, the television signal has a black level standard set during the horizontal retrace period. However, due to the charge pumping phenomenon in the horizontal and direct reading switches, an offset current flows when both switches are turned off, causing fluctuations in the black level during the horizontal retrace period.

The present invention solves the drawbacks of the prior art and outputs a video signal without blooming.
The purpose is to provide a still camera using a body imaging device.

According to the present invention, there is provided an exposure means for exposing a subject image to an MO9O9 type solid-state imaging device imaging cell array having a two-dimensional array of imaging cells, and an exposure means for controlling the exposure means to expose the imaging cell array for only an exposure period. In a still camera using an MO3 type solid-state imaging device including a control circuit that scans an imaging cell array and reads out pixel signals, each imaging cell is formed on a semiconductor substrate of one conductivity type and a control circuit of the other conductivity type. and a layer of one conductivity type that is formed on the layer of the other conductivity type and forms a photocarrier generation region, and the control circuit applies a bias voltage to the layer of the other conductivity type to lower the potential barrier formed by the layer of the other conductivity type. A voltage is applied to the conductive type layer during the exposure period, and is not applied during the readout period of the pixel signal.

LMJL (7) Dish J Next, embodiments of a still camera using a solid-state imaging device according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, in an embodiment of a still camera using a solid-state imaging differential according to the present invention, an optical solid-state imaging device 10 is positioned at an imaging position behind an imaging lens 14 that captures an object image. An imaging cell array 12 is provided. An optical shutter 1 is provided between the imaging lens 14 and the array 12.
6 is provided, which is opened and closed by a shutter drive mechanism 20 as symbolically indicated by an arrow 18.

The shutter drive mechanism 20 is controlled by a photographing control circuit 22 which controls the apparatus in response to scanning of the camera's shirt release button 40. A video signal output terminal 32 of the solid-state imaging device 10 is connected to a video circuit 36 via a preamplifier 34 and an integrating circuit 46. As will be described later, the integrating circuit 4B is a fixed pattern noise removal circuit that cancels out spike noise of both positive and negative polarities +1 generated by driving the horizontal readout switch 123 by integration.

The device has a clock generator 24, which operates the device 1,! The signal is supplied to the clock imaging device 1o, the imaging control circuit 22, the video circuit 36, and the like. The video circuit 36 is a circuit that responds to the horizontal and vertical synchronizing signals supplied from the clock generator 24 through the control line 42 to form a video signal in, for example, a television signal format, and outputs the video signal to the video signal output terminal 38. . This video signal is used, for example, by being recorded on a magnetic recording medium such as a magnetic disk or displayed on a monitor device.

In this embodiment, the two-dimensional solid-state imaging device 10 includes an imaging cell, that is, a photodiode 120, as shown in FIG.
An imaging cell array 1 having a MOS structure in which cells are arranged in a matrix.
2, and constitutes an MO3 type imaging device that reads out the charging temperature for the selected imaging cell 120 using a so-called XY address method.

Each imaging cell 120 is connected to a vertical readout electrode conductor, ie, a vertical readout path 122, through a source-drain path of a vertical readout switch 121.
The gate of 1 is connected to each stage of vertical scan shift register 128 by vertical addressing line 126. Each vertical readout switch 121 is a readout gate that reads out the photocharges accumulated in the corresponding imaging cell 120 from there to the il iI',+ readout line 122.

In this embodiment, the vertical scanning shift register 128 responds to the two-phase vertical shift clock φV of the clock generator 24, shifts the vertical drive pulse vP of tlt-・ given from the photographing control circuit 22, and shifts the vertical drive pulse vP of tlt-. This is a vertical scanning signal generation circuit that selectively and sequentially activates two vertical addressing lines 12fi.

The readout line 122 is connected to the video signal output terminal through the source/drain path of the horizontal readout switch 123.
r32, horizontal readout electrode conductor i.e. water 1
-Constituting the readout path 124. The gate of each horizontal readout switch 123, that is, the horizontal scanning addressing line 1
25 is connected to each stage of the horizontal scanning shift I register 130. In this embodiment, the horizontal scanning shift register 130 responds to the two-phase water/Il shift clock φH from the clock generator 24, and shifts the single horizontal drive pulse HP given from the photographing control circuit 22. One horizontal address designation v: This is a horizontal scanning signal generation circuit that selectively and sequentially energizes Al25.

A horizontal readout switch 123 connects each vertical readout path 122.
The pixel signals are sequentially read out to the output 32 in series. In this read operation, the vertical shift register 128 responds to the shift clock φV and outputs the vertical drive pulse vP by 1.
While the address line 126 is being activated, the horizontal drive pulse HP supplied from the imaging control circuit 22 to the control line 26 is applied to each of the horizontal scanning shift registers +30 in response to the horizontal shift clock φH. This is done by shifting stages. In this way, this constitutes the MO3 solid-state imaging device 1o of the XY addressing method.

FIG. 3(A) schematically shows the vertical cross-sectional structure of a signal path from any one photodiode 120 shown in FIG. 1 to the output terminal 32 via the vertical readout switch 121 and the horizontal readout switch 123. . In this embodiment, three types of n-type regions 144, 146 and 148 are formed in a p-type epitaxial layer 142 grown on an n-type silicon substrate 140. An insulating layer 150 made of silicon oxide or the like is formed between these layers, and metal conductors 152 and 154 are formed between the n-type regions.

The n-type region 144 forms a photodiode 120 with a pn junction together with the p-type layer 142 below, and the incident light hυ
generates and accumulates photocarriers.

n areas 144, 148. The aforementioned vertical readout switch 121 is formed by the electrode 152 and the insulating layer +50 thereunder, and the n-regions 148, 148 . The horizontal readout switch 123 described in 1)b is formed by the electrode 154 and the insulating layer +50 below. The electrode 15 is in the n region 148.
8 is connected to the output terminal 32. A video power supply 160 having a positive voltage El is connected to this through a resistor 15B as shown in Figure 1.

(The voltage E2 is supplied to the board 140, which may be higher than the video power source E1. Also, as shown in FIGS. 1 and 3,
As shown conceptually at 62 in A), the epitaxial layer 142 is connected to the imaging control circuit 22 by a connecting line 44, from which a pulse 50 of positive voltage E3 is supplied. This will be explained in detail later. Note that in this example, n
Although the channel MO9 configuration is adopted, it goes without saying that the present invention can also be advantageously applied to a p-channel MO9 configuration. In the case of a p-channel MOS, the voltage polarities are all opposite to those in the case of an n-channel.

The operation will be explained with reference to the timing diagram of FIG. When the shirt release button 40 is operated ((A) in the same figure)
, the control circuit 22 responds to this by controlling the shutter drive mechanism 20.
The shutter 16 is opened for the necessary exposure time ((B)). As a result, incident light corresponding to the subject image formed on the imaging cell array 12 is transmitted to the photodiode.
Optical carriers are generated at the pn junction of 20. The control circuit 22' also outputs a bias pulse 50 to the connection line 44 in synchronization with this, and temporarily sets the p-type epitaxial layer 142 to a positive voltage E3.

As conceptually shown in FIG. 3A, a vertical npn transistor 182 is formed by the pn junction of the photodiode 120 and the pn junction of the substrate 140 below.

As shown in Figure (B), according to the energy band structure of the structure in Figure (A) viewed in the lateral direction of the figure, steady state fl:
A potential well 206 is formed in the n region 144 of the photodiode 120 in FIG. If the bias pulse 50 is not applied to the terminal 44, the photocarriers generated excessively in the n-region 144 due to the strong incident light will cross the potential barrier 200 formed by the vertical readout switch +21 and reduce the potential of the vertical readout switch 121. It will overflow even into the well.

However, according to the present invention, as can be seen from FIG. 3(C), which shows the energy band structure when the photodiode 120 is viewed vertically in FIG. 3(A).

11) When the bias pulse 50 of voltage E3 is applied to the epitaxial layer +42, the vertical transistor 1
As the base voltage of 62 increases, which lowers the potential barrier 202 of layer 142, excess photocarriers 204, if generated, flow into n-type substrate 140. In other words, when excess carriers 204 are generated in the n-region 144, the potential of the n-region, that is, the emitter 144, decreases to a potential lower than the base-to-emitter voltage from the base potential E3 of the transistor 162 at that time. 162 is conductive, surplus carrier 204
is discharged onto the substrate 140. As will be seen, voltage E3 may be set to about the base-emitter voltage of transistor 162, for example about 0.7 volts.

In this way, each imaging cell 12 of the imaging cell array 12
0, optical carriers corresponding to the object image formed therein are accumulated. At this time, excess optical carriers generated by strong incident light are discharged to the substrate 140 through the vertical transistor 182 and do not overflow into the vertical signal path 122, so that blooming does not occur.

When the exposure time elapses and the shirt opening 1B closes, the control circuit 22 restores the bias pulse 50 to the O potential (
ER4 diagram (C)). As a result, the epitaxial layer 1
The potential barrier 42 returns to its original high state as shown in FIG. 3(D).

Therefore, the photographing control circuit 22 outputs a vertical drive pulse vP and a horizontal drive pulse HP to the control lines 28 and 2B, respectively (FIG. 4(F) and (G)). These driving pulses vP and IP are input to the first stages of the vertical shift register +28 and the horizontal shift register 130, respectively, and are sequentially applied to each stage in response to the vertical shift clock φV and horizontal shift clock φH supplied from the clock generator 24. Shift (CD) and (E)). Note that FIGS. 4(D) and (E) only show one phase of the two-phase shift clock for simplicity. Due to this shift operation, the photocarriers accumulated in the potential well 206 are
It is read out to the output terminal 32 as a pixel signal.

In this embodiment, the bias pulse 50 is applied to the shutter 16.
It is configured to take a high level in accordance with the opening of . However, as will be clear from the explanation that follows, it does not necessarily have to be configured in this way, and the point is that a high level bias is applied to the epitaxial layer 142 at least during the period when the imaging cell 120 is irradiated with the incident light hυ. However, a high level bias is not applied to the epitaxial layer 142 during the period of reading out pixel signals from the imaging cell 120.

By the way, according to the present invention, the vertical switch 1
21 and the horizontal readout switch 123, no charge bombing phenomenon occurs during the image readout period. Therefore, fixed pattern noise and black level shift due to this do not occur in the video signal.

To explain in detail, for the sake of explanation, it is assumed that the configuration is such that the bias pulse 50 is applied to the epitaxial layer 142 even during the readout period of the video signal. For example, let us take the horizontal readout switch 123 as an example and assume that a horizontal readout pulse 210 as shown in FIG. 5 is applied thereto from the horizontal shift register 130.

First, during the rising period TI of the pulse 210, FIG.
), electrons 212 are transferred from the source region 148 and drain region 148 to the channel region, and in steady state T2, the electrons 212 gather under the gate electrode 154, as shown in FIG. During the period T3 during which the pulse 210 falls, some of the electrons 21 gathered in the channel region
4 returns to source region 14B and drain region 148, while remaining 21B travels down epitaxial layer 142 and is discharged into substrate 140. Therefore, gate electrode 1
The amount of electrons returned to the source region 14B and drain region +48 at the fall of pulse 210 is larger than that injected from the source region 146 and drain region +48 at the rise of pulse 210 into the depletion layer immediately below 54. becomes less.

By the way, as is well known, fixed pattern noise leaks into the horizontal readout line 124 through the stray capacitance between the gate and source and between the gate and drain as the readout switch 123 of the water 11 is turned on and off. Since the spike noise varies depending on the stray capacitance of each element, it is mixed into the video signal as fixed noise that cannot be completely removed by a low-pass filter (not shown) provided in the video circuit 36.

That is, as shown in FIG.
As the spikes 220 and 222 are sequentially driven, the peak value of each spike 220 and 222 varies, but generally they appear almost equally in both positive and negative polarities. Therefore, this can be canceled by integrating in both positive and negative polarities in the integrating circuit 46. Note that the hatched portion 224 in FIG. 6 is the pixel signal component. However, if a bias is applied to the vertical transistor 162 even during the pixel signal readout period as assumed above, an imbalance will occur in the current flowing in and out of the channel depletion layer due to the charge bombing phenomenon, and this polarity will change between positive and negative. The spikes 220 and 222 are no longer equal and do not cancel out when integrated. However, as in the present invention, since the bias pulse 50 is not applied to the epitaxial layer 142 during the read period, the charge bombing phenomenon does not occur, and hence no fixed pattern noise occurs.

The same applies to the black level offset. According to the invention, during the readout period the horizontal readout switch 123
Also, since no charge bombing phenomenon occurs in the vertical readout switch +21, no offset current flows when both switches are turned off, and there is no fluctuation in the black level during the horizontal retrace period.

By configuring the still camera using the solid-state imaging device according to the present invention in this manner, it is possible to output a video signal without blooming.

In particular, since no bias is applied to the vertical transistor of the imaging cell during the video signal readout period, there is no charge pumping phenomenon in the horizontal and vertical readout switches.
Therefore, fixed pattern noise and black level offset caused by this are not included in the video signal 5't.

Although the present invention is embodied as a still camera, the present invention can also be effectively applied to continuous shooting such as a field skimp movie, which is the ultimate in still shooting.

Therefore, the term "still" shall be interpreted broadly to include continuous shooting in this sense.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a still camera using a solid-state imaging device according to the present invention, and FIG. 2 is a schematic diagram showing an example of the circuit configuration of an MO3 type solid-state imaging device used in the embodiment of FIG. 3(A) is a cross-sectional view schematically showing a vertical cross-sectional structure of a signal path from an arbitrary photodiode shown in FIG. 1 to a pixel signal output terminal via vertical and horizontal readout switches; Figure 3 (B) or D) is an energy band diagram showing the energy band structure in the structure shown in Figure 3 (A) corresponding to Figure 3 (A), and Figure 54 appears in each part of the embodiment shown in Figure 1. A waveform diagram showing signal waveforms, FIG. 5 is an explanatory diagram of the charge bombing phenomenon, and FIG. 6 is an explanatory diagram of spike noise included in the video signal. -1's IQ, , , MO3 type solid-state imaging device +2. ,,
Imaging cell array 140. Imaging lens 16, optical shutter 20, shutter drive mechanism 22, photographing control circuit 40, shirt release button 44, connecting line 48, integrating circuit 50, /Haias pulse +20. ,,imaging cell+21. ,, Vertical readout switch edge +23. ．． ．． Horizontal readout Sui Sochi! 42. ．． ．． Epitaxial layer 162, Vertical transistor special feature Applicant: Fuji Photo Film Co., Ltd.

Claims (1)

[Claims] 1. An MO9O9 type solid-state imaging device having a two-dimensional array of imaging cells; an exposure means for exposing a subject image to the imaging cell array; controlling the exposure means to expose the imaging cell array for an exposure period and scanning the imaging cell array; In a still camera using an MO3 type solid-state imaging device including a control circuit for reading pixel signals by reading out pixel signals, the imaging cell has a layer of one conductivity type formed on a semiconductor substrate of one conductivity type, and a layer of the other conductivity type formed on a semiconductor substrate of one conductivity type. A layer of a single conductivity type is formed on the layer of the other conductivity type and forms a photocarrier generation region, and the control circuit is formed on the layer of the other conductivity type.
A still camera using a solid-state imaging device, characterized in that a bias voltage for lowering the E-level barrier is applied to the layer of the other conductivity type during the exposure period, but is not applied during the pixel signal readout period. 2. A still camera according to claim 1, characterized in that the camera includes an integrating circuit that integrates pixel signals read out from the solid-state imaging device to remove fixed pattern noise. .