JPS60258951A - Dynamic memory cell - Google Patents

Abstract

PURPOSE:To contrive the increase of integration and improve the characteristics by a method wherein the intervals between capacitor holes is brought close into the limitation in resolution of an mask aligner with a structure that the conventional oxide film for element isolation has been removed. CONSTITUTION:Holes 81 and 82 are bored in a P<+> layer 12 deeply formed on a P<-> substrate 11, and an N<+> layer 22 is formed around these holes. One electrode of a capacitor C is made of the first poly Si layer 5, and a thin insulation film 32 lays between the N<+> layer 22 serving as the other electrode. The first poly Si layer 5 extends and is connected to the ground potential at a suitable point and acts also as the electrostatic shield plate between the adjacent element. The second poly Si layer 6 extends long into a WL line and forms the switching transistor TR of a memory cell. A contact 21 is formed at the connection part of a bit line 7 and the memory cell. Besides, a P<-> layer 13 decreased in concentration of a P type impurity is formed in the transistor-forming part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a dynamic memory cell as a semiconductor memory device.

[Technical background of the invention and its problems]

In recent years, progress in semiconductor memory devices has shown no signs of slowing down. In particular, dynamic RAMs are the most highly integrated because of their memory cell format, and 256-bit class ones are already in practical use. Also, at the research stage, IM-bit products have recently been produced.

In 1984, the 15SCC introduced a Corrugated Capacitor C (corrugated capacitor), which had a memory cell capacitor in a deep hole in the substrate.
At e1l, a 7t1M bit dynamic RAM using CCC cells was announced. In the case of this type of memory cell, by adjusting the depth of the hole, the storage capacity can, in principle, be increased without being affected by the memory cell size. In such cases, if you try to further increase the density,
It is necessary to reduce the width of the field oxide film for element isolation and the width and spacing of aluminum and polysilicon wiring. The minimum dimensions of these elements are roughly determined by the resolution of the mask aligner used when manufacturing LSIs.

FIG. 6 is a cross-sectional view of the CCC cell described above, and FIG. 7 is drawn to make clear the problems that arise when the cell is further integrated. In other words, this is a description of the case where the distance between the holes that make up the capacitor becomes narrower. In the figure, 1 is a P-type substrate, 21.

22 is an N+ layer, 31 is a field oxide film for isolation between elements,
3. is an oxide film for the capacitor, 4 is a dirt oxide film, 5 is a first polysilicon layer, 6 is a second polysilicon layer, 10 is an oxide film, 7 is a bit line (aluminum) +81+111
2 is a hole, 9 is a P layer for preventing inversion, C is a capacitor formation region, and TR is a transistor formation region.

First, the width of the field oxide film 31 separating each capacitor is determined by the hole 8! And hole 8! I want the interval to be determined. In this case, the hole needs to be opened so as to be self-aligned with the field oxide film 3K, and as can be seen from FIG.
Layer 2□ becomes very thin. In addition, when opening using RIE (ion reaction type etching equipment), etc., the above N+
If the capacitor C is formed due to damage to the second layer or an overhang (reverse level difference) in this urban area, there will be a large amount of leakage current, which will deteriorate the memory characteristics.

Second, as the distance between the carrier and motherboard sides decreases, leakage between cells becomes a problem. In particular, under the field oxide film 31 for element isolation, the depletion layer of the canopy is likely to extend and connect between cells (
punch-through). In such a case, interference between cells will occur, leading to destruction of stored data.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and has a structure in which the conventional field oxide film (insulating film) for isolation between elements is removed, thereby reducing the distance between the holes between capacitors to the resolution limit of the mask aligner. to be able to get close to
Therefore, the present invention aims to provide a dynamic memory cell suitable for high integration.

[Summary of the invention]

In place of the conventional field oxide film for isolation between elements, the present invention uses a highly impurity concentration layer formed deeper than the depth of the capacitor hole, and a conductive layer on top of the layer to shield static electricity. The elements were separated by They also propose a highly integrated dynamic memory cell in which this conductive layer is used as one electrode of a capacitor.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a t4 turn plan view of the same embodiment, and Figure 2 is the ■ of Figure 1.
It is a cross-sectional view along the -■ line.

Since this figure corresponds to that of FIG. 6, the same reference numerals are used for corresponding parts. The plan view of FIG. 1 shows approximately 4 bits of memory cells, and FIG. 2 shows the transistor section TR and the carrier A? for a typical 1 bit. The bottom part C is shown.

The word selection line (wr, line) and the read/write line (
BIT line). The hole wires are made from the second layer of polysilicon, and the BIT wires are made from aluminum. Although this embodiment uses 6 sets of folding bit line systems as the configuration of the memory cell array, the present invention is not limited to this, and it is clear that it is effective for open BIT line systems. It is.

The configuration shown in Figure 2 is a P+
Layer (high concentration layer of Geron I x 10"d) A hole 81e8M is drilled in the snow, two N+ layers are formed around this hole, and the threshold voltage of the MOS capacitor is set to be negative. A P+-N+ junction capacitor is also formed here at the same time.One electrode of the capacitor C is formed of the first polysilicon layer 5, and there is a 100X The first polysilicon layer 5 is extended and connected to the ground potential at an appropriate location.
At the same time, it is peeled off in the transistor part TR and the contact part 2, and acts as an electrostatic shielding plate between the adjacent devices. The second polysilicon layer 6 extends long to form a mammary gland, forming a switching transistor TR of a memory cell. bit line 7
At the connection portion between the memory cell and the memory cell, one contact portion 21 is formed for every two bits.

A P layer 13 with a reduced concentration of P-type impurities is formed in the transistor forming portion.

Next, a method of manufacturing the above structure will be explained with reference to FIG. First, as shown in FIG. 3(a), a P layer 1 is placed on a P type substrate ll.
2 will be provided. Next, as shown in FIG. 3(b), the P+ layer 1
A SiN film 31 is provided on 2, photo-etched to make holes for capacitors, and holes 81.8.8 are formed by RIE. wear it. Next, an A8 doped polysilicon layer 32 is deposited over the entire surface, and this polysilicon layer 32 is heated to form an N+ layer 22 around the holes 81*82. Next, as shown in FIG. 3(C) (84N film 31, polysilicon layer 3
After peeling off the entire surface of the P+ layer 2, a resistive layer 22 is extended on the P+ layer 12 by selectively implanting As fil'' ions for connection to the boundary region with the transistor.
Which Slog film 32' is 100X which is the insulator of the armpit?
&- A first polysilicon layer 5 is formed on the entire surface by thermal oxidation.
Polyforms are formed by f-deposition. This 14th! The silicon layer 5 is selectively removed to form an electrostatic shielding plate for capacitors and isolation between elements. In this part where there is no shielding plate, there is a third
As shown in Figure (C), the first silicon silicon layer 5 for shielding
Using this as a mask, Ast or P, which is an N-type impurity, is deeply implanted using ion implantation technology. Its depth is approximately 0.8~1μ
It is. In this way, P+ in this region is compensated with N-type impurities to form a P layer 1s. Next, as shown in FIG. 3(d), P layer 13. Oxidize the top of the first polysilicon layer 5,
The oxide formed in this step is referred to as a dirt oxide film 4.

Thereon, a second polysilicon layer 6 is further formed by deposition, photolithography is performed to form a transistor, and source and drain diffusions 2 are performed. Then the third
As shown in FIG.
The aluminum wiring 7 is formed, and finally, three protective PSG films are formed by tube deposition to complete the process.

The above method has the following advantages: First, as already mentioned, the process is simplified because elements can be isolated without requiring the field oxide film 31 for element isolation as shown in FIG. Generally, the technology to form a narrow and thick oxide film is very complicated and requires a long process. Second, since the thick oxide film 31 is not required, the hole 8. ,8. There is no overhang in the area.

Therefore, a memory cell with good data retention characteristics can be obtained.

Third, the spacing between elements can be created at the resolution limit of the mask aligner. This makes it possible to create dynamic memory with higher density than ever before. In other words, a larger capacity memory can be obtained with the same chip size. This allows storage costs to be reduced.

Fourthly, since the memory cell is built into the t-P+ layer 1, the reliability of the memory can be improved.

There is, however, very slight crystal disorder within the silicon substrate. This portion usually becomes a source of minority carriers. Minority carriers move within the substrate, are captured in memory cells, and recombine with holes within the cells. A similar situation occurs in the case of minority carriers due to high-energy particles contained in particles and other particles. The former is a hard error in the retention characteristic, and the latter is a temporary failure (soft error). For these minority carriers, increasing the probability of recombination with holes is effective in preventing errors.

In the present invention, the memory cell is made up of P layer 1. Since the structure is formed in the same manner as above, the resistance to these defects can be greatly improved. Fifth
Between the holes 81 and 81, a P+ layer 1. Since a portion of the cell is present, the depletion layer does not extend as in the conventional case, and data interference (/f cross-through) does not occur between cells. Conversely, since the depletion layer does not extend toward the memory cell substrate side, the PN junction capacitance in this portion is large, and as a result, the storage amount can be increased. Sixthly, in the memory cell of the present invention, the P+ layer 13 is counter-doped through the opening of the first polysilicon layer 5 in a self-aligned manner to return the transistor portion and the contact portion to p-. For this,
It is possible to prevent the threshold voltage of the switching transistor from becoming too high, and it is also possible to reduce the PN junction capacitance in the contact portion 2.

This can significantly reduce the pit line capacity. That is, P"-
It is possible to reduce the capacitance of this portion to about 1/10 of the N+ junction capacitance. This makes it possible to reduce the power consumed by charging and discharging all bit lines,
This contributes to lower power consumption.

Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, in the embodiment, the SiO
A layered structure of N and 5IO2 may also be used.

In addition, in the example, the 1st f of Cat4 Shita! silicone layer 5
Although the hole is not completely filled, the hole may be completely filled with the polysilicon layer 5 as shown in FIG.

Further, as shown in FIG. 5, the present invention provides an N+ layer 2 between the capacitor C and the switching transistor TR in FIG.
1 is removed and an insulator 10 is placed on the first polysilicon layer 5.
The second polysilicon layer 6 may be placed on top of the second polysilicon layer 6 through the second polysilicon layer.

In this case, the channel length of the transistor changes depending on the mask alignment, but if the mask alignment accuracy is improved, higher integration is possible.

〔Effect of the invention〕

As explained above, according to the present invention, since the conventional oxide film for isolation between elements is removed, the distance between the capacitor holes can be made close to the resolution limit of the mask aligner. It is suitable for high integration and can realize dynamic memory cells with excellent characteristics.

[Brief explanation of the drawing]

Fig. 1 is a four-turn plan view showing an embodiment of the present invention, Fig. 2 is a sectional view taken along the line ■-■ in Fig. 1, and Fig. 3 is a process showing the steps for obtaining the configuration of the embodiment. The explanatory drawings, FIGS. 4 and 5 are cross-sectional views for explaining other embodiments of the present invention, and FIGS. 6 and 7 are cross-sectional views for explaining conventional memory cells. 13- 11...P- type substrate, 12...P+ layer, 13...
P one layer, 2, . 22...1 layer, 32...oxide film, 4
... dirt oxide film, 5... first polysilicon layer,
6... second polysilicon layer (dart electrode), 7...
Pit line, Jls&2...hole, 21...contact, C...cano-interformation region, TR...transistor formation region. Applicant's agent Patent attorney Takehiko Suzue 14- Figure 4 Figure 5 Figure 6 Figure 7

Claims (2)

[Claims] (1) It has a dynamic memory cell main body in which one MO8 canister and one MOS) transistor form one bit, and the MO8 canister/arm is provided on a first conductivity type semiconductor substrate. a first semiconductor layer of a first conductivity type that is free from the heat and contains impurities of a first conductivity type at a higher concentration than the substrate; and a second semiconductor layer of a second conductivity type is provided around the hole. a conductor layer is provided on the semiconductor layer via an insulating film, and another adjacent memory cell and the second semiconductor layer are electrically isolated by the first semiconductor layer; A dynamic memory cell characterized in that a field insulating film for element isolation is not provided on the semiconductor layer. (2) It has a dynamic memory cell main body in which one MOS capacitor and one MOS transistor form one pit, and the MOS capacitor is provided on a first conductivity type semiconductor substrate and a first conductive type semiconductor substrate. a first semiconductor layer of a first conductivity type containing impurities of a first conductivity type at a higher concentration than the substrate; a second semiconductor layer of a second conductivity type surrounding the hole; A conductor layer is provided on the semiconductor layer via an insulating film,
Another adjacent memory cell and the second semiconductor layer are electrically isolated by the first semiconductor layer, and no field insulating film for element isolation is provided on the semiconductor layer, The MO8) Lanzoster provides a third semiconductor layer of the first conductivity type forming the transistor on the first semiconductor layer, and sets the impurity concentration of the first conductivity type of the third semiconductor layer to the level of the first conductivity type impurity concentration of the third semiconductor layer. A dynamic type memory cell characterized in that the impurity concentration of the first conductivity type layer is lower than that of the first conductivity type.