JPS60253319A - C-mos logical circuit - Google Patents

Abstract

PURPOSE:To decrease the number of desired elements and to facilitate the pattern layout by using an input signal A as the power supply of a C-MOS inverter, applying an input signal B to the connection gates of a pair of MOS transistors (TR) constituting the C-MOS inverter and using the series connection points of said paired MOSTRS as an output terminal. CONSTITUTION:A p channel MOSTRQ21 is provided together with an n channel MOSTRQ22 and an n channel MOSTRQ23. The TRQ21 and TRQ22 constitute a C-MOS inverter, and the TRQ23 delivers an L level of the inverter. If B=H is satisfied with this C-MOS logical circuit, the TRs Q21 and Q22 are turned off and on respectively with an output C=L satisfied. Then the TRs Q21 and TR Q22 are turned on and off respectively with H=L. Then an output C=A is satisfied. In other words, the TRQ23 is turned off with the output C set at H when A=H is satisfied. While the TRQ23 is turned on with the C set at L when A=L is satisfied. That is, the signal A is separated by the signal B. In addition, just three using transistors suffice with the same structure as a C-MOS inverter. Thus the pattern layout is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a C-M method for gating one signal A with another signal B.
Regarding the O3 logic circuit, it is an attempt to reduce the number of constituent elements.

Circuits that gate signal A with another signal B, which has problems with the prior art, are often used for extracting part of a signal, creating a clock, and the like. This circuit is essentially an AND gate, and when constructed from C-MO3, it becomes as shown in FIG. 1 or 2. Q with Figure 1 + al
l, Q2. Qa is a p-channel MO3) transistor, Q3
．． Qa and Qa are n-channel MOS transistors,
Q + -Q a are connected as shown to form an AND gate.

For example, when input signals A and B are both at H (high) level, Ql, Q4 on, Ql, Q2 off, and intermediate outputs are at L (low) level, which is caused by C-MOS inverter Q5.
It is inverted by Qa and becomes an H level output C. Input A, B
If any or all of the above is L, then Q3. Any or all of Qa is off, any or all of Ql and Q2 are on, and the intermediate output becomes H, which is the C-MOS inverter Q5.

It is inverted by Qa and becomes an L level output C. That is, AND logic is performed. Signals A and B are shown in Fig. 1 (A in bl,
When B<H,L, the output C is as shown in the figure, where A is converted to B.
It is cut out by . This circuit requires six transistors, which is a large number of elements.

Also, since n-channel transistors are connected in series (
C3 and C4), it is necessary to increase the channel width.

The circuit shown in FIG. 2 only requires four elements. In this circuit, Qll + Q10 is a p-channel MOS transistor,
C12 and C14 are n-channel MO3) transistors, Qll and C12 are C-MOS switches, and Q10
, Q10 constitute a C-MOS inverter. When input signal B is at H level, the intermediate output is at L level, so transistor QllQ+2 is on, and when A is at H level, output C is also at H level. If A is L level, output C is also L level, and if B is L level, Qll, C1
2 is off, the output C is at L level (assuming it is pulled down). In other words, AND logic is executed,
When the input signals A and B change as shown in Figure 2 (bl), the output C
is as shown in Figure C, which is the same as Figure 1 (bl).

Although the circuit of FIG. 2 has fewer elements than the circuit of FIG. 1, it still requires four elements, and has the problem that the pattern layout is complicated and the area required is large.

OBJECTS OF THE INVENTION The present invention aims to improve the above points and provide a C-MO3 logic circuit for signal gates that uses as few elements as possible and allows easy pattern layout.

Structure of the Invention The present invention provides a C-MO3 logic circuit that gates an input signal A with another input signal B, which includes a C-MOS inverter, uses the input signal A as a power source for the C-MOS inverter, and gates an input signal A with another input signal B. A pair of MO3Is forming a MOS inverter
- applying an input signal B to the mutually connected gates of the transistors;
It is characterized in that the series connection point of the pair of MOS transistors is used as an output end, which will be explained next with reference to embodiments.

Embodiment of the Invention FIG. 3 shows an embodiment of the present invention, in which Q2+ is a p-channel MOS transistor, 022 is an n-channel MOS transistor, C23 is an n-channel MOS transistor, and Q2+ and 022 constitute a C-MOS inverter. death,
C23 outputs the L level of the inverter. C-MO
The power source of the S inverter is the signal A, the input is the signal B, and the input of the transistor 23 is the inverted signal of the signal A. In this circuit, when B=H, 021 is off, 022 is on, output C is on, and when B=L, Q2+ is on, C
22 is off, and the output C=A. That is, if A=H then 02
3 is off and output C is H; if A=L, C23 is on and output C is L. That is, signal A is extracted using signal B. Moreover, the number of transistors used is as few as three, and the structure is just a C-MOS inverter, so the pattern layout is simple.

However, this logic circuit requires an inverted signal A, and in order to generate this, an inverter is required, which increases the number of transistors used. However, when a plurality of gate circuits are used, the inverted signal (2) can be used in common, so the increase in the number of transistors used in the (2) gate circuit light is not significant. An example of this is shown in FIG.

In FIG. 4, Ll, L2. L3 is the C-MO8 logic circuit in FIG. 3, with A, input, Bl, B2 . B3 is an input signal to these, and C1, C2', and C3 are output signals. Signal Bl
``B3 is input to each circuit individually, but the signals A and A are common to each circuit. Therefore, although the ``input'' is not shown, it can be generated from A using one inverter. In the diagram explaining the operation of the circuit, in the logic circuit L1, the input clock A
is gated with signal B1 to produce an output clock C1, and similarly logic circuit L2. At L3, input clock A is connected to signal B2.
B3 is gated to produce output cloths C2 and C3.

6 and 7 are diagrams showing planar patterns of C-MO5 logic circuits. FIG. 6 is the circuit of FIG. 2 ta+, and FIG. 7 is the circuit of FIG. 3. ■ indicates a wiring connected to the positive terminal of the power supply, G indicates a wiring connected to the same negative terminal (ground), and an X mark indicates a contact portion.

Comparing FIGS. 6 and 7, it is clear that the circuit of the present invention allows the pattern to be considerably miniaturized.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, the C-M03i! gates one signal with another signal, which requires a small number of transistors, and facilitates pattern layout. It can be used to construct a logical circuit and is extremely effective.

[Brief explanation of the drawing]

1st v;! J and FIG. 2 are circuit diagrams and waveform diagrams showing the conventional example, FIGS. 3 and 4 are circuit diagrams and block diagrams showing the embodiment of the present invention, FIG. 5 is a waveform diagram for explaining the operation, and FIG.
This figure and FIG. 7 are schematic plan views showing the pattern layout. In the drawing, 021 + 022 are a pair of transistors forming a C-MOS inverter, and C is an output signal. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi Figure 1 (dn (b) (d) (b)

Claims (1)

[Claims] C-MO that gates a certain input signal A with another input signal B
In the S logic circuit, the c-LMosMOS inverter inputs the input signal A to the C-M
It is characterized in that it serves as a power source for an OS inverter, applies an input signal B to the mutually connected gates of a pair of MO3) transistors constituting the c-Mos impark, and uses the series connection point of the pair of MO3) transistors as an output terminal. C-MO
S inverter.