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JPS61103318A - Semiconductor logic circuit - Google Patents

Semiconductor logic circuit

Info

Publication number
JPS61103318A
JPS61103318A JP59225242A JP22524284A JPS61103318A JP S61103318 A JPS61103318 A JP S61103318A JP 59225242 A JP59225242 A JP 59225242A JP 22524284 A JP22524284 A JP 22524284A JP S61103318 A JPS61103318 A JP S61103318A
Authority
JP
Japan
Prior art keywords
circuit
common
elements
input
logic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59225242A
Other languages
Japanese (ja)
Inventor
Masateru Fujii
藤井　正照
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP59225242A priority Critical patent/JPS61103318A/en
Publication of JPS61103318A publication Critical patent/JPS61103318A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce number of elements of the titled circuit by using in common internal transistors (TRs) connected in common in the circuit having plural input NAND or NOR circuits having signal input terminals connected in common. CONSTITUTION:In case of two 2-NAND circuits, transistors (TRs) connected to B and C inputs are used in common to be a TR N2 only, and the number of elements is decreased by one, into seven. Thus, the gate capacity is decreased, the chip area is reduced and the layout is simplified. Further, this effect is increased as the number of input and common terminals is increased.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は０ＭＯ８による半導体論理回路（関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor logic circuit based on 0MO8.

（従来の技術〕 一般に、０ＭＯ８を用いた半導体論理回路としを構成す
る場合、第２図に示すように、２個の２入力ＮＡＮＤ回
路１，２から構成される。この場合、入力端子Ａ、Ｂ、
Ｃのうち端子Ｂが共通の入力端子となり、出力は出力端
子Ｘ、Ｙからとり出されろ。この回路の真理値表は第１
表のように示される。(Prior Art) Generally, when configuring a semiconductor logic circuit using 0MO8, it is composed of two 2-input NAND circuits 1 and 2, as shown in FIG. 2. In this case, input terminals A, B,
Terminal B of C will be the common input terminal, and the output will be taken out from output terminals X and Y. The truth table for this circuit is
Shown as a table.

第１表 この回路ＣＭＯＳで構成する場合、第３図の回路図のよ
うに示される。すなわち、一方のＮＡＮＤ回路ｌは、電
源端子ＶＤＤｖＶＳＳの間に２個のＰチャンネル（Ｐｃ
ｈ））ランジスタＰｉ、　Ｐ、の並列回路と、２個のＮ
ｃｈ　）ランジスタＮ１−Ｎ！の直列回路とを接続した
回路から構成され、他方のＮＡＮ　Ｄ回路２も、同時に
２個のＰｃｈ　）ランジスタＰｓｔＰ４２個のＮｃｈ　
）ランジスタＮ、　、　Ｎ４から構成され、８個の素子
で構成される。Table 1 When this circuit is constructed from CMOS, it is shown as a circuit diagram in FIG. That is, one NAND circuit l has two P channels (Pc
h)) Parallel circuit of transistors Pi, P, and two N
ch) Transistor N1-N! The other NAND circuit 2 also connects two Pch transistors (PstP) and 42 Nch transistors (PstP) in series.
) It consists of transistors N, , N4, and consists of eight elements.

（発明の解決しようとする問題点） 従来の回路では１個の共通入力のある２個のＮＡＮＤ回
路を８個の素子で構成している丸め、素子数が多いとい
う問題がある。本発明は、このような問題を解決し、素
子数の少い論理回路を提供することを目的とする。(Problems to be Solved by the Invention) In the conventional circuit, there is a problem in that two NAND circuits with one common input are constituted by eight elements, and the number of elements is large. The present invention aims to solve such problems and provide a logic circuit with a small number of elements.

（問題点を解決するための手段） 本発明の構成は、共通接続された信号入力端子のある複
数入力のＮＡＮＤあるいはＮＯＲ回路を、ｌ　　　　　
　　複数個有すＡＣＭＯＳ半導体論１０路１３“１・前
記共通接続される内部トランジスタを共有化することに
より、回路の素子蚊を減少させたことを特徴とする。(Means for Solving the Problems) The configuration of the present invention is to connect a plurality of input NAND or NOR circuits with commonly connected signal input terminals to one another.
ACMOS Semiconductor Theory 10 Route 13 "1. A plurality of ACMOS semiconductors are characterized in that the number of circuit elements is reduced by sharing the commonly connected internal transistors.

（実施例） 次に本発明を図面により詳細に説明する。(Example) Next, the present invention will be explained in detail with reference to the drawings.

第１図は本発明の一実施例の回路図で、第３図と同様に
２個の２入力ＮＡＮＤ回路の場合を示している。本実施
例は、第３図におけるＮｃｈ）ランジスタＮｔ　−Ｎ４
を共有化したため、素子数を７としたものでおる。この
ように共通接続端子をもった論理回路は入力回路を一部
共有化できるので、回路が簡単化される。FIG. 1 is a circuit diagram of an embodiment of the present invention, and similarly to FIG. 3, it shows the case of two 2-input NAND circuits. In this embodiment, Nch) transistor Nt −N4 in FIG.
Since the elements are shared, the number of elements is seven. In this way, a logic circuit having a common connection terminal can share part of the input circuit, so the circuit is simplified.

（発明の効果） 以上説明したように、本発明によれば、一部の回路が共
有化できるので、素子数の減少、ゲート容量の削減、チ
ップ面積の減少及びレイアウトの簡素化ができる。この
場合、さらにＮＡＮＤあるいはＮＯＲ回路の入力端子、
及び共通端子の数が多いとその効果はより大きい。(Effects of the Invention) As described above, according to the present invention, some circuits can be shared, so the number of elements, gate capacitance, chip area, and layout can be simplified. In this case, the input terminal of the NAND or NOR circuit,
And, the larger the number of common terminals, the greater the effect.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の回路図、第２図は論理式Ｘ
＝Ａ−１３，Ｙ＝Ｂ−υの論ｍｇｌ！１図、第３■は第
２図の従来の０ＭＯ８による回路図である。 図において、 １．２・・・・・・２入力ＮＡＮＤ回路、Ａ、Ｂ、Ｃ・
・・・・・入力端子、Ｘ、Ｙ・・・・・・出力端子、Ｎ
ｌ−’−Ｎ、・・・・・・Ｎｃｈトランジスタ、Ｐ　ｓ
　ＳＦ３　・・−・＝　Ｐ　ｃｈ／　＃　）ランジスタ
でるる。FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a logical formula
=A-13,Y=B-υ theorymgl! 1 and 3 are circuit diagrams of the conventional 0MO8 shown in FIG. In the figure, 1.2... 2-input NAND circuit, A, B, C...
...Input terminal, X, Y...Output terminal, N
l-'-N,...Nch transistor, Ps
SF3...=Pch/#) Transistor output.

Claims (1)

【特許請求の範囲】[Claims] 共通接続された信号入力端子のある２入力以上のＮＡＮ
Ｄ、ＮＯＲ回路を複数個もったＣＭＯＳ半導体論理回路
において、前記共通接続される内部のトランジスタを共
有化することにより、回路の素子数を減少させたことを
特徴とする半導体論理回路。NAN with two or more inputs with commonly connected signal input terminals
D. A CMOS semiconductor logic circuit having a plurality of NOR circuits, characterized in that the number of elements in the circuit is reduced by sharing the commonly connected internal transistors.
JP59225242A 1984-10-26 1984-10-26 Semiconductor logic circuit Pending JPS61103318A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59225242A JPS61103318A (en) 1984-10-26 1984-10-26 Semiconductor logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59225242A JPS61103318A (en) 1984-10-26 1984-10-26 Semiconductor logic circuit

Publications (1)

Publication Number Publication Date
JPS61103318A true JPS61103318A (en) 1986-05-21

Family

ID=16826224

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59225242A Pending JPS61103318A (en) 1984-10-26 1984-10-26 Semiconductor logic circuit

Country Status (1)

Country Link
JP (1) JPS61103318A (en)

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