JPS60250676A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To suppress a gate leakage without loss of data retaining characteristic by increasing the density of an impurity contained in a floating gate higher than that in the side as compared with the flat part of the gate. CONSTITUTION:The first gate oxide film 31, a floating state 28 doped with phosphorus of density of 4X10<20>cm<-3>, the second gate oxide film 29 and a control gate 30 are formed on a P<-> type Si substrate 21 formed with a field oxide film 22. Then, phosphorus is doped to form the density of phosphorus on the side of the gate 28 to 6X10<20>cm<-3>. Subsequently, with the gate 30 as a mask As<+> is implanted to form N<+> type source and drain regions 33, 34, and the surface of the exposed substrate 21, and gates 28, 30 are converted into oxide film 32. Thus formed, the phosphorus density in the gate 28 becomes higher than the flat part from the side, thereby improving the withstand strength of the gate 30 and the region 34 of the gate 28 and suppressing the gate leakage due to punch through the film 31.

Description

[Detailed description of the invention] [@Ming technology field] The present invention relates to semiconductor memory devices, particularly EFROM.

B'' This improves the reliability of semiconductor storage devices such as FROM devices.

[Technical background of the invention]

Conventionally, two-layer disilico/gate EPROM cells are
It is manufactured by the steps shown in Figures (a) to (d).

First, field oxidation a is applied to the Pfi silicon base rL1 surface.
Substrate 1 surrounded by field oxide film 2
A thermal oxide film 31 that will become a first gate oxide film is formed on the surface. Next, after depositing the first polycrystalline silicon film 4 of 7g2-nainggut over the entire surface, for example, POCI! , is used as a diffusion source to dope phosphorus into the first polycrystalline silicon film 4.

At this time, the phosphorus concentration in the first polycrystalline silicon substrate 4 is 6
It is assumed to be about X l O"Cl1l-". Subsequently, thermal oxidation is performed to form a polysilicon II layer, which will become a second gate oxide film, on the surface of the first polycrystalline silicon lI4.
Form. Subsequently, after depositing a second polycrystalline silicon @6 that will become a control gate on the entire surface, for example, POC
The second polycrystalline silicon film 6 is doped with phosphorus using / as a diffusion source (as shown in FIG. 1(1)). Next, after forming a photoresist pattern 7 on the second polycrystalline silicon film 6, using this as a mask, the second polycrystalline silicon film 6, polysilicon oxide film 5, first polycrystalline silicon film 4, and thermal oxidation are applied. The film 3t is sequentially etched to form a first gate oxide film 8, a floating gate 9, a second gate oxide film io, and a control gate 11 on the substrate 1. Subsequently, As ion implantation is performed to form a source and a drain (as shown in FIG. 3(b)). Next, after removing the photoresist pattern 7, post-oxidation is performed to expose the exposed substrate 1.
1 floating gate 9 and control gate lI
The surface of is converted into a thermal oxide film 12. At the same time, arsenic is activated and the Nff1 source and drain regions 13.1
4f is formed (as shown in the same figure (C)). Next, CV on the entire surface
After depositing the D oxide film 15, a contact hole is opened, and KAj=i is deposited on the entire surface, followed by patterning to form source and drain electrodes 15 and 16f to manufacture an EFROM cell (as shown in FIG. ).

[Problems with background technology]

In order to ensure data retention in the floating gate 9 of the BP[1M cell, the impurity (su0-3) concentration in the floating gate 9 must be as high as 6XlO (m) as described above. On the other hand, as RFROM devices become more highly integrated and operate at higher speeds, the first gate oxide film 8 is required to be made thinner.
If something like a pinhole exists in the floating gate 9, the high concentration impurity in the floating gate 9 penetrates through the first gate oxide film 8t and diffuses into the substrate l, resulting in gate leakage. In addition, the gate electrode t-7 of the peripheral circuit
If a polycrystalline silicon film of Al is used as a zeroing gate, the circuit operation becomes unstable due to similar gate leakage.

This will significantly reduce the reliability and yield of EFROM devices.Similar drawbacks are
Of course, this also occurs in ROM devices.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor memory device that suppresses gate leakage without impairing data retention characteristics and has high reliability and high yield.

[Summary of the invention] - The holding voltage of the floating gate of the EFROM cell or Ei'' FROM cell with respect to the control gate is determined by the polysilicon oxide film formed on the flat surface S (indicated by X in FIG. 1(b)) of the floating gate. It is determined by the smoothness of the interface with the floating gate.In this case, in order to obtain a smooth interface and increase the retention voltage f attached to the control gate, the impurity concentration in the floating gate should be at a certain high concentration (for example, 4 x
However, if the impurity concentration in the flat part of the floating gate is made too high (for example, 6XIQ"m or more), gate leakage tends to occur.

On the other hand, the holding voltage with respect to the drain of the floating gate is determined by the shape of the interface after oxidation of the processing edge (indicated by Y in IT diagram (b)) that is perpendicular to the edge of the floating gate. In this case, it is necessary to obtain a smooth interface shape so that the resistance to the drain is higher than that of the fluting gate. The main feature of this semiconductor memory device is that the concentration is higher on the side surface portions than on the flat portions.

With such a semiconductor memory device, it is possible to suppress leakage without impairing data retention characteristics and improve reliability and yield.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described together with the manufacturing method shown in FIGS. 2(a) to 2(f).

First, a Pg silicon substrate 21 with a specific resistance lO~209-
A field oxide film 22 with a thickness of 1 to 2 μm is formed on the surface of the substrate. Next, a thermal oxide film 23f, which will become a first gate oxide film, is formed to a thickness of 500 on the surface of the element region surrounded by the field oxide film 112, and then B is added to control the threshold value.・Ion implantation is carried out under the conditions of a fast energy of 100 keV and a dose of lXl0''-.Next, the film thickness is 0.4μ by LPCVD@.
After depositing the first polycrystalline silicon film 24 that will become the floating gate of 1.m, POCI is performed.

into the first polycrystalline silicon film 24 by performing thermal diffusion at 1000° C. for 5 minutes using as a diffusion source! j;/14X
Dope at a concentration of 1O”m. Then, dope at 1000°C.
By performing oxidation in a dry oxygen atmosphere of
A polysilicon oxide film 25 is formed to serve as a second gate oxide film.

Subsequently, after depositing a second polycrystalline silicon film 26t which will become a control gate with a film thickness of 0.4 μm on the entire surface, P
As an OCZai diffusion source, thermal diffusion is performed at 1000° C. for 5 minutes to add 4×I phosphorus into the second polycrystalline silicon film 26.
It is doped at a concentration of Q100m'' (as shown in FIG. 2(a)).

Next, after forming a photoresist pattern 2rt- on the second polycrystalline silicon film 26, the second polycrystalline silicon film 2 is etched by reactive ion etching using this as a mask.
6. Sequentially etching the polysilicon oxide film 25 and first polycrystalline silicon film 24, and sequentially stacking fluting gate 2B, second gate oxide film 29, and control gate 30 on thermal oxide film 23: Formation. (Figure (b)
(Illustrated). Subsequently, the photoresist pattern 27f,
After removal, POCI was incubated at 909°C for 5 days with POCI as a diffusion source.
Heat diffusion for 2 minutes and add new phosphorus to 2X l 010c
m-'' (7) Concentration te)''-7'' L, phosphorus concentration on the side surface of the floating gate 28 t-6×1020 儂-
3 (as shown in the same figure (C)).

Next, a part of the thermal oxide film 23 is removed by etching in NH4F, and the first gate oxide film 31 is etched with a rapid energy of 5.
Ion implantation is performed under the conditions of g keV and a dose of 2XlOcrIL (as shown in FIG. 4(d)). Subsequently, thermal oxidation is performed at 1000° C. for 30 minutes in a dry oxygen atmosphere to convert the exposed surfaces of the substrate 2J, floating gate 28, and control gate 30 into a thermal oxide film 32.

At the same time, the ion implantation layer is activated /'8=50Ω
, /ll, xj=Q, 3 pm N-type source and drain regions 33 and 34 are formed (as shown in FIG. 3(e)).
. Next, a CVD oxide film 35 with a thickness of 0.5 μm is provided on the entire surface.
After depositing contact holes, a contact hole is formed, and an A/-S i film having a thickness of 1 and Q pm is deposited over the entire surface, and then patterned to form a source electrode 36 and a drain electrode 43.
7 to manufacture an EFROM cell (same figure (illustrated))
.

However, the above EPROM 7 has a floating gate 2.
Since the phosphorus concentration in the 74-ion conductor 28 is approximately 4X10 cm at the flat part and approximately 6XIO cm at the 20-" side surface, the phosphorus concentration at the interface between the 74-naing groove 28 and the second gate oxide film 29 and at the floating gate 28 is The interface shape of the thermally oxidized @ 32 formed during the etching becomes smooth. Therefore, both the holding voltage of the floating gate 28 with respect to the control gate 30 and the holding voltage with respect to the drain region 34 can be improved. . Moreover, the phosphorus concentration in the flat part of the floating gate 28 is approximately 4×IQ! 0(m), so phosphorus is the first
Gate leakage caused by penetrating through the gate oxide film 31 of , is suppressed. Therefore, the reliability and yield of the EFROM cell can be improved.

In addition, when forming the gate electrode of the transistor in each cycle circuit using the first polycrystalline silicon film which becomes the floating gate, during the second phosphorus diffusion in the process shown in FIG. 82(C), the gate electrode surface KY screen is The phosphorus concentration in the gate electrode can be prevented from becoming higher by means of forming a material or the like. Therefore, is there a way to suppress gate leakage? Reliability can also be improved. This gathering,
IPROM-y device reliability is significantly improved.

In addition, in the above-mentioned example, POClg is
Although the side surface of the floating gate 28 is doped with phosphorus as a diffusion source, the present invention is not limited to this, and for example, PSGrll,
The same effect can be obtained even if the side surfaces of the floating gate 28 are doped with phosphorus by thermal diffusion after depositing phosphorus.

Further, in the above embodiment, the case where the present invention is applied to an EPROM cell was explained, but the present invention is applicable to an E''FROM cell.
Of course, it can be applied to 0M cells.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a ramie conductor memory device with significantly improved reliability and yield.

[Brief explanation of drawings]

FIGS. 1(a) to (d) are cross-sectional views showing the manufacturing process for obtaining a conventional 8-yen M cell, and FIGS. 2(a) to (f) are for obtaining an EPROM cell in an embodiment of the present invention. FIG. 2 No... P-type silicon substrate, 22... Field oxide film, 23... Thermal oxide film, 24... First polycrystalline silicon film, 25... Polysilicon oxide film, 26...・
Second polycrystalline silicon "as z y... photoresist pattern, 28... floating gate, 29...
- Second gate oxide film, 30... Control gate, 31... First gate oxide film, 32... Thermal oxide film, 33. 34... N-type source, drain region, 35.
...CVD oxide film, 36...source electrode. 37...Drain electrode/Applicant's agent Patent attorney Takehiko Suzue Figure 1 2m

Claims (1)

[Claims] A first gate oxide film, a 7P-Ninggut, a second gate oxide film, and a control gate, which are sequentially stacked on a semiconductor substrate of a first conductivity type, and a substrate surface located on both sides of the fluting gate. The second formed in
A semiconductor memory device having a conductive source and drain region, characterized in that the 11k degree of impurity contained in the 70-Teinggut is higher in the side surface portion than in the flat portion of the floating gate. Storage device.