JPS6024593B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and provides a transistor having both an NNN type (PPP type) structure and an NNP type (PPN type) structure, and a semiconductor device using this transistor. be.

An object of the present invention is to provide a MOS transistor with a large gm (mutual conductance) by adopting this structure. First, SOS is formed on silicon formed on an insulating substrate such as sapphire.
An example of the structure of a slave of a (Silicon on Sapphire) type transistor is shown in FIG.

For convenience, an N-channel transistor will be described below, but the same applies to a P-channel transistor. That is, an epitaxial layer of P-type silicon is formed on a sapphire substrate 1, the necessary parts 2 to 4 are removed, a gate 6 is provided through a gate oxide film 5, and N0 is diffused using the gate 6 as a mask to form a source. 2 and a drain 4 are formed. The voltage and current (VDo
-loo) characteristics are shown in FIG. If a potential higher than the threshold voltage (VT) is applied to the gate, the source is grounded, and a positive potential Voo is applied to the drain, a current of 1 will flow between the source and drain as the gate potential VG increases. . flows. There is a non-saturated region A in which loo increases as V blood increases, and a saturated region B in which loo hardly increases even if Voo increases. Third
The figure shows an SOS type CM using a transistor with the structure shown in Figure 1.
An example of the structure of an OS subordinate is shown.

N-type silicon is epitaxially formed on a sapphire substrate 1, and parts other than the necessary portions 2 to 7 are removed, and silicon regions 2, 3, and 4 are filled with P such as boron to form N-channel transistors.
Type impurities are diffused by ion implantation or the like. Or conversely P
Type silicon is epitaxially formed, and N such as phosphorus is applied to silicon regions 5, 6, and 7 where P channel transistors are formed.
The type impurity may be diffused by ion implantation or the like. Gates 9 and 11 are provided through gate oxide films 8 and 10, and N0 is diffused into regions 2 and 4 using gate 9 as a mask.
Using this as a mask, diffusion is applied to regions 5 and 7, respectively, to form a source and a drain. Vss electrode for source 2,
Output electrode common to drains 4 and 5, VoD to source 7
When an input electrode is provided in common to the electrodes and gates 9 and 11,
A CMOS inverter is configured. The CMO in this figure 3
Since the S inverter forms independent N-channel and P-channel transistors, there is a problem that the integrated circuit area becomes large. The present invention aims at higher speed, higher density, and easier manufacturing in transistors and ICs.

Now, an example of an SOS type transistor according to an embodiment of the present invention will be explained with reference to FIG.

A is a cross-sectional structural diagram, and lines 1-1' of B and A are top views,
For convenience, the following description will be made for an N substrate, but the same holds true for a P substrate by reversing P to N. This SOS
To create a transistor, first, a semiconductor such as silane (SiH4) gas or the like is used to etch a layer of N-type (100) silicon about one mountain thick on the (1102) crystal plane of an isolated substrate 1, such as sapphire. grow pitaxially,
remove the silicon layer except for necessary regions 12 to 14, or
Or change it to an insulator by thermal oxidation, etc. An oxide film of about 1200 A is formed on the surface of the silicon by thermal oxidation, and then polycrystalline silicon of about 5000 A is formed on top of it by CVD. The polycrystalline silicon is removed leaving only the gate pattern 16, and then using the gate as a mask, the thin layer described above is formed. The oxide film is removed, leaving the gate oxide film 15. Area 1 of the source part
2 is an N-type material such as phosphorus, and the drain region is in contact with the N-type channel forming region 13 and is shown in FIG. 4B.
An N-type material such as phosphorus is diffused into the region 14b, and a P-type material such as boron is diffused into the remaining region 14b so as to reach the bottom of the silicon layer. Furthermore, after forming a CVD oxide film on the surface as a protective film, Sekiguchi 17 is formed in each source, drain, and gate region.
- 19 are provided and electrode wiring is applied thereto to serve as an electrode terminal. This completes the N-channel MOB transistor. This transistor is composed of regions 12, 13, and 14a, and has an N-channel (deep depletion) cross-sectional structure of NNN.
n-type) first transistor, and regions 12, 13, 14
b, and is parallel to the second transistor whose cross-sectional structure is NNP.

The transistor in FIG. 4 has its source region 12 grounded (V
ss), positive potential (Voo) in the drain region, gate 1
When a positive potential (VG) is applied to 6, it operates as an N-channel transistor, and its voltage/current characteristics are shown in FIG. Curve 1 is N channel (deep depletion
type) (12, 13, 14 in Figure 4)
The current flowing through the part a), the current flowing through the second transistor (12, 13, 14b in Fig. 4),
The curved line shows the current of the transistor of FIG. 4 according to the present invention, and m is the sum of the former two. The operating principle will be explained next.

In the first N-channel transistor, the region 13 in which the channel is formed is also N-type, so a small amount of current flows even when VG=OV, but as Vc increases, it becomes a non-saturated region where loo increases in proportion to VoD. It has a saturation region where loo hardly increases even if VDo increases, resulting in the characteristics shown in FIG. 5.

The current at this time is a current based on minority carriers. Next, the second transistor has a forward breakdown voltage of 0.6V as shown in FIG.
Since it is 0.6V, if Vc<Voo-0.6V, VG becomes effectively negative with respect to the channel region 13, and a depletion layer is formed, making it difficult for current to flow.

The current at this time is a current based on majority carriers. Therefore, if the thickness of the region 13 is thin, when Vc=OV, it will be depleted and the electron density will be low and it can be set to 0. P
The forward current of an N junction is extremely large, but in the case of an SOS type, the PN junction area is sufficiently small, and by providing a gate as shown in Figure 4, two
~3 times the IDo. That is, in the second transistor with this structure, the source 12 is grounded, and the drain 1
When a positive potential VDo is applied to 4a and 14b, regions 12 and 1
3 and 14b are each NNP, so areas 13 and 1
4b PN junction is biased in the normal direction and Voo becomes PN
When the forward breakdown voltage (0.6V) of the junction is exceeded, a source-drain current loo flows.

In this case, the channel is formed inside the region 13, and a conductive channel for majority carriers is formed. When the gate potential VG is zero, VG is effectively negative in the channel forming portion formed by the region 13 near the boundary with the drain. As a result, the depletion layer expands and IDD hardly flows. As VG increases, majority carriers accumulate in the channel forming portion 13, and a drain current due to the majority carriers tends to flow. Constant Vo
However, as VDo increases, electric field concentration occurs and loD tends to be saturated, as in a normal MOS. When compared with the normal IDo-VoD characteristics of the transistor in Figure 1, Ioo increases rapidly from Voo20.6V, and Voo
o》There is a tendency to saturate at 0.6V, and Voo>2
It has the ability to flow a larger current at ~3V than a MOS transistor with a conventional structure of an inversion layer. Although the N channel has been described above, the same characteristics can be obtained even if P and N are configured in reverse to form a P channel.

Since the transistor shown in FIG. 4 according to the present invention has the above-described first and second transistors connected in parallel, Voo>0.
At 6V, two loops are added, and 2 to 3 times the normal current flows, effectively increasing the bonito m (mutual conductance).
will have the following.

Next, FIG. 6 shows another embodiment of an SOS complementary type (CMOS) transistor according to the present invention using the transistor shown in FIG. 4. Figure 6A is a cross-sectional structural view taken along line 1-1' of B;
1 is a top view, and for convenience, the case where an N-type silicon layer is used first will be described, but the same effect can be obtained even if a P-type silicon layer is used by reversing P and N. Regions 12, 13, 14a, 14b, 22, 23,
Gates 16 and 26 made of polycrystalline silicon or the like are provided via gate insulating films 15 and 25 on an N-type silicon layer with a thickness of about 1 skin, which is selectively provided to form the region 12.
N+ diffusion into region 14a. N ten diffusion, P in region 14b
+diffusion, and P+diffusion into regions 22 and 24, respectively, so as to reach the bottom of the silicon substrate. After forming a CVD oxide film (not shown) or the like as a protective film on the surface, three regions 12 and 14a partitioned by gates and gates 16 and 26 are formed.
, 14b and the CVD oxide film on the surface of each of 24 and 22 (
A portion of the electrode metal (not shown) is removed and an electrode metal (not shown) is provided. In this case, common wiring is provided between 14a and 14b using electrodes. Here, in the inverter of FIG. 6, the region 12 is the source, the region 13 is the channel forming part, and the regions 14a and 14b.
The transistor shown in FIG. 4 has a drain as shown in FIG. 4, and a normal P-channel PNPMOS transistor as shown in FIG. The electrode terminal 19 is an output terminal.

Now, in this device, the region 12 is grounded (Vss), and the electrode 14 is at a positive potential (Vss).

. ), and when a gate potential (VG) is applied to the gates 16 and 26, an inverted signal of the gate input signal is output to the output electrode 19. This inverter has the N-channel transistor of the present invention shown in FIG. 4 on the N-channel side and a normal enhancement-type P-channel transistor on the P-channel side. An N-type N-channel transistor may be disposed, and the P-channel transistor of the present invention may be disposed on the P-channel side.

As described above, the semiconductor device according to the present invention has IVcl
．． Since the first transistor (12, 13, 14a in FIG. 4) allows current (idling current) to flow at 6V (PN junction breakdown voltage), it can operate at a low voltage and has an IVGI of 0.
At 6V, the second transistor (12, 13, 1 in Figure 4)
4b) allows a large current to flow, thereby realizing an excellent characteristic of being able to operate at high speed.

[Brief explanation of drawings]

Figure 1 is a conventional structural diagram of an SOS type MOS transistor.
Figure 2 shows the voltage and current characteristics of the element in Figure 1, and Figure 3 shows the S
FIG. 4 shows the structure of an SOS type MOS transistor according to an embodiment of the present invention, A is a cross-sectional structural diagram taken along the line 1-1' of B, B is a top view, and FIG. 4 shows the voltage and current characteristics of the device shown in FIG. 4, and FIG. 6 shows the structure of an SOS type CMOS transistor according to an embodiment of the present invention. B
is a top view. 1... Insulating sapphire substrate, 12, 13...
...Source, channel forming region, 143...
Drain region of the first transistor, 14b... Drain region of the second transistor, 15, 25...
...Gate insulating film, 16, 26...Gate, 1
9... Output electrode, 23... Channel forming region, 24, 28... P-type region, 27...
...Input electrode. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1 A gate is provided on a first conductivity type semiconductor substrate selectively provided on an insulating substrate via a gate insulating film to divide the semiconductor substrate into two regions, and one of the two regions is provided with a first conductivity type high concentration. 1. A semiconductor device, comprising: forming a region, and forming first and second conductivity type high concentration regions adjacent to a channel forming portion under the gate insulating film in the other of the two regions.