[go: up one dir, main page]

JPS60241239A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60241239A
JPS60241239A JP9648684A JP9648684A JPS60241239A JP S60241239 A JPS60241239 A JP S60241239A JP 9648684 A JP9648684 A JP 9648684A JP 9648684 A JP9648684 A JP 9648684A JP S60241239 A JPS60241239 A JP S60241239A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor device
silicon carbide
fin
carbide substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9648684A
Other languages
Japanese (ja)
Inventor
Norihiko Okochi
大河内 敬彦
Keigo Naoi
直井 啓吾
Tomiro Yasuda
安田 富郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9648684A priority Critical patent/JPS60241239A/en
Publication of JPS60241239A publication Critical patent/JPS60241239A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15Ceramic or glass substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3731Ceramic materials or glass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve the heat dissipating characteristic by a method wherein an Si transistor is adhered to an Si carbide substrate of fin-integral structure. CONSTITUTION:A pellet 1 of Si transistor is made integral with the Si carbide ceramic substrate 2' with fins on one surface via solder layer 5. The substrate 2' is made of an SiC sintered body containing 0.1-3wt% of Be or Be compound. The solder layer 5 is made of Au-Si, and the Si is preferably contained at 3- 10atom%. Since an Si carbide substrate of fin-integral structure is used, the thermal fatigue resistance improves.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、半導体装置に係り、特に大電力半導体素子を
搭載するのに好適な熱放散性に優れた半導体装置に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device with excellent heat dissipation properties suitable for mounting a high-power semiconductor element.

〔発明の背景〕[Background of the invention]

半導体装置において、半導体素子により生ずる熱の放散
を助け、半導体素子の搭載部における熱疲労を防止する
という目的で、高熱伝導、電気絶縁性炭化ケイ素セラミ
ックス(熱伝導率二0.6W/’C1熱膨張係数:4x
10−1′/℃以下)ヲ半導体素子支持基板として用い
ることは既に特開昭55−113042で報告されてい
る。しかし、さらにrす放散を効果的なものにするため
には、第1図に示すように炭化ケイ素基板にアルミニウ
ムや銅などで加工された放熱用のフィンをはんだや樹脂
接着剤などで接合しなければならない。しかし、一般的
に、はんだや樹脂接着剤は熱抵抗が大きく、しかも性能
ばらつきを生じ易い接着工程を必要とするため、第1図
の構造は十分とは言えない。さらに、放熱フィンとして
用いるアルミニウムや銅は前記炭化ケイ素基板に比べ熱
膨張係数が極めて大きいため、ヒートサイクルや熱衝撃
により接着層の劣化が生じ熱抵抗が大きくなるという問
題も生じる。
In semiconductor devices, high thermal conductivity, electrically insulating silicon carbide ceramics (thermal conductivity 20.6 W/'C1 Expansion coefficient: 4x
10-1'/°C or less) The use of the material as a semiconductor element support substrate has already been reported in JP-A-55-113042. However, in order to make radiation even more effective, heat radiation fins made of aluminum or copper are bonded to a silicon carbide substrate using solder or resin adhesive, as shown in Figure 1. There must be. However, since solder and resin adhesives generally have high thermal resistance and require a bonding process that tends to cause variations in performance, the structure shown in FIG. 1 cannot be said to be sufficient. Furthermore, since aluminum and copper used as the heat dissipation fins have a much larger coefficient of thermal expansion than the silicon carbide substrate, there is also the problem that the adhesive layer deteriorates due to heat cycles and thermal shock, resulting in increased thermal resistance.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、前述の欠点を改め、フィン構造を有す
る前記炭化ケイ素セラミックス基板を用いて半導体素子
において生ずる熱の放散を助け、半導体素子の搭載部に
おける熱疲労を防止して、高信頼性を有する半導体装置
を提供するものである。
An object of the present invention is to correct the above-mentioned drawbacks, use the silicon carbide ceramic substrate having a fin structure to help dissipate heat generated in a semiconductor element, prevent thermal fatigue in the mounting part of the semiconductor element, and achieve high reliability. The present invention provides a semiconductor device having the following features.

〔発明の概要〕[Summary of the invention]

第1図に示す前記炭化ケイ素セラミックス基板を用いた
半導体装置では、6に示すハンダもしくは樹脂接着剤の
熱抵抗が前記炭化ケイ素セラミックスや放熱フィンであ
るアルミニウム、銅の約10倍程度ある。そのため、1
の半導体素子において生ずる熱の放散性を向上させるた
めには、6の接着層を出来るたけ薄くするか、出来れば
無い方が良い。
In the semiconductor device using the silicon carbide ceramic substrate shown in FIG. 1, the thermal resistance of the solder or resin adhesive shown in 6 is about 10 times that of the silicon carbide ceramic or the heat radiation fins such as aluminum or copper. Therefore, 1
In order to improve the dissipation of heat generated in the semiconductor device, it is better to make the adhesive layer 6 as thin as possible, or to eliminate it if possible.

さらに、前記炭化ケイ素基板は熱膨張係数が4X]、0
−’/℃以下であるのに対し、アルミニウムは23X1
0−’/℃、Cuは1.7 X 10− ’/℃である
ため、接着後ヒートサイクル、熱NMにより接着層劣化
が生じる恐れがある。
Furthermore, the silicon carbide substrate has a thermal expansion coefficient of 4X], 0
-'/℃ or less, while aluminum is 23X1
0-'/°C, and Cu is 1.7 x 10-'/°C, so there is a risk that the adhesive layer will deteriorate due to heat cycles and thermal NM after adhesion.

そこで、本発明では第2図の2′に示すように片面をフ
ィン加工した前記炭化ケイ素基板を用いることにより、
熱抵抗の大きな接着層を無くして熱放散性を向上させる
とともに、熱膨張係数の著しく異なる放熱フィンを除去
することにより接着層劣化を防止することができ、高信
頼性を有する半導体装置を得ることができた。
Therefore, in the present invention, as shown in 2' in FIG. 2, by using the silicon carbide substrate with fin processing on one side,
To improve heat dissipation by eliminating an adhesive layer with large thermal resistance, and to prevent deterioration of the adhesive layer by removing heat dissipating fins having significantly different coefficients of thermal expansion, thereby obtaining a highly reliable semiconductor device. was completed.

〔発明の実施例〕[Embodiments of the invention]

本発明における半導体装置は、第2図に示すようにシリ
コントランジスタペレット1と片面にフィン加工された
前記炭化ケイ素セラミックス基板2′との間に半田層5
を介して一体化したものである。このような構造で得ら
れた半導体装置の熱放散性は、第1図の構造で示される
金属放熱フィンを用いた場合に比べ約20%向上するこ
とがわかった。これは、熱抵抗の大きな接着層6が除去
できたためであると考える。
As shown in FIG. 2, the semiconductor device of the present invention has a solder layer 5 between the silicon transistor pellet 1 and the silicon carbide ceramic substrate 2' having fins on one side.
It is integrated through . It has been found that the heat dissipation performance of the semiconductor device obtained with such a structure is improved by about 20% compared to the case where metal heat dissipation fins shown in the structure of FIG. 1 are used. It is believed that this is because the adhesive layer 6, which has a large thermal resistance, was removed.

SiC焼結体からなるセラミックス基板では、Beとし
て0.1〜3重景%のBe又はBe化合物(B eo、
B e、C等を)を含むSac焼結体からなる組成を有
し、図に示す構造のフィンを有する。焼結は生成形した
後、2000℃で真空中300にα/dの加圧下で行な
われ、室温の熱伝導率0.20CaQ/an ・sec
・℃以上、室温の電気抵抗率1010Ω■以上を有する
In a ceramic substrate made of a SiC sintered body, Be or a Be compound (Be o,
It has a composition consisting of a Sac sintered body containing (Be, C, etc.), and has a fin having the structure shown in the figure. After forming the product, sintering is carried out at 2000°C in vacuum under a pressure of 300°C/d, and the thermal conductivity at room temperature is 0.20CaQ/an sec.
・Has electrical resistivity of 1010 Ω or more at room temperature or higher.

シリコンペレット1と基板2′とはAu−8i牛田が用
いられる。Siは3〜10原子%を含むものが好ましい
。これらの接合に当り、シリコンペレットにAuを蒸着
したもの又はそれを施さないもののいずれでもよく、基
板には同様にAuを蒸着したもの、Auと1〜5重量%
のガラス又は酸化鋼とからなるペーストを焼付して厚膜
としたものが用いられる。
Au-8i Ushida is used for the silicon pellet 1 and the substrate 2'. It is preferable that Si contains 3 to 10 atomic %. For these connections, silicon pellets may be made with or without Au vapor-deposited, and the substrate may be made with Au vapor-deposited in the same way, or 1 to 5% by weight of Au.
A paste made of glass or oxidized steel is baked into a thick film.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、ブイン一体棺造の炭化ケイ素基板を用
いるため、熱放散性及び耐熱疲労向上に効果があるばか
りでなく、放熱フィン接着工程の除去もでき工数低減の
効果もある。
According to the present invention, since a silicon carbide substrate having a single-piece structure is used, it is not only effective in improving heat dissipation performance and thermal fatigue resistance, but also the process of bonding heat dissipation fins can be eliminated, thereby reducing the number of man-hours.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の高熱伝導炭化ケイ素基板と金屈放然フ′
インとを組み合わせた半導体装置の説明図。 第2図は本発明によるフィン加工された産熱伝導炭化ケ
イ素基板を用いた半導体装置の説明図である。
Figure 1 shows a conventional high thermal conductivity silicon carbide substrate and a gold-plated silicon carbide substrate.
FIG. FIG. 2 is an explanatory diagram of a semiconductor device using a fin-processed heat-generating conductive silicon carbide substrate according to the present invention.

Claims (1)

【特許請求の範囲】[Claims] 1、高熱伝導、電気絶縁性炭化ケイ素基板を用いた半導
体装置において、前ill!ti>化ケイ素基板がフィ
ン構造を有することを特徴とする半導体装置。
1. In semiconductor devices using high thermal conductivity and electrically insulating silicon carbide substrates, the previous ill! A semiconductor device characterized in that a silicon oxide substrate has a fin structure.
JP9648684A 1984-05-16 1984-05-16 Semiconductor device Pending JPS60241239A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9648684A JPS60241239A (en) 1984-05-16 1984-05-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9648684A JPS60241239A (en) 1984-05-16 1984-05-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60241239A true JPS60241239A (en) 1985-11-30

Family

ID=14166394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9648684A Pending JPS60241239A (en) 1984-05-16 1984-05-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60241239A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6489448A (en) * 1987-06-23 1989-04-03 Texas Instruments Inc High-performance heat sink and mounting member of semiconductor products, and manufacture thereof
JPH0160545U (en) * 1987-10-12 1989-04-17
WO1999025022A1 (en) * 1997-11-10 1999-05-20 Parker-Hannifin Corporation Non-electrically conductive thermal dissipator for electronic components
US6705388B1 (en) 1997-11-10 2004-03-16 Parker-Hannifin Corporation Non-electrically conductive thermal dissipator for electronic components
JP2019207992A (en) * 2018-05-30 2019-12-05 京セラ株式会社 Package for mounting electrical element and electrical apparatus

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6489448A (en) * 1987-06-23 1989-04-03 Texas Instruments Inc High-performance heat sink and mounting member of semiconductor products, and manufacture thereof
JPH0160545U (en) * 1987-10-12 1989-04-17
JPH0543483Y2 (en) * 1987-10-12 1993-11-02
WO1999025022A1 (en) * 1997-11-10 1999-05-20 Parker-Hannifin Corporation Non-electrically conductive thermal dissipator for electronic components
US6705388B1 (en) 1997-11-10 2004-03-16 Parker-Hannifin Corporation Non-electrically conductive thermal dissipator for electronic components
JP2019207992A (en) * 2018-05-30 2019-12-05 京セラ株式会社 Package for mounting electrical element and electrical apparatus

Similar Documents

Publication Publication Date Title
JPH0363824B2 (en)
JPH0261539B2 (en)
JPH04162756A (en) Semiconductor module
JPS62287649A (en) Semiconductor device
JPH03211860A (en) Semiconductor package
JPS60241239A (en) Semiconductor device
JPH03218031A (en) Semiconductor integrated circuit device and preform bonding material used in the same
JP3419642B2 (en) Power module
JPS6315430A (en) Manufacture of semiconductor device
JPH08222670A (en) Package for mounting semiconductor devices
JPS6381956A (en) Package for semiconductor device
JP2761995B2 (en) High heat dissipation integrated circuit package
JP3222348B2 (en) Manufacturing method of ceramic package
JPS5835956A (en) Hybrid integrated circuit device
JPH0321092B2 (en)
JPS61256746A (en) semiconductor equipment
JPS58103144A (en) Semiconductor device
JPH0763080B2 (en) Semiconductor package structure
JPS5952853A (en) Semiconductor device
JPH0794623A (en) Circuit board
JPH0515439U (en) Semiconductor device
JPS60241240A (en) Semiconductor device
JPS63179734A (en) Good thermal conductive substrate
JPS61150251A (en) semiconductor equipment
JPH04116960A (en) Semiconductor circuit device