JPS60240140A - Semiconductor device - Google Patents

Abstract

PURPOSE:To connect chips and chips without passing a package, by outputting input signals, which are applied to the chip through a pad, and making that inputted signals to be inputted to the other chips. CONSTITUTION:Input terminals 2 are provided at one outer edge part of a chip 1. Output terminals 3 are provided at the outer edge part on the other side. The terminals 2 and 3 are connected by wiring materials 8. The terminals are also connected to the circuits, which are integrated at the central part of the chip 1 at the same time. For example, address signals are supplied to the address signal input terminals 2 of the chip 1 at the center from an upper chip 13. At the same time, the signals are sent to the address signal output terminals 3 of the chip 1 through the wirings 8 in the chip. The signals are also sent to a lower chip 14. Memory data signals and power sources are also supplied to the central chip 1 from a left chip 15. They are also supplied to a right chip 16. By repeating this procedure, the signals and power sources can be supplied to the many chips. Therefore, the equivalently large-scale memory devices and the like can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] This invention relates to connection terminals for semiconductor devices with the outside.

[Prior art]

Transistors and integrated circuits produced on substrates such as silicon are already widely used as electronic circuit components. Although the chips themselves of these semiconductor devices can be made extremely small, they have conventionally had the disadvantage of requiring a large volume when mounted. Taking semiconductor memory @Kin (hereinafter abbreviated as semiconductor memory) as an example,
5-501195 "Configuration of Dynamic Random Access Memory", 64 shows an example of realizing a bit dynamic RAM, but when manufactured at the current technology level, the planar area of the chip is usually about 30 square millimeters. (Literature, Nikkei Electronics, September 29, 1980 issue, pages 78-94). The thickness of the chip is approximately 0.4 mm. However, the bit dynamic RAM in the 64 was usually attached to eight terminals on each side.

Since it is mounted in a so-called 16-bin in-line package, the package area is about 150 square millimeters, and the package quotient is about 4 millimeters. Therefore, by mounting a chip in a package, the planar area is five times larger and the height is ten times larger, which has been a major obstacle in increasing the density of electronic circuits. Furthermore, in general, it is often not possible to secure sufficient capacity with one semiconductor memory. Therefore, when a large-scale memory system is required, a large number of semiconductor memories such as the 64-bit dynamic RAM are used in the memory system, but at this time, the address selection (hereinafter abbreviated as address) signal is used. , data signals, and even power supply are applied to each element in parallel, so the number of elements other than semiconductor memory is extremely small. Many columns are often connected in parallel. Therefore, the above-mentioned disadvantage in terms of space due to mounting in a package has become extremely large. Furthermore, in a large-scale device, the number of parts increases, and the number of connection points using sockets and soldering also increases, which has the disadvantage that troubles such as poor workmanship are more likely to occur.

[Objective] In order to eliminate such drawbacks, the present invention enables chips to be connected without using a package.

〔overview〕

The present invention provides a circuit within a chip to perform the original functions of the chip, and at the same time provides an area for wiring, and connects a plurality of connection terminals (hereinafter referred to as pads) with the outside of the chip using the wiring. Accordingly, an input signal applied to a certain chip by tracing back to a certain pad is outputted from another pad and used as an input signal to the other chip.

〔Example〕

Hereinafter, the present invention will be described in detail based on Examples.

FIG. 1 shows an example of a semiconductor memory embodying the present invention.
It shows the external shape of a chip of a semiconductor memory device. 1 in the diagram
Reference numeral 1 denotes a circuit portion for this semiconductor memory device to perform its original function. In the figure, 2 is an address selection (hereinafter referred to as address) signal input terminal, 3 is an address signal output terminal, 4 is a power input terminal, 5 is a power input terminal, 6 is a storage data input terminal, and 7 is a storage data input terminal. The output terminal 8 is a wiring connecting each input terminal and the output terminal. In this example,
This storage device also has 9 input terminals and 10 output terminals that are not used. This terminal is used to pass signals to other devices. Note that in this embodiment, 2 and 3.
Since there is no electrical distinction between terminals 4, 5.6, 7.9, and 10, there is no problem even if the input/output relationship of each terminal is reversed. Note that 6 and 7 are input/output terminals, and the internal circuit is a so-called three stealth circuit. FIG. 2 shows a semiconductor memory device according to the present invention shown in FIG. 1 that has been implemented at a high density to achieve a large Me storage cost. The wiring indicated by 12 in the figure can be made by wire bonding using a conductive thin wire made of gold or aluminum, or by attaching a la-contact chip to a board on which wiring is drawn with a conductive thin film such as copper. The signal is supplied from the chip 13 above the so-called gear bonding to the address signal input terminal 2 of the chip 1 in the center. At the same time, the signal is also transmitted to the address signal output terminal 3 of the chip 1 through the wiring 8 within the chip, and is also supplied to the lower step 14. Similarly, for storage data signals and power supply, chip 1 on the left
5 is also supplied to the chip 1 in the center and also to the chip 16 on the right.

By repeating this process, it is possible to supply signals and power to a large number of chips by simply making a V connection between chips, making it possible to obtain a virtually large-scale storage device.

When configuring a large-scale storage device, there is a method of connecting multiple memory columns in parallel, adding the same address signal to all address signals, and selecting a memory column using a chip select signal. Fig. 4 shows the application of the present invention to the method of adding a chip select signal.In Fig. 6,
21, 22, 23, and 24 are separate chip select signal wirings, and when these signals are activated, the memory chip 20 connects the chip select input terminal 17 (
When No. 2J is added, the chip select wiring 19 is bent and the internal circuit is activated to operate. At the same time, this signal is output from the chip select output terminal 1, but at this time, by partially changing the arrangement with the unused output terminal 10, the chips in the four columns are each independently selected. Ru. In other words, the leftmost chip is layout #2.
The chip on the right is selected when the chip select signal 911i is activated, and the chip on the right side is selected on the wiring 26, the chip on the right side 911i is selected on the wiring 22, and the chip on the right is selected on the wiring 21. It is selected when its chip select signal is activated. In FIG. 4, the same operation as in FIG. 6 is achieved by partially changing the arrangement of the wiring connecting the chips. 5 and 6 show a method of generating a chip select signal within each chip. In FIG. Added to chip 29. When the signal applied by 55 is output from the leftmost chip, it is inverted by the logic inverting amplifier 27 and supplied to the rightmost chip. With such a connection, the selection signal line 34 is set to "1" and 65 is set to "1"! !
If it shows “1”, the leftmost chip is selected and 64
If is logic 1111+ and 65 is logic uO'', then the chip on the right is 64 is logic ``o'' and 55 is logic ``0''
Then, the chip on the right side, 34, is logic ``'0''
If 65 is logic "1", the rightmost chip is selected. This shows that a memory column can be selected by applying an upper address signal7. In FIG. 6, 36 is added as an inverted signal of the selection signal line 64, and 37 is added as an inverted signal of the selection signal @35. In this case, any one of the four chips can be selected as in FIG. It is possible to create a state in which no chips are selected, or it is possible to select two out of four chips by setting both 64 and 36 to logic "1".

Note that the embodiments of the present invention are not limited to the above examples, and the present invention can be applied even if there are a large number of wiring lines such as address signal lines and data signal lines.

Further, the arrangement of the signal lines and power supply of each box is arbitrary, and it is also arbitrary to mix different types of chips.

〔effect〕

As described above in the embodiments, according to the present invention, it is possible to line up and wire a large number of semiconductor chips at narrow intervals without mounting the semiconductor chips in a package. Therefore, the wasted area caused by mounting can be extremely reduced and high-density mounting is possible, resulting in the effect that the device can be made smaller. especially,
Using many chips of the same type, such as in large-scale storage devices7)
It is extremely effective in some cases. Furthermore, if the present invention is implemented, a number of chips can be housed in a package at the same time, which reduces the number of chips to be distributed outside the package, resulting in lower production costs and improved reliability. It also has the effect of

[Brief explanation of the drawing]

FIG. 1 shows one embodiment of the invention. FIG. 2 shows the layout and wiring method of the embodiment of the invention shown in FIG. FIGS. 3, 4, 5, and 6 illustrate four different methods for applying chip selection signals in accordance with embodiments of the present invention. 2...Address signal input terminal, 6...Address signal output terminal, 4...Power input terminal, 5...Power output terminal, 6...Stored data input terminal, 7...Stored data output Terminal, 8...Wiring connecting each input terminal and output terminal. Applicant: Suwa Seikosha Co., Ltd. Representative Patent Attorney Tsutomu Mogami

Claims (1)

[Claims] A semiconductor device equipped with a plurality of connection terminals on the outer edge of the chip and a circuit integrated in the center of the chip. [Input terminals are provided on one outer edge, output phase terminals are provided on the opposite outer edge, and the two terminals are connected using a four-conductor wiring material, and at the same time the above-mentioned A semiconductor device characterized in that it is also connected to a circuit integrated in its center.