JP2006156814A - Multi-chip package semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-chip package semiconductor device that does not increase the total number of external terminals and improves flexibility in selecting the capacities of multiple semiconductor device circuit chips. <P>SOLUTION: In an MCP semiconductor device, multiple semiconductor integrated circuit chips 201, 202 and 203 at least subject to control by the enable control signal are packaged into a single multi-chip package. A supply voltage conversion circuit for increasing or decreasing a single supply voltage from the outside to generate another supply voltage and a source voltage/address conversion chip 204 provided with a chip enable generation circuit for generating a chip enable control signal are mounted to supply the generated supply voltage and chip enable control signal to another semiconductor integrated circuit chip. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a multi-chip package (MCP) semiconductor device, and more particularly to an MCP semiconductor device in which a plurality of semiconductor chips using a plurality of types of power supply voltages are mounted on one MCP.

  Recently, there are an increasing number of systems (for example, portable electronic devices) that use a plurality of power supply type MCP semiconductor devices in which a plurality of semiconductor chips using a plurality of types of power supply voltages are mounted on one MCP.

  In such a system, conventionally, power supply components of a type corresponding to the type of required power supply voltage are prepared on the system side, and each power supply voltage generated on the system side is input from an external terminal of the MCP. Therefore, the conventional MCP semiconductor device using a plurality of power supplies has the following types of problems because the types and number of power supply voltage terminals required by each semiconductor chip are provided as external terminals.

  (1) The total number of MCP external terminals increases. Accordingly, the number of frames (lead terminals) on one package substrate on which a plurality of semiconductor chips are mounted in the MCP semiconductor device and the number of wirings are increased. For this reason, it may be difficult to design the wiring on the package substrate, or there may be a restriction that the width and interval of the wiring cannot be increased.

  (2) When there are many types of power supply voltages supplied to the MCP semiconductor device, the number of power supply components prepared on the system side increases.

  On the other hand, when a plurality of memory chips are mounted on one MCP semiconductor device, the total capacity of a specific type of memory required for one MCP semiconductor device, for example, Pseudo Static RAM (PSRAM), is integrated into one chip. If it can be configured, there is no problem if a set of control signal pins, address input pins, and data I / O pins necessary for controlling one chip are prepared as external terminals of the MCP semiconductor device. However, when developing an actual MCP semiconductor device, there are many cases where a necessary mounting capacity must be configured by a plurality of memory chips due to various circumstances.

  For example, if you want to install a total of 256Mbit PSRAM in an MCP semiconductor device, but the available PSRAM chip has a maximum capacity of 128Mbit, or you can get a 256Mbit PSRAM chip, but use one 256Mbit PSRAM chip In some cases, it is more cost-effective to configure using two 128Mbit PSRAM chips than to configure using two 128Mbit PSRAM chips. Or, for the convenience of the system, 192Mbit is required as PSRAM, and in terms of the market situation, it is advantageous in terms of cost to configure using one 128Mbit PSRAM chip and one 64Mbit PSRAM chip.

  On the other hand, in general, a chip enable control signal of a memory chip is input as one input signal per memory chip, and is used to control whether the chip is in a selected (enabled) state or a non-selected (disabled) state. used. Therefore, when the specific type of memory required for the MCP semiconductor device is configured using two or more memory chips of the same type as described above, the address input signal other than the chip enable control signal, the data I / O Signals and the like can be commonly connected to a plurality of chips. However, since the chip enable control signal needs to select and control a plurality of memory chips, the number of memory chips required is the same as the number of memory chips. The reason is that the chip enable control signal for controlling the selection of each memory chip is normally negative logic, and when the activation level “Low” is input, the chip is selected. This is because an upper address signal assigned to select a memory chip cannot be directly input as a chip enable control signal.

  However, on the system side, a chip for a memory device for controlling the address space of each memory chip, although there is a sufficient margin in the address signal corresponding to the total memory capacity in the MCP semiconductor device In many cases, the number of enable control signals is limited. That is, due to the market situation such as the price of the memory chip as described above, the address space per memory chip must be configured with a relatively small capacity. As a result, a chip enable control signal is supplied for each address space of a large number of memory chips that should not be divided if possible. In other words, the system side originally wants to treat the memory in the MCP semiconductor device as a single memory, but since a plurality of memory chips are used, a plurality of chip enable control signals with different address spaces are used. It is supposed to be used.

  Such a situation often becomes a particularly important problem because it is necessary to control various memory devices in a cellular phone system or the like equipped with many multimedia functions such as music, still images, and moving images. .

  FIG. 9 shows a first conventional example of an MCP semiconductor device. In this MCP semiconductor device, one MCP 100 is mounted with a total of two chips, one 128 Mbit PSRAM chip 101 and one 256 Mbit NAND Flash chip 102. Here, the I / O of the PSRAM chip 101 is 16 bits, VDD = 3.0V, VDDQ = 1.8V, and the I / O of the NAND Flash chip 102 is 16 bits (common with the PSRAM chip 101), VDD = 1.8V. is there.

  In this MCP semiconductor device, the 16-bit I / O terminal is commonly used by the PSRAM chip 101 and the NAND Flash chip 102, but all other terminals used in each chip are independently of the MCP. It is set as an external terminal. That is, a power supply terminal for VDD and a power supply terminal for VDDQ are used for the 128 Mbit PSRAM chip 101. As a result, the total number of external terminals of the MCP 100 is 58 terminals. The VDDQ is a power supply voltage for the data I / O terminal used when the data I / O circuit in the chip has a power supply voltage specification different from other circuits.

  FIG. 10 shows a second conventional example of an MCP semiconductor device. In this MCP semiconductor device, two 64 Mbit PSRAM chips 201 (total 128 Mbit) and one 256 Mbit NAND Flash chip 202 are mounted in one MCP 200. Here, the I / O of the PSRAM chip 201 is 16 bits, VDD = 3.0V, VDDQ = 1.8V, and the I / O of the NAND Flash chip 202 is 16 bits (common with the PSRAM chip 201), VDD = 1.8V. is there.

  Also in this MCP semiconductor device, as in FIG. 9, only the 16-bit I / O terminal is shared by two PSRAM chips 201 and one NAND Flash 202. Addresses and various control signals are commonly used for two 64-Mbit PSRAM chips 201, but only the chip enable signal / CE is a separate signal for each chip. As a result, one chip enable signal / CE terminal is added compared to the MCP semiconductor device of FIG. 9, but one address signal is reduced. Therefore, the total number of external terminals of the MCP 200 is 58 terminals as in the MCP semiconductor device of FIG.

  FIG. 11 shows a third conventional example of an MCP semiconductor device. In this MCP semiconductor device, a total of 5 chips of four 32 Mbit PSRAM chips 301 and one 256 Mbit NAND Flash chip 302 are mounted in one MCP 300. Here, the I / O of the PSRAM chip 301 is 16 bits, VDD = 3.0V, VDDQ = 1.8V, and the I / O of the NAND Flash chip 302 is 16 bits (common with the PSRAM chip 301), VDD = 1.8V. is there.

  Also in this MCP semiconductor device, the 16-bit I / O terminal is commonly used by the four PSRAM chips 301 and the one NAND Flash chip 302 as in the MCP semiconductor device of FIG. Addresses and various control signals are commonly used for the four PSRAM chips 301, but only the chip enable signal / CE is a separate signal for each chip. As a result, compared with the MCP semiconductor device of FIG. 9, three chip enable signals / CE terminals are added, but two address signals are reduced. Therefore, the total number of external terminals of the MCP 300 is 59 terminals, one more than that of the MCP semiconductor device of FIG.

  FIG. 12 shows a fourth conventional example of an MCP semiconductor device. In this MCP semiconductor device, a single 32 Mbit PSRAM chip 401, a 64 Mbit PSRAM chip 402 and a 256 Mbit NAND Flash chip 403 are mounted in a total of 3 chips in one MCP 400. . Here, in each PSRAM chip 401, 402, I / O is 16 bits, VDD = 3.0V, VDDQ = 1.8V, and I / O of NAND Flash chip 403 is 16 bits (common with PSRAM chips 401, 402). VDD = 1.8V.

  Also in this MCP semiconductor device, as in the MCP semiconductor device of FIG. 9, only the 16-bit I / O terminal is commonly used by two PSRAMs and one NAND flash. The address and various control signals are commonly used for the two PSRAM chips 401 and 402, but only the chip enable signal / CE is a different signal for each chip. As a result, as compared with the MCP semiconductor device of FIG. 9, one address pin is reduced and one / CE pin for PSRAM chip is increased. Therefore, the total number of external terminals of the MCP 400 is 58 terminals as in the MCP semiconductor device of FIG.

Patent Document 1 discloses that different voltage values are generated by a power supply circuit on one chip.
JP 2000-246541 A

  SUMMARY OF THE INVENTION The present invention has been made to solve the above-described conventional problems, and a multi-chip package semiconductor device capable of improving the degree of freedom in selecting the capacity of a plurality of semiconductor integrated circuit chips without increasing the number of external terminals as a whole. The purpose is to provide.

  A multichip package semiconductor device according to the present invention is a multichip package semiconductor device in which a plurality of semiconductor integrated circuit chips controlled by at least a chip enable control signal are mounted in one multichip package. A power supply / chip enable generation semiconductor integrated circuit chip including a power supply voltage conversion circuit for generating a new power supply voltage by stepping up or down the power supply voltage and a chip enable generation circuit for generating the chip enable control signal is mounted. The generated power supply voltage and chip enable control signal are supplied to another semiconductor integrated circuit chip.

  According to the present invention, it is possible to provide a multichip package semiconductor device capable of improving the degree of freedom in selecting the capacitance of a plurality of semiconductor integrated circuit chips without increasing the number of external terminals as a whole.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

<First Embodiment>
FIG. 1 is a block diagram schematically showing a first embodiment of the MCP semiconductor device of the present invention. This MCP semiconductor device is a power supply / chip enable generation semiconductor integrated circuit chip (hereinafter referred to as a power supply / chip enable generation function) having a power generation function and a chip enable generation function as compared with the conventional MCP semiconductor device described above with reference to FIG. The address conversion chip 203 is added and mounted, and the external input, external terminal, internal wiring, etc. of the MCP differ accordingly. The power / address conversion chip 203 includes a power supply voltage conversion circuit that generates a new power supply voltage by stepping up or down from one power supply voltage supplied from the outside, and a chip enable generation circuit that generates the chip enable control signal. .

  In other words, this MCP semiconductor device has a total of four chips of two 64Mbit PSRAM chips 201 (128Mbit in total), one 256Mbit NAND Flash chip 202, and power / address conversion chip 203 in one MCP 200a. Has been implemented. Here, the I / O of the PSRAM chip 201 is 16 bits, VDD = 3.0V, VDDQ = 1.8V, and the I / O of the NAND Flash chip 202 is 16 bits (common with the PSRAM chip 201), VDD = 1.8V. is there.

  In the MCP semiconductor device of FIG. 1, a 16-bit I / O terminal is used in common by two PSRAM chips 201 and one NAND Flash chip 202, and has a power supply voltage VDD (PS) of 3.0V. The terminal and the terminal of the ground potential GND (PS) are commonly used by the PSRAM chip 201 and the power / address conversion chip 203. In addition, address signals A0 to A21 (PS), chip select signal / CS (PS), output enable signal / OE (PS), and write enable signal / WE (PS) for two PSM chips 201 of 64 Mbit. Control signals such as upper byte designation signal / UB (PS) and lower byte designation signal / LB (PS) are commonly used, but chip enable signal / C (PS) is a separate signal for each chip. ing. Other external terminals individually used in the NAND Flash chip 202 include a chip enable signal / CE (N), a write enable signal / WE (N), and a read enable signal / RE (N).

  That is, in the MCP semiconductor device of FIG. 1, the power supply voltage VDD (PS) 3.0V supplied from the outside is the power supply voltage VDD (PS) 3.0V of the two PSRAM chips 201 and the power supply voltage of the power / address conversion chip 203. Input as VD (input) 3.0V. Then, the power supply voltage VDDQ (output) 1.8V generated by the power supply / address conversion chip 203 is replaced with the power supply voltage VDDQ (PS) 1.8V for I / O of the two PSRAM chips 201 and the power supply voltage VDD of the NAND Flash chip 202. (N) Supply directly as 1.8V. In this case, the pad for the power supply voltage VDDQ (PS) 1.8V on the two PSRAM chips 201 and the power supply voltage on the NAND Flash chip 203 from the pad for the power supply voltage VDDQ (output) 1.8V of the power supply / address conversion chip 203. Wired directly to the VDD (N) 1.8V pad by wire bonding (direct bonding between chips). An example of direct bonding between chips is shown in FIG. The VDDQ is a power supply voltage for the data I / O terminal used when the power supply voltage specification of the data I / O circuit in the chip is different from other circuits.

  Further, two chip enable signals / CE (PS) 1, / CE (PS) 2 for controlling the two PSRAM chips 201 required in the conventional MCP semiconductor device described above with reference to FIG. Instead, a chip enable signal / CE (PS) for performing PSM selection control of 128 Mbit as a whole is used as an input signal to the power supply / address conversion chip.

  Furthermore, in the conventional MCP semiconductor device described above with reference to FIG. 10, only 22 addresses A0 to A21 (PS) are required for 64 Mbit PSRAM, but two 64 Mbit PSRAM chips 201 are required. The highest address A22 is additionally input from the outside for a total of 128 Mbits of PSRAM, and used as an input signal to the power / address conversion chip 203.

  Then, the power / address conversion chip 203 generates chip enable signals / CEout9 and / CEout10 based on the input signals / CE (PS) and A22, and chip enable signals / CE (2 of the 64Mbit PSRAM chips 201, respectively. Supplied as PS). For this purpose, the power / address conversion chip 203 and the two PSRAM chips 201 are wired by direct inter-chip bonding.

  As a result, in the MCP semiconductor device of FIG. 1, the external terminals related to the address / chip enable are the chip enable signal / CE terminal as compared with the conventional MCP semiconductor device of FIG. 10 that does not use the power / address conversion chip 203. One address signal A22 terminal and one address signal A22 terminal are added (enclosed by thin solid lines in the figure), but the chip enable signal / CE (PS) 1 terminal and / CE (PS) 2 terminal are no longer required. The number is unchanged. In addition, the power supply-related external terminals include a total of two external terminals for the power supply voltage VDDQ (PS) 1.8V for the PSRAM chip 201 and an external terminal for the power supply voltage VDD (N) 1.8V for the NAND Flash chip 202. Reduction is possible (enclosed by a broken line in the figure). Therefore, the total number of external terminals of the MCP 200a is reduced by two compared to the MCP semiconductor device of FIG.

  The power / address conversion chip 203 generates the two chip enable signals / CE (PS) based on the input signals / CE (PS) and A22 using the conventional MCP semiconductor device shown in FIG. This was done in the system (outside of the MCP), and it seems as if the input signal / CE (PS), A22 was needed as an additional signal. However, in the sense that all the chip enable signals can be created in the chip mounted on the MCP, the number of parts can be reduced as a whole system.

  Next, the power generation function (power voltage conversion function) and the chip enable generation function of the power / address conversion chip 203 in FIG. 1 will be described in detail.

(1) Power generation function (power voltage conversion function)
It has the ability to generate a power supply voltage obtained by stepping down or boosting the input power supply voltage and supplying it to other chips. For example, 5V, 3V, 2.5V, 1.8V, or 1.3V power supply voltage is input, and 5V, 3V, 2.5V, 1.8V, or 1.3V power supply voltage is generated and output based on it. To do.

(2) Chip enable generation function Generates and outputs a signal / CEout for selectively controlling activation / deactivation of each chip based on a plurality of input address signals A0, A1, A2 and / CE signal . The input signals A0, A1, A2, / CE and the output signals / CEout1 to 14 can be selected from 5V, 3V, 2.5V, 1.8V and 1.3V depending on the voltage specifications of the chip used. Has the same function.

  FIG. 2 is a block diagram showing an example of the power / address conversion chip 203 in FIG. The power supply voltage conversion circuit 2031 has a function of raising or lowering one power supply voltage supplied from the outside to generate a new power supply voltage and supplying it to another chip. In this example, a power supply voltage of 5V, 3V, 2.5V, 1.8V, or 1.3V is input, and a power supply voltage of 5V, 3V, 2.5V, 1.8V, or 1.3V is generated based on the input. Output.

  The address / CE conversion circuit 2032 receives the address signal and the memory system control signal / CE, generates and outputs a plurality of chip enable control signals / CEout signals. Here, the memory system control signal / CE is a chip enable control signal for controlling activation / deactivation of the maximum capacity chip of a specific type of memory, and a plurality of chips are selected and controlled based on the timing. To generate a plurality of control signals / CEout signals.

  FIG. 3 is a circuit diagram showing a specific example of the address / CE conversion circuit 2032 in FIG. In the address / CE conversion circuit of this example, 14 bits of the chip enable control signal / CEout1 are inputted by inputting the 3-bit signals A0, A1, A2 of the upper address assigned for chip selection and the 1-bit / CE signal. A plurality of decoder circuits (NAND gate circuits) 2033 are provided so as to selectively generate and output .about. / CEout14.

  In this case, by decoding the 3-bit signals A0, A1, and A2 based on the timing of the 1-bit memory system control signal / CE, / CEout1 to / CEout8 for up to 8 memory chips are selectively used. It is possible to activate ("Low" level).

  Based on the timing of the 1-bit memory system control signal / CE, the / CEout9 to / CEout10 for two memory chips are selectively activated according to the logic level of the 1-bit signal A2 ("Low"). Level).

  In addition, by decoding 2-bit signals A1 and A2 based on the timing of 1-bit memory system control signal / CE, / CEout11 to / CEout14 for up to 4 memory chips are selectively activated ( "Low" level).

  In other words, when mounting chips of the same capacity, use / CEout9 to / CEout10 for up to 2 chips, use / CEout11 to / CEout14 for up to 4 chips, and use / CEout1 to / CEout8 for up to 8 chips. do it. Furthermore, when a plurality of chips having different capacities are mounted, any one of / CEout1 to / CEout14 may be used in combination.

  According to the MCP semiconductor device according to the first embodiment described above, a plurality of power supply voltages and a plurality of chip enable control signals required in the MCP are generated on the power / address conversion chip and supplied to the plurality of memory chips. be able to.

  At this time, with respect to the power supply system, a power supply of a certain voltage value is supplied from the outside, a power supply of another voltage value is generated on the power supply / address conversion chip, and this is supplied to other chips that need it. As a result, the types of power supply voltages supplied from the outside to the MCP can be reduced (the power supply voltage can be at least one).

  As for the chip enable control system, when a specific type of semiconductor memory is mounted on the MCP, one memory chip corresponding to the maximum capacity that can be mounted is assumed, and the number of address signals necessary for the memory chip is controlled. And an external terminal corresponding to the chip enable control signal may be provided. In addition, the capacity of a specific type of semiconductor memory that is actually mounted is less than the maximum capacity, and it is possible to configure a plurality of memory chips having a capacity smaller than the maximum capacity as the specific type of semiconductor memory that is actually mounted. This increases the degree of freedom in memory configuration. Further, it becomes unnecessary to prepare a chip enable control signal corresponding to the final number of memory chips mounted as an external input signal. Therefore, since the number of chip enable control signals input to the MCP can be reduced, the total number of input signals to the MCP can be reduced.

  In addition, it is possible to reduce parts related to generation of a plurality of types of power supply voltages and generation of a plurality of chip enable control signals, which were conventionally performed outside the MCP. As a result, by reducing the number of external terminals and the number of external parts of the MCP, the cost and space of the entire system using the MCP semiconductor device of the present invention can be significantly reduced.

<Second Embodiment>
FIG. 4 is a block diagram schematically showing a second embodiment of the MCP semiconductor device of the present invention. Compared with the conventional MCP semiconductor device described above with reference to FIG. 11, this MCP semiconductor device is additionally provided with a power supply / address conversion chip 303. Accordingly, the MCP external input, external terminal, Internal wiring is different.

  In this MCP semiconductor device, a total of six chips including four 32-Mbit PSRAM chips 301, one 256-Mbit NAND Flash chip 302, and a power / address conversion chip 303 are mounted in one MCP 300a. Here, the I / O of the PSRAM chip 301 is 16 bits, VDD = 3.0V, VDDQ = 1.8V, and the I / O of the NAND Flash chip 302 is 16 bits (common with the PSRAM chip 301), VDD = 1.8V. is there.

  In this MCP semiconductor device, the 16-bit I / O terminal is commonly used by the four PSRAM chips 301 and the one NAND Flash chip 302 as in the MCP semiconductor device of FIG. For the four PSRAM chips 301, address signals A0 to A20 (PS), chip select signal / CS (PS), output enable signal / OE (PS), write enable signal / WE (PS), upper Control signals such as byte designation signal / UB (PS) and lower byte designation signal / LB (PS) are commonly used, but chip enable signal / C (PS) is a separate signal for each chip. . Other external terminals individually used in the NAND Flash chip include a chip enable signal / CE (N), a write enable signal / WE (N), and a read enable signal / RE (N).

  That is, in the MCP semiconductor device of FIG. 4, the power supply voltage VDD (PS) 3.0V supplied from the outside is the power supply voltage VDD (PS) 3.0V of the four PSRAM chips 301 and the power supply voltage of the power / address conversion chip 303. Input as VD (input) 3.0V. Then, the power supply voltage VDDQ (output) 1.8 V generated by the power supply / address conversion chip 303 is replaced with the power supply voltage VDDQ (PS) 1.8 V for I / O of the four PSRAM chips 301 and the power supply voltage VDD (for NAND Flash) N) Supplying directly as 1.8V. In this case, the pads for the power supply voltage VDDQ (PS) 1.8V on the four PSRAM chips 301 and the power supply voltage on the NAND Flash chip 302 from the pads for the power supply voltage VDDQ (output) 1.8V of the power supply / address conversion chip 303. It is wired to the pad for VDD (N) 1.8V by direct bonding between chips.

  Further, four chip enable signals / CE (PS) 1, / CE (PS) 2 for controlling the four PSRAM chips 301 required in the conventional MCP semiconductor device described above with reference to FIG. Instead of, / CE (PS) 3 and / CE (PS) 4, a chip enable signal / CE (PS) for controlling the selection of PSRAM for 128 Mbits as a whole is used to supply power to the power / address conversion chip 303. Input signal.

  Furthermore, in the conventional MCP semiconductor device described above with reference to FIG. 11, only 21 address signals A0 to A20 (PS) are required for 32 Mbit PSRAM, but four 32 Mbit PSRAMs are sufficient. Upper addresses A21 and A22 are additionally input from the outside for a certain 128 Mbit PSRAM and used as an input signal to the power supply / address conversion chip 303.

  The power supply / address conversion chip 303 generates chip enable signals / CEout11, / CEout12, / CEout13, and / CEout14 based on the input signals / CE (PS), A21, and A22, and each of the four 32Mbit PSRAM chips. 301 is supplied as a chip enable signal / CE (PS). The power supply / address conversion chip 303 and the four PSRAM chips 301 are wired by direct inter-chip bonding.

  As a result, in the MCP semiconductor device of FIG. 4, the address / chip enable-related external terminals of the address signals A21 and A22 are compared with those of the conventional MCP semiconductor device of FIG. 11 that does not use the power / address conversion chip 303. Two terminals and one chip enable signal / CE terminal (three in total) are added (enclosed by thin solid lines in the figure). However, the chip enable signals / CE (PS) 1, / CE (PS) 2, / CE (PS) 3, / CE (PS) 4 terminals can be reduced (enclosed by dotted lines in the figure), so the whole The number of terminals decreases by one.

  In addition, there are two external terminals related to the power supply: the external terminal for the power supply voltage VDDQ (PS) 1.8V for the PSRAM chip 301 and the external terminal for the power supply voltage VDD (N) 1.8V for the NAND Flash chip 302. Reduction is possible (enclosed by a broken line in the figure). Therefore, the total number of external terminals of the MCP is reduced by 3 compared with the MCP semiconductor device of FIG.

  The process of generating four chip enable signals / CE (PS) based on the input signals / CE (PS), A21, and A22 by the power / address conversion chip 303 described above is the MCP semiconductor shown in FIG. This is what was done in the system that uses the device (outside the MCP), and it seems as if the input signals / CE (PS), A21, and A22 were needed as additional signals. However, in the sense that all the chip enable signals can be created in the chip mounted on the MCP, the number of parts can be reduced as a whole system.

<Third Embodiment>
FIG. 5 is a block diagram schematically showing a third embodiment of the MCP semiconductor device of the present invention. Compared with the MCP semiconductor device of the conventional example described above with reference to FIG. 12, this MCP semiconductor device is additionally provided with a power / address conversion chip 404. Accordingly, the MCP external input, external terminal, Internal wiring is different.

  This MCP semiconductor device includes one 32 Mbit PSRAM chip 401, one 64 Mbit PSRAM chip 402, one 256 Mbit NAND Flash chip 403, and a power / address conversion chip 404 in one MCP 400a. A total of 4 chips are mounted. Here, in each PSRAM chip 401, 402, I / O is 16 bits, VDD = 3.0V, VDDQ = 1.8V, and I / O of NAND Flash chip 403 is 16 bits (common with PSRAM chips 401, 402). VDD = 1.8V.

  In this MCP semiconductor device, similar to the MCP semiconductor device of FIG. 12, the 16-bit I / O terminal is shared by the two PSRAMs 401 and 402 and the one NAND Flash chip 403. For two PSRAMs 401 and 402, address signals A0 to A21 (PS), chip select signal / CS (PS), output enable signal / OE (PS), write enable signal / WE (PS), upper byte designation Control signals such as signal / UB (PS) and lower byte designation signal / LB (PS) are commonly used. The chip enable signal / C (PS) is a different signal for each chip. Other external terminals individually used in the NAND Flash chip 403 include a chip enable signal / CE (N), a write enable signal / WE (N), a read enable signal / RE (N), and the like.

  That is, in the MCP semiconductor device of FIG. 5, the power supply voltage VDD (PS) 3.0V supplied from the outside is the power supply voltage VDD (PS) 3.0V of the two PSRAM chips 401 and 402 and the power supply of the power / address conversion chip. Input as voltage VD (input) 3.0V. Then, the power supply voltage VDDQ (output) 1.8 V generated by the power supply / address conversion chip 404 is used as the power supply voltage VDDQ (PS) 1.8 V for the two PSRAMs 401 and 402, and the power supply voltage for the NAND Flash chip 403. Directly supplied as VDD (N) 1.8V. In this case, the pad for the power supply voltage VDDQ (PS) 1.8V on the two PSRAM chips 401 and 402 and the pad for the NAND Flash chip 403 from the pad for the power supply voltage VDDQ (output) 1.8V of the power supply / address conversion chip 404. Wiring is made to the pad for power supply voltage VDD (N) 1.8V by direct bonding between chips.

  Further, two chip enable signals / CE (PS) 1, / CE (PS for controlling the two PSRAM chips 401, 402 required in the conventional MCP semiconductor device described above with reference to FIG. ) Instead of 2, the chip enable signal / CE (PS) for controlling the selection of PSM for 96 Mbits as a whole is used as an input signal to the power supply / address conversion chip.

  Furthermore, in the conventional MCP semiconductor device described above with reference to FIG. 12, 21 address signals A0 to A20 (PS) for 32 Mbit PSRAM chip 401 or A0 to A21 for 64 Mbit PSRAM chip 402 are used. Although only 22 (PS) are sufficient, the most significant address A22 is additionally input from the outside for the 32 Mbit PSRAM chip 401 or the 64 Mbit PSRAM chip 402 and used as an input signal to the power / address conversion chip 404.

  The power supply / address conversion chip 404 generates chip enable signals / CEout9 and / CEout10 based on the input signals / CE (PS) and A22, and the chip enable signals of the 32Mbit PSRAM chip 401 and the 64Mbit PSRAM chip 402, respectively. Supplied as / CE (PS). The power / address conversion chip 404 and the two PSRAM chips 401 and 402 are wired by direct inter-chip bonding.

  As a result, in the MCP semiconductor device of FIG. 5, the address / chip enable-related external terminal is the same as the terminal of the address signal A22, as compared with the conventional MCP semiconductor device of FIG. 12 that does not use the power / address conversion chip 404. One chip enable signal / CE terminal (two in total) is added (surrounded by a thin solid line in the figure) for chip enable signals / CE (PS) 1, / CE (PS) 2. Since the number of terminals can be reduced (enclosed by dotted lines in the figure), the total number of terminals is unchanged.

  In addition, the power supply-related external terminals are a total of 2 external terminals for the power supply voltage VDDQ (PS) 1.8V for the PSRAM chips 401 and 402 and external terminals for the power supply voltage VDD (N) 1.8V for the NAND Flash chip 403. The number can be reduced (enclosed by a broken line in the figure). Therefore, the total number of external terminals of the MCP is reduced by two as compared with the MCP semiconductor device of FIG. 12, to 57 terminals.

  The process of generating two chip enable signals / CE (PS) based on the input signal / CE (PS) and A22 by the power / address conversion chip 404 described above is the same as that of the conventional MCP semiconductor device of FIG. This is what was done in the system used (outside the MCP), and it seems as if the input signal / CE (PS), A22 was needed as an additional signal. However, in the sense that all the chip enable signals can be created in the chip mounted on the MCP, the number of parts can be reduced as a whole system.

  FIG. 6 is a perspective view schematically showing the inside of one implementation example of the MCP semiconductor device of FIG. The mounting substrate 61 has a wiring pattern (frame) 62 formed on the top surface, a wiring pattern formed on the back surface, the top surface frame 62 and the wiring pattern on the back surface are connected via through-hole wiring, and an external connection terminal ( For example, a ball grid array) is formed. A plurality of semiconductor chips are appropriately stacked on the mounting substrate through adhesives and spacers. In this example, chip 2 (64Mbit PSRAM chip in this example), chip 3 (32Mbit PSRAM chip in this example), and power / address conversion chip are stacked in this order on chip 1 (NAND Flash chip in this example). ing. Here, the chips 1 are usually mounted in order of chip size from the chip 1 having the largest chip size to the power / address conversion chip having the smallest chip size.

  A predetermined wire 67 of each chip 1, 2, 3 is connected to a predetermined frame 62 on the upper surface of the mounting substrate by a bonding wire 68. As described above, in a state where predetermined pads between chips are directly connected to each other by the bonding wires 68, the MCP semiconductor device having a small and thin stack structure as a whole is configured by sealing with, for example, a resin.

<Fourth Embodiment>
In each of the embodiments described above, an example in which only a memory chip is mounted in addition to a power supply / address conversion chip as a chip mounted on the MCP has been described. It is also possible to mount a chip.

<Fifth Embodiment>
In each of the above embodiments, the case where the power / address conversion chip is mounted on the MCP as a dedicated chip having only the power / address conversion function without having other functions has been described. There is no particular limitation to this, and it is also possible to mount the power supply / address conversion chip function on the memory chip or another chip having another function so that necessary connections can be made inside the MCP. It is. In this case, the number of chips, the cost, and the size of the MCP can be further reduced.

<Sixth Embodiment>
In each of the above embodiments, one power supply voltage generated by the power / address conversion chip is commonly supplied to a plurality of chips. However, the present invention is not limited to this, and a plurality of different power supply voltages generated by the power / address conversion chip are used. You may comprise so that it may supply separately to a some chip | tip.

<Seventh Embodiment>
In each of the above embodiments, the number and arrangement of the pads on the power / address conversion chip facilitate the wire bonding process for wiring between the pads on each chip in the MCP and the frame on the MCP wiring board. It is desirable to devise a degree of freedom to make it easier.

  FIG. 7 is a plan view showing an example of the number and arrangement of pads on the power / address conversion chip mounted on the MCP semiconductor device of the present invention. This power supply / address conversion chip 700 is provided with a plurality of sets of pads for output signals / CEout1 to / CEout14, and each set is arranged corresponding to a peripheral portion on the chip, for example, each side (four sides).

  When such a power supply / address conversion chip is mounted on and mounted on an MCP semiconductor device together with other chips, the arrangement side of the MCP power supply voltage input frame and the arrangement side of the power supply voltage input terminal on the power supply / address conversion chip The direction of the power / address conversion chip is determined so as to face each other. As a result, it is easy to bond and connect the power supply voltage input terminal of the power supply / address conversion chip and the MCP power supply voltage input frame with wires, and to each side (four sides) on the power supply / address conversion chip. It becomes easy to make wire bonding connection between any of the pads of the corresponding output signals / CEout1 to / CEout14 and the pad of the chip enable control signal / CE (PS) on another chip.

<Eighth Embodiment>
FIG. 8 is a block diagram schematically showing an eighth embodiment of the MCP semiconductor device of the present invention. Compared with the MCP semiconductor device of the conventional example described above with reference to FIG. 9, this MCP semiconductor device is additionally mounted with a power / address conversion chip 103. Accordingly, the MCP external input, external terminal, Internal wiring is different.

  In this MCP semiconductor device, a single 128 Mbit PSRAM chip 101, a single 256 Mbit NAND Flash chip 102, and a power / address conversion chip 103 are mounted in one MCP 100a. Here, the I / O of the PSRAM chip 101 is 16 bits, VDD = 3.0V, VDDQ = 1.8V, and the I / O of the NAND Flash chip 102 is 16 bits (common with the PSRAM chip 101), VDD = 1.8V. is there.

  In this MCP semiconductor device, the 16-bit I / O terminal is commonly used by one PSRAM chip 101 and one NAND Flash chip 102, as in the MCP semiconductor device of FIG. The external terminals individually used in the PSRAM chip 101 include address signals A0 to A22 (PS), chip select signal / CS (PS), output enable signal / OE (PS), write enable signal / WE (PS ), Upper byte designation signal / UB (PS), lower byte designation signal / LB (PS), and the like. As external terminals individually used in the NAND Flash chip 102, there are a chip enable signal / CE (N), a write enable signal / WE (N), a read enable signal / RE (N), and the like.

  That is, in the MCP semiconductor device of FIG. 8, the power supply voltage VDD (PS) 3.0V supplied from the outside is the power supply voltage VDD (PS) 3.0V of the PSRAM chip 101 and the power supply voltage VD (input) of the power / address conversion chip 103. ) Input as 3.0V. Then, the power supply voltage VDDQ (output) 1.8 V generated by the power supply / address conversion chip 103 is used as the I / O power supply voltage VDDQ (PS) 1.8 V for the PSRAM chip 101 and the power supply voltage VDD (N for the NAND Flash chip 102. ) Directly supplied as 1.8V. In this case, the pad for the power supply voltage VDDQ (PS) 1.8 V on the PSRAM chip 101 and the pad for the power supply voltage VDDQ (PS) 1.8 V on the PSRAM chip 101 and the power supply voltage VDD (N on the NAND Flash chip 102 of the power supply / address conversion chip 103 are used. ) It is wired to 1.8V pad by direct bonding between chips.

  In the MCP semiconductor device of FIG. 8, the power supply-related external terminal is the power supply voltage VDDQ (PS) 1.8 for the PSRAM chip 101, as compared with the conventional MCP semiconductor device of FIG. A total of two external terminals for V and an external terminal for the power supply voltage VDD (N) 1.8 V for the NAND Flash chip 102 can be reduced (enclosed by a broken line in the figure). Accordingly, the total number of external terminals of the MCP is reduced by two as compared with the MCP semiconductor device of FIG. 9 to 56 terminals.

1 is a block diagram schematically showing a first embodiment of an MCP semiconductor device of the present invention. FIG. 2 is a block diagram showing an example of a power / address conversion chip in FIG. 1. FIG. 3 is a circuit diagram showing a specific example of the / CE conversion circuit in FIG. 2. The block diagram which shows schematically 2nd Embodiment of the MCP semiconductor device of this invention. The block diagram which shows schematically 3rd Embodiment of the MCP semiconductor device of this invention. FIG. 6 is a perspective view schematically showing the inside of one mounting example of the MCP semiconductor device of FIG. 5. FIG. 2 is a plan view showing an example of the number and arrangement of pads on a power / address conversion chip in FIG. 1. The block diagram which shows 8th Embodiment of the MCP semiconductor device of this invention roughly. 1 is a block diagram schematically showing a first conventional example of an MCP semiconductor device. The block diagram which shows the 2nd prior art example of an MCP semiconductor device roughly. The block diagram which shows schematically the 3rd prior art example of an MCP semiconductor device. The block diagram which shows schematically the 4th prior art example of an MCP semiconductor device.

Explanation of symbols

200a ... MCP, 201 ... 64Mbit PSRAM chip, 202 ... 256Mbit NAND Flash chip, 203 ... power supply / address conversion chip.

Claims (3)

In a multichip package semiconductor device in which a plurality of semiconductor integrated circuit chips controlled by at least a chip enable control signal are mounted in one multichip package,
A power supply voltage conversion circuit that generates a new power supply voltage by stepping up or down one power supply voltage supplied from outside, and a chip enable generation circuit that generates a chip enable control signal corresponding to the plurality of semiconductor integrated circuit chips A multichip package semiconductor device comprising: a semiconductor integrated circuit chip for generating a power supply / chip enable included therein; and supplying the generated power supply voltage and chip enable control signal to another semiconductor integrated circuit chip.   2. The multi-chip package semiconductor device according to claim 1, wherein the power supply / chip enable generation semiconductor integrated circuit chip has a function of a semiconductor memory in addition to the power supply voltage conversion circuit and the chip enable generation circuit.   The power supply / chip enable generation semiconductor integrated circuit chip has a plurality of output pads for outputting the plurality of chip enable control signals generated based on one chip enable signal input and a plurality of address bit signal inputs. 3. The multi-chip package semiconductor device according to claim 1, wherein the plurality of output pads and the chip enable signal input pads of the plurality of semiconductor integrated circuit chips are wired by direct inter-chip bonding. .

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