JPS60217568A - Error correcting system - Google Patents

Abstract

PURPOSE:To improve the error correcting capability of random error and burst error by setting an error flag in a sequence having an error detected at a single error correction time and performing erasure correction. CONSTITUTION:In the first correction sequence in a double interleave system, for example, 10 words of the sum of 8 information words and two parities P2 and Q2 are defined as data, and the single error correction is performed with parities P1 and Q2. If an error word is detected in the first correction sequence, the error flag is added to the word; and when an error of two or more words is detected, error flags are added to individual words. In the second correction sequence, the number of error flags added in the first correction sequence is counted; and if the counted value is 2, parities P1 and Q1 are used to perform the error correction of two words by erasure correction. If the number of error flags is not 2, the single error correction is performed.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an error correction method for a storage system such as a magneto-optical disk or a floppy disk that records and reproduces data in one unit (hereinafter referred to as a sector), and in particular, an error correction method for a storage system such as a magneto-optical disk or a floppy disk. The present invention relates to an error correction method suitable for a recording system using an optical disk memory.

[Prior Art] Taking an optical disk memory as an example, an optical disk memory uses a photoreactive recording material to form a disk,
While the disk is being rotated, a laser beam is irradiated onto it with a narrow diameter of approximately 1 μm. By controlling the irradiation of laser light in accordance with the signal, it is possible to record and reproduce the signal at high density in the form of a plate, a hole, or a change in density on an optical disc. The track pitch during signal recording and reproduction is approximately 1.5 .mu.m11, and the pitch diameter is approximately 1 .mu.m11, which is very small. Therefore, random errors are likely to occur in the reproduced signal due to defects during disk formation, dust, etc. Furthermore, there is a high possibility that long burst errors will occur due to scratches made after recording.

As countermeasures against these errors, defects during disk formation can be inspected after the disk is formed and sectors with defects are not used, and data can be played back immediately after recording to detect errors. , the reliability of reproduced data can be increased by re-recording it in another sector.

However, the bit error rate of the disk itself is 10-4
Since the rate is as high as ~10-5, if sectors with even one bit of error are removed, the recording efficiency will decrease. Furthermore, even if there are no errors during recording, ii! After recording, dirt or dust may appear or be scratched, causing errors in the playback data.

Therefore, in order to increase the reliability of data, it is necessary to perform error correction.

The same applicant has proposed an error correction method that performs double interleaving as an error correction method that has a high correction ability for both burst errors and random errors. (See Japanese Patent Application No. 58-247431). This error correction method divides and arranges sectors of data to be recorded and reproduced sector by sector on a recording medium into frames each having an information word and two sets of parity.
And the first data is interleaved so that it is completed within the sector
A correction sequence is formed, and a set of parity is added to the first correction sequence, while a second correction sequence is interleaved in a direction different from that of the first correction sequence and completed within the sector. Random and burst errors occurring in data are corrected by forming a correction sequence and adding a set of parity to this second correction sequence.

This error correction method reduces the word error rate before correction to 10-4
Then, after correction, for example, about 1 for a random error
The word error rate can be reduced to about o-13.

However, since this error correction method performs single error correction on each of the first and second correction sequences, error correction is not performed when there is an error of 2 words or more in one sequence. I couldn't do it.

[Purpose] The present invention provides a storage system such as an optical disk, a magneto-optical disk, a floppy disk, etc., in which data is recorded and reproduced in sector units, by providing an error correction capability greater than that of an error correction code alone, and The purpose of the present invention is to provide an error correction method that has higher correction ability for both random errors and random errors.

[Configuration] In the first correction series (hereinafter referred to as 01 correction series), the present invention corrects a one-word error by single-error correction, and when an error of two words or more occurs, the error is If detection is possible, an error flag is added to each word of the C1 correction series, and erasure correction is performed in the second correction series (hereinafter referred to as the C2 correction series) based on this error flag. This improves the error correction ability for random errors and burst errors.

Embodiments of the present invention will be described below based on the drawings. First, the "double interleaving method" used in the present invention,
"Adjacent code" and "erasure correction" will be explained.

A. Double interleaving method The double interleaving method used in the present invention will be explained with reference to FIG. This double interleaving method is the same as that used in the aforementioned Japanese Patent Application No. 58-247431. The frames within a sector are arranged in a column direction, starting from the first frame, in a buffer memory, for example, as shown in FIG.

The figure shows up to the 127th frame.

Recording and reproduction of data on the disk is performed sequentially in the row direction starting from the first frame. 8 in each frame
Data is added to words (1-8), and two sets of parity (P2.Q2) and (Pt, (1+)) are added to the remaining four words.

First, during recording, data is arranged on a buffer memory in a direction intersecting the row direction as shown below. That is,
Starting from Wl of the first frame, words v1 to v8 are interleaved every 14th frame, and two words of parity P2 and 02 for this 02 correction sequence are added by interleaving to form a C2 correction sequence. Next, starting from Wl of the second frame, another word 1111-v8 is interleaved every 14th frame, and parity P2°Q2 is added to form a C2 correction sequence in the same way (not shown). Similarly, the 25th
A 02 correction sequence starting from Wl of 6 frames is formed. By the way, if the C2 correction sequence is formed in this way, the 256th frame will be exceeded in the middle of interleaving. At this time, as shown in FIG. 2, the interleaving is continued by returning to the first frame. In this way,
When a 02 correction sequence starting from Wl of the 256th frame is formed, the data part of each frame and the parity part of (P 2 , Q 2 ), except for the parity part of (218 bits 1), are used for any C2 correction. It is filled with series data and parity (P2.Q2).

In this state, 1 of the first frame in the direction intersecting with the row direction.
Starting from 111, in a direction different from the 02 correction series, 1
Information word for each 1st frame (W Ip W 2r, old...

w8) and parity (P 2 , Q 2 ) is formed. Note that the data constituting the 01 correction series consists of the eight words v1 to w8 of the already arranged C2 correction series and the parities P2 and o2. Parity P1 and Q+ are further added to this 01 correction series every 11 frames. Thereafter, as in the case of the C2 correction sequence, a C1 correction sequence starting from vl of the 256th frame is formed. When the 256th frame is reached in the middle of interleaving, as shown in FIG. 2, the interleaving is continued by returning to the first frame, as in the case of the C2 correction sequence. In this way, the 256th
When a C1 correction sequence starting from vl of a frame is formed, the data part and parity part of each frame are filled with data and parity of one of the C1 correction sequences.

Note that each correction sequence is interleaved once every frame.
4. As described later, the parity Q2 of the 02 correction sequence starting from vl of the first frame does not exceed the 256th frame, and is appropriately selected to a value that minimizes burst errors and random errors. However, it is not limited to the values shown in FIG. Furthermore, the interleaving distance between C1 and C2 may be C1>C2, contrary to what is illustrated. In this way, a double interleave that is completed within a sector can be constructed. therefore,
A format suitable for recording data in sectors can be obtained. This makes it possible to achieve extremely high correction capability for burst errors, as described below.

B, b-adjacent code 1
The 1b adjacent code is a code that can correct the adjacent error of one word (in this example, 8 bits 1~) in a code block using the parity of two words P and Q. The P and Q parities are generated using the following formula. be done.

l)=υN■suN-1■・・・・・・■v2■v1 ・
...(1)Q=TWN■T WN-+■・Song・■
Tll14w+ = (2) Here, ■ represents addition modulo 2 for each bit of the word. Further, T is a correction matrix, and when the primitive polynomial in GF(2) is b−s g(x)=x+Ad−s·x +−+At·x+1, it is expressed by the following equation.

Information words WNJN-sp..., ll+ and parity words P and Q are recorded on the disk, and during playback, the corresponding words 1', N, W' N -t, --,
Suppose that W' r , P' and Q' are obtained. Here, there is an error [ER in the information word Wk, and it is = -Wk■
If there is an error such as ER (error ER≠0), the Pa syndrome Sp and the 0 syndrome So are as shown in the following equations.

Next, when Sp is multiplied by T sequentially and compared with So, -1 T 5p=So (6) holds true when T is multiplied by -1 time, so there is an error in Wk. You can know what happened. The error pattern will then be equal to Sp.

Therefore, the error position WK of one word in the adjacent code can be determined by Equation (6), and the error of one word can be corrected by Equation (7) below.

Wk=W' k Sp (7) As described above, in the b-adjacent code, one error word in the correction sequence can always be corrected. However, if an error of two or more words occurs, the error may not be detected or a correction operation that makes correct data erroneous, that is, error correction, may occur, but in the following cases, the correction sequence It is possible to detect that an error has occurred within the system.

Sp≠0 (8) SQ≠0 (9) Next, erasure correction, which is the second part of the error correction method using b-adjacent codes, will be explained.

C. Erasure Correction Erasure correction can correct errors up to two words in a correction sequence if the position of the error word is known in advance. Now, the information word Wm, un's 2
It is known that an error has occurred in the word, and Em and En are the reproduced words W'm and W', respectively.
Suppose that there are n error patterns. At this time, the syndromes SP and SQ are each given by the following formulas.

5p=b■Frost...Song (11) SQ=T Ell■T, En ·Song (12) As a result, the error patterns of Vm and un can be determined by the following formulas.

En=Sp■" -song-(14) Therefore, 1 layer 1m=W' m■Ell ・------(15)
Wn=:W' n■En ・=-(16), so 2
Word errors can be corrected.

Furthermore, even if one of the two error words is in a parity word, or if both of the two error words are parity words, correction is possible using Sp and So, respectively.

Next, the error correction method of the present invention will be explained with reference to FIG.

The 01 correction sequence formed by the method described in the above section A (double interleaving method) is
l to lla information words and two parities P2 and Q
A total of 10 words of 2 are used as data, and correction is performed using Pr and 01 as parity.

With these parities P1 and Ql, as described in section B above, single-error correction can be performed using equation (7) to correct a one-word error. Similarly, for other 01 correction sequences, single-error correction is performed for errors in l words to correct them into correct words.

If an error of 2 or more words occurs, only error correction is possible, but as explained in section B above, (8) above.

The presence of an error word in this C1 correction series can be detected using equations (9) and (10). When an error word is detected in the CI correction sequence.

Construct a 01 correction sequence + -'l a yP 2
Add an error flag to each word of Io2. Similarly, when it is detected that an error of 2 or more words exists in another 01 correction sequence, V]~1g, P2 . Add an error flag to each word of Q2.

When each of the above-described processes is completed for each 01 correction sequence, error correction for the C2 correction sequence is next performed.

In the C2 correction series, - counts the number of error flags added in the 01 correction series. If the number of error flags is two, the parities Pi and Ql are used to correct two words of errors by the erasure correction described in section C above.

Furthermore, when the number of error flags is other than 2, single-error correction is performed in the same way as in the C1 correction series.

In this way, one word error is corrected by single-error correction for the 01 correction series, and up to two word errors are corrected for the C2 correction series. Due to the synergistic effect of the double interleaving and the above two error corrections, the ability to correct both random errors and burst errors can be improved as described below.

■ Random error correction ability Now, the word error rate is Pw, and the word error rate after correction is P.
wc, (8), (9), (10), where K is the error detection ability for random two-word errors, the corrected word error rate Pwc is given by the following equation.

Ric=K”XeCIX(t IC+)”XgCi
:ni+2C2XpH'+(1-♂)XaCIX(t
+C+)2XP-... (17) In the case of Figure 1, =0.80, so Pvc:i:3.71X1
0'XPw'+3.87X10''
It becomes 3.87X10-14.

On the other hand, in the case where the above-mentioned single-error correction is repeated in two stages, Pwc=(+tc+)"X act
It is w4. Here, if Pal = IX10', then Pwc: 1.09X10-13. That is, when using the error correction method of the present invention, the error rate is reduced to about 173 compared to the error correction method that repeats two stages of single-error correction.
can be lowered to

■ Burst error correction ability In the C1 correction series, each word is interleaved every 11th frame, so even if there are consecutive burst errors within the 11th frame, the error is a one-word error from the perspective of the interleaved series. Because it only appears as
All can be corrected by Pl, Q+parity.

For example, even if there are continuous burst errors in IJ+ in the 1st to 11th frames in the column direction, only one word Vl is erroneous in each C1 correction series starting from each w1 in the 1st to 11th frames. Since it only appears as an object, it is corrected by the PI and 01 parity of each C1 correction series. Therefore, all the burst ridges occurring in frames 11 of the 1st to 11th frames can be corrected. That is, if there are no errors in the preceding and succeeding 88 frames, they can all be corrected using Pl, Q+parity of the 01 correction series.

As already mentioned, in the error correction system of the present invention described above, the frame intervals of each data in each correction series of C1 and C2 are not limited to 11 and 14. However, cases where the distance between the two is equal are excluded.

For example, suppose the number of words in the CI correction series is 10 words, and 0
2 correction series may be made into 12 words. Conversely, the 01 correction series may be 12 words and the C2 correction series may be 10 words. The number of information words is not limited to 8 words, and if the parity code is an adjacent code,
The code is not limited to the b-adjacent code, and may be a Reed-Solomon code or the like.

Furthermore, the present invention is not limited to optical disk memories, but may also be applied to magneto-optical disks, floppy disks, etc. for storing data in 1. It can be used as an error correction method for storage systems that record and reproduce data in one unit. moreover,
It can be generally applied to digital devices requiring error correction.

The above description also applies to each embodiment described below.

FIG. 3 shows an embodiment of a specific device that implements the error correction method of the present invention for reproduced data.

In FIG. 3, reference numeral 11 denotes C! which stores playback data in an array as shown in FIG. 12 is a memory write address counter that generates an address for writing reproduced data into the 01 deinterleave memory 11; 13 is a memory read address counter that reads the C1 correction series from the Cl deinterleave memory 11; 1
4 is a C1 decoder that performs single-error correction on the C1 correction sequence; 15 is a C2 deinterleave memory that stores the C1 correction sequence that has been subjected to single-error correction; and 16 is Wt to Va, Pz of the C1 correction sequence.

Error flag memory 17 stores error flags corresponding to each word of C2, C2 deinterleave memory 15
A memory write address counter generates an address for writing the C1 correction series into the error flag memory 16 and an error flag corresponding to the 01 correction series in the error flag memory 16. 18 is a memory readout counter that reads the C2 correction series from the C2 deinterleaving memory 15 and the error flag memory 16. An address counter 19 is a C2 decoder that performs erasure correction on the 02 correction series, and 20 is an error 7 flag counter that counts the number of error flags of the 02 correction series read from the error flag memory 16.

Next, the operation shown in FIG. 3 will be explained.

Data reproduced from a recording medium such as an optical disk (not shown) is sequentially written from the first frame into the C1 deinterleave memory 11 in an arrangement as shown in FIG. 1 at the address given from the memory write address counter 12. When data writing is finished, the data is read out in the order of the 01 correction series using the address given from the memory read address counter 13, and the C1
input to the decoder 14.

The C1 decoder 14 generates the syndromes of equations (4) and (5) above, and depending on the value of the syndrome -,
If there is an error in one word in one correction series, the position of the word with the error is detected using equation (6), and correction is performed using equation (7).

Here, if there is an error of 2 or more words in the C1 correction series,
Furthermore, when an error is detected using equations (8), (9), and (10),
P2. The error flag corresponding to each word of Q2 is written into the error flag memory 16.

On the other hand, the error-corrected data output from the C1 decoder 14 is further processed by the memory write address counter 1.
The address value given from 7 is written into the C2 deinterleave memory 15.

In this manner, when the error correction processing for all 01 correction sequences of reproduced data stored in the CI deinterleaving memory 11 is completed, erasure correction is performed for the next 02 correction sequence.

The data stored in the C2 deinterleave memory 15 is
By memory read address counter 18.

The data are read out in the order of the 02 correction series shown in FIG. 1 and written to the C2 decoder 19. C2 decoder 19 generates syndromes Sp and SQ similarly to C1 decoder 14.

At the same time, the error flag counter 20 counts the number of error flags in this C2 correction series written in the error flag memory 16.

When the number of error flags is 2, C2 decoder 1
9 performs two-word error correction using the erasure correction described above. When the number of error flags is not equal to 2, a simple
Correct errors.

The above correction operations are controlled by a control processor (not shown). FIG. 4 is a flowchart showing the correction operations of the C1 correction series and C2 correction series described above. The contents are clear from the above explanation regarding FIG. 3, so a description thereof will be omitted.

In this embodiment, a case has been described in which the error correction of the C1 correction sequence is performed after writing to the CI deinterleave memory 11, and then the error correction of the C2 correction sequence is performed. When more than the number of frames for interleaving (122 frames or more in this embodiment) have been written, a correction operation for the CI correction sequence is performed, and this correction operation is performed for the number of frames equal to or more than the difference in interleaving between the 02 correction sequence and 01 correction sequence (this example). In the embodiment, the correction operation for the 02 correction series is performed after 28 frames or more, and by performing both correction operations alternately, the overall correction operation can be shortened.

The embodiment shown in FIG. 5 below performs such a correction operation using one deinterleave memory.

In FIG. 5, the memory write address counter 12
, memory read address counter 13, C1 decoder 14, error flag memory 16, and C2 decoder 19 are common to those in FIG. 21 is a deinterleave memory having the same configuration as the CI deinterleave memory 11 and C2 deinterleave memory 15 in FIG. A C1 decode address counter that generates an address to be read and written to the C1 decoder 14; 24 is a C2 decode address counter that reads the C2 correction series from the deinterleave memory 21 and generates an address to be written to the C2 decoder 19;
Reference numeral 25 denotes an output register for taking out error-corrected data from the deinterleave memory 21.

Next, the operation shown in FIG. 5 will be explained. Reproduction data inputted from a recording medium (not shown) is sequentially written into the deinterleaving memory 21 by the memory write address counter 12 via the input register 22, starting from the first frame, as shown in FIG.

After the reproduction data has been written for the number of interleaved frames of the CI correction series (122 frames or more in the case of FIG. 1), the C1 correction series is read out by the C1 decode address counter 23 and input to the 01 decoder 14.

The C1 decoder 14 generates the syndromes Sp and So using the above-mentioned equations (4) and (5), detects the position of the erroneous word in the same manner as in the embodiment shown in FIG. Look at the address and find the error pattern. Next, the data in the deinterleave memory 21 is read using this address.

One word error correction is performed according to the above equation (7), and the corrected data is written again to the original address of the deinterleave memory 21 by the 01 decode address counter 23. Further, the CI decoder 14 sets an error flag in a position corresponding to each word in the error flag memory 16 for a CI correction series in which an error has been detected.

The error correction processing for each 01 correction sequence is calculated by calculating the difference between the interleaving of the C2 correction sequence and the interleaving of the 01 correction sequence (
When more than 28 frames in the case of FIG. At this time, the error flag of the word corresponding to the 02 correction series is also read into the 02 decoder 19 from the error flag memory 16. C2 decoder 19
counts this error flag, and when the number is 2, performs the aforementioned erasure correction based on the error flag. If the number of error flags is a number other than 2, the C2 decoder 19 performs single-error correction in the same way as the C+ decoder 14. These error-corrected data are written again to the original address of the deinterleave memory 21 by the C2 decode address counter 24.

The error-corrected data that has been subjected to the error correction processing for the above 01 correction series and 02 correction series and is stored again in the deinterleaving memory 21 is transferred to the external device via the output register 25 according to the address of the memory read address counter 13. The data is sent to the device used.

In this way, writing of reproduced data to the deinterleave memory 21, error correction of the C1 correction series, error correction of the C2 correction series, and reading of the error-corrected data from the deinterleave memory 21 are performed in sequence. Become. Therefore, the entire error correction operation can be shortened.

Of course, one sector worth of data is stored in the digital leave memory 21.
After writing above, it is possible to perform error correction processing for all 01 correction sequences, then perform error correction processing for C2 correction sequences, and output data after completing error correction processing for all 02 correction sequences, Furthermore, it is also possible to realize error correction by combining these methods.

In each of the above embodiments, an error flag memory is provided in addition to each deinterleave memory. However, the number of bits per word of each deinterleave memory is increased by one, and this 1 bit is used as an error flag memory. It may also be used as

[Effects] As explained above, according to the present invention, error correction is performed using double interleaving that is completed within a sector, and errors are detected in single error correction and sequences with errors detected during single error correction. By setting a flag and performing erasure correction,
Error correction ability can be greatly improved. Also,
By interleaving that is completed within a sector, a format suitable for recording data in sector units can be obtained, and an extremely high correction ability can be obtained even for burst groups.

[Brief explanation of drawings]

1 and 2 are explanatory diagrams of the double interleaving method used in the present invention, FIG. 3 is an explanatory diagram of one embodiment of a device implementing the correction method of the present invention, and FIG. FIG. 5 is an explanatory diagram of another embodiment of the apparatus implementing the correction method of the present invention. 11...C+deinterleave memory, 12.17.
・・Memory write address counter, 13.18・
...Memory read address counter, 14...C1
Decoder, 15...C2 deinterleave memory, 16
...Error flag memory, 19...C2 decoder,
20...Error flag counter, 21...Deinterleave memory, 22...Input register, 23...C
I decode address counter, 24...C2 decode address counter, 25...output register. Figure 7: T! Direction a □ Fig. 4

Claims (1)

[Scope of Claims] In an error correction method for a system for recording and reproducing data on a recording medium using first and second correction sequences formed by interleaving in a direction intersecting frames, there is provided an error correction method for a system for recording and reproducing data on a recording medium, which When error correction is performed and an uncorrectable error is detected, an error flag is added to each word of the information word, and in the second correction series, the number of error flags in the first correction series in this series is added to callan 1. , an error correction method characterized in that erasure correction is performed when the value is a value that allows erasure correction, and normal error correction is performed in other cases. (2. In claim 1, a code having a single-error correction capability is used for parity, the first correction series performs single-error correction, and the second correction series uses a code that has the number of error flags. An error correction method characterized in that erasure correction using a flag is performed when is 2, and single error correction is performed when otherwise. An error correction method characterized in that the error correction method is completed by wrapping within a sector.