JPS60217444A - Control method for disk cache device - Google Patents

Abstract

PURPOSE:To attain high speed response by changing immediately a block into a block storing the data of an LRU control region and recovering the system if a fault takes place in the block storing the data of a bind control area. CONSTITUTION:A data of the bind control area not rewriting when it is stored in cache memories 400-700 and a data of the LRU control area performing rewrite exist in a data stored in a disc memory 200. Then the blocks storing the data of the bind control area and the LRU control area are sequenced in a prescribed criterion. If a fault takes place in the block storing the data of the bind control area, the block is disconnected from the ordering. Similarly, the required capacity of the block storing the data of the LRU control area is disconnected similarly from the relation according to a prescribed criterion. The data of the disconnected LRU area is ordered as the block storing newly the data of the bind control area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of controlling a disk cache device, and particularly to a method of controlling a disk cache device suitable for use in a system requiring high responsiveness.

[Background of the invention]

The disk cache device has the following two functions. The first function is to shorten the average response time for CPU access to disk memory while exchanging data between the CPU and disk memory.

Second, by specifying an area on the disk memory and controlling the data in that area so that it always exists in the cache memory, a high-speed response is guaranteed for access to the specified area. It is a function.

On the other hand, a disk cache device can be structurally separated into a control device and a cache memory, but the hardware required for the cache memory
In terms of megabytes, even if the currently available 64 kilobit memory is used, there will be only 500 pieces of data, and the reliability circuit I
As) If other peripheral circuits are included, approximately 100% of the IC will be required. That is, since a large number of ICs are used, reliability of the device becomes a problem.

Disk cache devices manage data in cache memory in units of blocks of a fixed size, but conventional disk cache devices prevent failures by not accessing blocks where a failure has been detected. I was dealing with it. However, with this method, the second function of the disk cache device mentioned above, that is, when data in a specific area of the disk memory is always retained, if a failure occurs in the storage area of the cache memory, a high-speed response is provided. It becomes impossible to guarantee.

In addition, if such a failure occurs, as a means of recovery,
It is conceivable to move the entire storage area on the cache memory, but in this case all the data to be held will be lost at once, resulting in a significant drop in performance. Further, depending on the relationship between the size of the storage area and the location (block number) of the failure, the movement itself may not be possible. Moreover, as mentioned above, disk cache devices require a large amount of I/O.
Since C is used, the probability of such a situation occurring is not low.

[Purpose of the invention]

The present invention was devised in view of the above-mentioned drawbacks of the prior art, and when a failure occurs in the area that always holds specific data on the cache memory, it is possible to immediately recover the area and provide high-speed response of the specific data. The purpose of this invention is to provide a method for controlling a disk cache device that ensures the following.

[Summary of the invention]

The method of controlling a disk cache device according to the present invention is as follows. That is, the data stored in the disk memory includes bind control area/codata that is not rewritten once it is stored in the cache memory, and data in the I4U control area that is rewritten. Cache memory stores data in units called blocks, but if a failure occurs in a block that stores data in the bind control area, the block that stores data in the LRU control area is immediately replaced with the block that stores data in the bind control area. It changes the blocks that store data, recovers the system, and enables high-speed response.

Specifically, blocks that store data in the bind control area are ordered in advance based on a certain standard, and blocks that store data in the L/U control area are similarly ordered based on a certain standard. If a failure occurs in a block that stores data in the bind control area, the block is separated in the above order. Similarly, the core capacity of the block that stores data in the L/U control area is separated from the above relationship according to a certain standard. Next, the separated LR
The block in which the data of the U control area is stored is ordered as a block in which the data of the bind control area is newly stored.

[Embodiments of the invention]

The present invention will be described in more detail below with reference to embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of a disk cache device that executes the method of the present invention.

In the figure, a CPU 1oo is connected to a disk memory 200 via a control device 300, and the control device 300 is connected to cache memories 400, 500, 600, and 700. CPUI 00 and control device 300 are connected by signal line 10 and control line 30, and disk memory 2
00 and the control device 300 are connected by a signal line 20 and a control line 40. The control device 300 and each cache memory 400 to 700 are connected to a control signal bus 50 and a data bus 6.
0 by an address bus 70.

Disk memory 200 has a storage capacity of 100 megabytes. In addition, each cache memory 400 to 700
consists of independent boards, each with a storage capacity of 1 megabyte.

FIG. 2(a) shows the storage area of the disk memory 200, FIG. 2(tb) shows the storage area of the cache memories 400 to 700, and FIG. There is.

In the cache memory device shown in FIG. 1, the cache memories 400 to 700 manage data in units called blocks. If one unit of this block is 8 kilobytes, a 4 megabyte cache consisting of the cache memories 400 to 700 There will be 512 blocks in memory. Therefore, there are actually 512 blocks in the cache memory shown in FIG. 2(b), and the pointer l-IJ shown in FIG. 2(c) corresponds to 512 blocks. 512 pieces of management information will be stored. However, Fig. 2 (1), (b),
As shown in tc), in this embodiment, for simplicity, the number of blocks in the cache memory is set to 8 blocks a to h, and the number of directories is also changed accordingly.
8 of 8.

As shown in FIG. 2(C), the directories 1 to 8 are composed of a part for storing the block numbers a to h of the blocks to be managed, and a pointer indicating the number of each directory 1 to 8, and are stored in the cache memory 400. ~700 corresponding blocks are managed.

As shown in FIG. 2(a), the storage area of the disk memory 200 includes a bind control area that cannot be rewritten once stored in the cache memories 400 to 700, and a bind control area that cannot be rewritten on the cache memories 400 to 700 even if the cache memory 400 to 700 goes bankrupt. There is an LRU control area to be used. cache memory 40
The data in the bind control area stored in 0 to 700 is managed by directories 1 to 3, and each directory 1 to 700 is
The pointer 3 indicates the address order in the disk memory 200 of the data stored in the cache memories 400 to 700 (the smaller address comes first). Data in the LRU control area stored in cache memories 400 to 700 is managed by directories 4 to 8, and one
(The directors 9.1 to 8 indicate the order in which data stored in the cache memories 400 to 700 are accessed. In other words, the pointers of directories 1 to 3 point to the managed cache memory 400. The address order of the data in ~700 on the disk memory 200 is the 11-discuss relationship between directories 1~3. The access order of directories 4 to 8 is shown in the order relationship of directories 4 to 8.

In this embodiment, for the sake of simplicity, it is assumed that pointers in directories 1 to 8 indicate an order relationship in only one direction. Directories 1 to 8 are composed of 2 words, and in the embodiment shown in FIG. 2(C), 2×8=16 words are required. However, in reality, as mentioned above, 512 blocks correspond to 512 blocks, so 2×512=1024 words are required. The directories 1 to 8 are provided in the control device 300 because high-speed operations are required.

When a data read command is output from the CPU 100 shown in FIG.
Data is transferred from the disk memory 200 to the CPU 700, and if the corresponding data does not exist, the data is transferred from the disk memory 200 to the CPU100, and the data is transferred from the cache memory 400 to 70.
Write this data in one block of 0. When newly writing data to the cache memories 400 to 700, it is desirable to write data in the LL (, U control area) to the oldest accessed block in the cache memories 400 to 700.

In this embodiment, this is achieved by associating the directories 4 to 8 with the pointers described above.

FIG. 3 is a diagram showing the structure of directories 1 to 8.

As shown in the figure, the directory consists of two words, one
The word number is a cache memory 400 to 70 in which data managed by the directory is written.
Flock numbers above 0 are written. In the second word,
In addition to the pointers (7th to 16th bits) indicating the order relationship among the till lefts 91 to 8 described above, there are a plurality of pits for writing information about each rice. The first bit DE of the second word is a pit indicating that the data managed by the directory is valid, and indicates that the data is valid when the pit DE is 1''.The second bit BB is A pit indicates that there is a failure in a block on the cache memory 400 to 700 in which data managed by the directory is written, and a pit BB of 1'' indicates that there is a failure. The fourth bit END is a pit indicating whether the data managed by the directory is data in the bind control area or data in the LRU control area, and the pit BND is 1''.
When it is 0'', it indicates that the data is in the bind control area, and when it is 0'', it indicates that it is data in the I4U control area.

FIGS. 4(a), (b), and (C) show the storage area of the disk memory 200, the storage area of the cache memories 400 to 700, and the contents of directories 4 to 8 when managing data in the LRU control area. It is a diagram. As shown in FIG. 4(a), data D, E, F, B, and C are stored in the disk memory 200, and these data are stored in the cache memories 400 to 400 as shown in FIG. 4(b). 7
Assume that the cache memory is stored in block d+e+f+go'' in block 00.Currently, cache memory 400 to 700
If data is accessed at j@ numbers of F, E, D, C, and B, the directory 5 is accessed as shown in Figure 4 (C).
The access order of data B to F is maintained by the series of pointer instructions (new) → 4 → 6 → 7 → 8 (old). The pointer LTOP indicating the most recently accessed directory number indicates 5, and the pointer LBO indicating the oldest accessed directory number.
8 is specified in TTOM.

A read command for any one of data C, D, E, and F is output from the CPU 100, and the data C, D, and E are read.
, F, and when the CPU 100 outputs a command to read data stored in the LRU control area other than data C, D, B, and F, it is necessary to rewrite the data on the cache memories 400 to 700. If this occurs, it is possible to express a new old-new relationship by writing pointers to directories 4 to 8.

It is assumed that there is no failure in each block d-hl/m from 400 to 700, and that all data B-F are valid.

Therefore, the pins DE in directories 4 to 8 shown in FIG.
is t 1pr, and pit BB is turned on. Further, since the directories 4 to 8 perform LRU control, BND shown in FIG. 3 is "0".

FIGS. 5(a), (b), and (C) show disk memory 2 when managing data stored in the Indian control area.
2 is a diagram showing the storage area of 00, the storage areas of cache memories 400 to 700, and the contents of directories 1 to 3. As mentioned above, the data y, z, and w in the bind control area on the disk memory 200 are stored in the cache memory 400.
~700 Once stored in block al bl C, it will not be replaced by any other data. Additionally, generally the memory capacity of the bind control area on the disk memory 200 is the same as that of the cache memories 400 to 70.
It is secured above 0. ) Indian control area data Y
, Z, and W are written in blocks a, b, and C of the -+mV-k quiche memories 400 to 00 shown in FIG. block a.

Directories 1 to 3 that manage data Y, Z, and W stored in b and c are the same as directories 4 to 8 of the LRU control area described above, but the bit BND shown in FIG. 3 is u III. (and the pointer each pointer points to) The meanings of IJ are different. That is, as described above, directories 4 to 8 manage data in the LRU control area.
In the above, the new and old access relationships were indicated, but the directories 1 to 3 that manage the bind control area are arranged in the order of addresses in the disk memory 200 of the data managed by each directory 1 to 3 (the smaller address comes first). )
shows. That is, as shown in FIG. 5(a), since the data in the bind control area is stored in the address order of Y, Z, and W, the directory for managing data Y is stored as shown in FIG. 5(c). The pointer 1 points to directory 2 that manages data Z 7 , the pointer of directory 2 points to directory 3 that manages data W, and the pointer of directory 3 points to directory 1 . Pointer BTOP indicates directory 1 that manages data Y stored at the smallest address, and pointer BB
A directory 3 that manages data W stored at the largest address is specified in OTOM.

As mentioned above, the storage capacity of the cache memory 400 is the same as the storage capacity of the bind control area of the disk memory 200.
~700, therefore, the cache memory 40
Data in blocks above 0-700 disk memory 20
It is possible to store in address order of 0. but,
Sequencing the data in the bind control area in this way is useful for recovery when a failure occurs in blocks a, b, c in the cache memories 400 to 700 that store data in the bind control area. It is an effective method.

FIG. 6 is a block diagram showing an example of a control device 300 that executes the disk cache device control method of the present invention. As shown in the figure, the control device 300 includes a microprocessor 310 that controls internal operations, a memory module 320 that holds directories and data necessary for control, a CPU interface 330, a processor interface 3401, a memory interface 350, and interfaces between each element. It is composed of two internal buses 360 and 370 for communication, an input bus 380 and an output bus 390.

FIGS. 7(a), (b), and (C) show the cache memory 4.
Disk memory 200 when performing recovery processing assuming that a failure has occurred in block b from 00 to 700
This is a diagram showing the operation contents of cache memories 400 to 700 and directories 1 to 8. Further, FIGS. 8(a) and 8(b) are flowcharts showing the operation contents of the recovery process.

In normal operating conditions, as described above, blocks a to h of cache memories 400 to 700 store data Y to F as shown in the figure, and data Y, Z, and W are data in the bind control area. Yes, data B, C, D, E
, F is data in the LRU control area.

Here, block b of cache memory 400 to 700
Suppose that a failure occurs and it becomes impossible to store data Z, the cache control device 300 operates as shown in FIG.
The operations are performed according to the flowcharts shown in a) and (b). That is, from steps S1 to 83, the directory that manages the oldest accessed block in the LRU control area is removed from the relationship by the pointer of directories 4 to 8, and the blocks managed by the removed directory are freed. Demonstrate operation. That is, in step S1, the contents of the pointer LBOTTOM are stored in the register SVDBTM.
write to. That is, FIG. 7(a).

In the examples shown in (b) and (C), the content of the pointer LBOTTOM is 8, so 8 is written to the register SVDBTM. Next, in step S2, register SVDBTM
It searches for pointers to directories 4 to 8 that have the same contents as , and stores the directory number in register LBOTTOM. Figure 7(a).

In the examples shown in (b) and (C), the content of register SVDBTM is 8, and the directory whose pointer content is 8 is directory 7, so the pointer LBOTTO
Add 7 to M. In step S3, a pointer L is set to the pointer of the directory searched in step S2.
Write the contents of 'I'OP.

In the example shown in FIGS. 7(a), (b), and (c), the contents 5 of the pointer LTOP are written to the pointer of the directory 7. As described above, it is completed that a block that has been accessed just once more recently than the oldest block is associated as the block that has been accessed the oldest.

From steps S4 to 814, the directory that manages the failed block among the blocks that manage data in the bind control area is separated from the relationship between directories 1 to 3, and further, in the processing from steps 81 to S3, Processing is performed to newly associate the freed block as a block that manages data in the bind control area. That is, in step S4, it is determined whether the block in which the failure has occurred is a block that stores data stored at the smallest address (address of disk memory 200) among the data in the bind control area. If YES, in step S5 the CPU
Set the TOP flag of 100 to "1". this is,
If the faulty block stores data stored at the smallest address in the bind control area, the faulty block is made unused and freed in steps 81 to S3. Since the block is used as a new block for storing the take of the bind control area, it is necessary to rewrite the contents of the pointer BTOP. This is a process that temporarily stores this information. In step S6, similarly, the block where the fault has occurred is
It is determined whether data stored in the largest address among the addresses of the bind control area (addresses of the disk memory 200) is stored. And YE
In the case of S, in step S7, the CPU 100's BOTT
Set "1#" to the OM flag. This process also applies if the faulty block is a block that stores data stored at the largest address among the addresses in the bind control area. In order to disable the block where the error occurred and use the block freed in steps 81 to S3 as a new block for storing the take of the bind control area, it is necessary to change the contents of the pointer BBOTTOM. This is the process of storing the information in detail.FIGS. 7(a) and (b).

In the example shown in (C), the faulty block is block b, which is neither the upper limit nor the lower limit of blocks that store takes in the bind control area, so the TOP flag and BO
The TTOM flag is never set to 1 "1".

In step S8, a directory whose contents of the pointer are equal to the directory number of the block where the failure has occurred is searched for, and the pointer of the corresponding directory is set in the register S.
Write the contents of VDBTM.

In the examples shown in FIGS. 7(a), (b), and (C), the number of the failed directory is 2, so directory 1
is selected and register SV is set to the pointer of directory 1.
Content 8 of DBTM is inserted. As a result, the failed block 2 is removed from the association of the directory that manages data in the bind control area, and step 8
The directory 8 that manages the block h freed in the processing of steps 1 to S3 is associated as the directory that manages the take of the bind control area.

In step S9, the content of the pointer of the directory that manages the failed block is changed to the pointer of the directory associated in step 8 as the directory that manages data in the bind control area (the directory indicated by the content of register SVDBTM). will be written to. Figure 7(a).

In the examples shown in (b) and (C), the faulty block b
The content 3 of the pointer of the directory 2 that manages the is written to the pointer of the associated directory 8.

Through this process, directory 8 that manages block h is completely associated in the order of directories 1→8→3.

In step 810, bit BND of the directory selected in step S8 is set to 11'', and bit DE is set to II Ojl.

In the example shown in FIGS. 7(a), (b), and (C), bit BND of directory 8 is set to 1'1" and bit DE is set to "0". As a result, directory 8 This means that the directory that manages data in the L⇠U control area has been changed to the directory that manages data in the bind control area.

In step Sll, the BOTTOM flag is set to “1”.
” is set, and if “1” is set, the pointer BBO is set in step 812.
Rewrite the contents of TOM with the contents of register SVDBTM. In step 813, the TOP flag is set to 11".
If 1'' is set, the contents of pointer BTOP are rewritten to the contents of register SVDBTM in step 814. FIGS. 7(a), (b), and (c) In the example shown in FIG. 1, neither the BTTOM flag nor the TOP flag is set to 1'', so the processes of steps 812 and 814 are not executed. Through the processing in steps 811 to 814, the number of the directory that manages the data stored at the smallest address (address of the disk memory 200) among the data in the bind control area is written to the pointer BTOP,
The number of the directory that manages the data stored at the largest address (address of the disk memory 200) will be written to BBOTTOM.

In this example, we have shown an example of using the block that was currently accessed the oldest as a replacement for a bad block.
It is arbitrary to select which block among the blocks to store data in the RU control area.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, if a failure occurs in the bind control area that always holds specific data on the cache memory, fc, the block in the bind control area where the failure occurs is replaced. By newly using a block of the LRU control area in which data is not rewritten as a new block of the bind control area, it is possible to immediately recover the data and ensure high-speed response of the data in the specific area.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a disk cache device that is the object of the present invention, FIG. 2(a) is a diagram showing the storage area of the disk memory shown in FIG. 1, and FIG. FIG. 2(C) is a diagram showing the storage area of the cache memory shown in FIG.
is a pointer in the control device shown in Fig. 1) A diagram showing IJ, Fig. 3 is a diagram showing details of the directory, and Fig. 4 (a)
Figure 1 shows the storage area of the disk memory, and Figure 4 shows the storage area of the disk memory.
Figure 5(b) is a diagram showing the storage area of the cache memory shown in Figure 1, Figure 4(C) is a diagram showing the directory in the control device shown in Figure 1, and Figure 5(a) is the diagram shown in Figure 1. 5(b) is a diagram showing the storage area of the disk memory shown in FIG. 1, FIG. 5(b) is a diagram showing the storage area of the cache memory shown in FIG.
) is a pointer in the control device shown in FIG. 1) A diagram showing IJ, FIG. 6 is a block diagram showing details of the control device shown in FIG. 1, and FIG. 7(a) is a disk memory shown in FIG. 1. 7(b) is a diagram showing the storage area of the cache memory shown in FIG. 1, and FIG. 7(C) is a diagram showing the pointer (IJ) in the control device shown in FIG. 1. , Figure 8 (
Figures a) and (b) are flowcharts showing the operation of an embodiment of the present invention. 100...CPU, 200...Disk memory, 3
00...Control device, 400-700...Cache memory, C, B, D, E, F, W, Y, Z...Data, a-h...Block, 1-8... directory. Agent Patent Attorney Masami Akimoto (σノmuj52 [≧] Dimatafu also figure 3 < (1) also figure 4 Tisfunaiswa tenuijintsuki figure 8 (a Tsuki figure 8 (b)

Claims (1)

[Claims] 1. In a disk cache device that stores data on a disk memory in the cache memory via a control device and enables high-speed response to a data read command from a CPU, The blocks that store data in the bind control area where data will not be rewritten are ordered based on a certain standard, and the blocks that store the data in the LRU control area where data is rewritten on the cache memory are ordered based on a certain standard, and the blocks that store data in the bind control area where data is not rewritten are ordered based on a certain standard. When a failure occurs in a block that stores the block 'k' in the LRU control area, the block in which the failure occurred is disconnected from the above relationship, and then the block 'k in the LRU control area is disconnected from the relationship according to certain criteria, and then the block is disconnected from the relationship. A method for controlling a disk cache device, comprising associating a block storing data in a separated LRU control area as a new block storing take in a bind control area. 2. Claim 1, wherein the certain standard for ordering the blocks that store data in the bind control area is the order of data atomicity on the disk memory.
A method for controlling a disk cache device described in Section 1. 3. The method of controlling a disk cache device according to claim 1, wherein the certain standard for ordering the blocks storing data in the LRU control area is the order of access by the take CPU. 4. Claim 1, characterized in that the certain criterion for separating the blocks of the LRU control area from the relationship is the data that was accessed the oldest by the CPU.
A method of controlling the disc character/tsuyu device described in section 1.