JPS60208792A - Image display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention has a graphic memory that stores an image pattern corresponding to a display screen, and generates a multi-level gradation graphic based on a readout signal from the graphic memory. The present invention relates to an image display device that displays patterns.

[Prior art]

In an image display device as described above, only one graphics memory is usually provided, and therefore only one bit of memory cell is allocated to each dot (or i!!il element) on the display screen. Not yet. Therefore, in this type of image display device, there is a problem when erasing a part of the displayed image pattern.

That is, as shown in FIG. 1 (al), after displaying line 2 intersecting line 1 on the display screen, line 1 or line 2
When erased, the intersection point 3 between line 1 and line 2 is also erased, as shown in Figure 1 (bl), resulting in the line being cut. The unnaturalness becomes noticeable when operating the screen interactively or when making a hard copy of the display screen.Therefore, even if line 2 is deleted as described above, line 1 remains as shown in Figure 1 tc>.
It is required that there is no chipping.

Therefore, a plurality of graph ink memories are provided, and the number of times the pattern is superimposed at each dot position is stored using memory cells of multiple bits corresponding to the same dot in each graph ink memory. An image display device has been devised that displays a graph ink pattern based on a signal obtained by ORing the readout output from each bit of a multi-bit register.

This image display device prevents the overlapping portion from being missing even if one side of the image patterns that overlap each other is erased, but it displays the image based on a signal obtained by ORing the readout output from the register. It has the following drawbacks:

That is, no problem occurs when one of the image patterns is erased, but when the overlapping area patterns of FIG. 2(a) are displayed, they are displayed as shown in FIG. 2(fbl). Therefore, a problem arises in that the superimposed state of the image pattern cannot be visually recognized.

[Purpose of the invention]

The object of the present invention has been made in view of the above-mentioned problems, and
The purpose of this is to prevent chipping of the overlapping part even if one of the overlapping patterns is erased in an image display device.
Moreover, the purpose is to make it possible to visually recognize how the patterns are superimposed.

[Structure of the invention]

In order to achieve the above object, the image display device of the present invention has the following features:
It consists of a plurality of graph ink memories, an up/down counter and a digital-to-analog converter connected to the graph ink memories, and each dot has a plurality of memory cells corresponding to the same position in the graph ink memory. A bit register is configured, and the up/down counter adds 1 to the contents of the register each time a pattern is written to the dot and subtracts 1 from the contents of the register each time the pattern is erased. Digital·
The present invention is characterized in that an analog converter converts the reading from each bit of the register into analog, and changes the brightness of the image pattern based on the output thereof.

〔Effect of the invention〕

According to the present invention, a plurality of graphic memories are provided, and the number of times the pattern is superimposed at each dot position is stored using a plurality of bits of memory cells corresponding to the same dot in each graphic memory, so that the number of times the pattern is superimposed at each dot position is stored. Even if one is deleted, no chipping will occur in the overlapping part. Furthermore, the readout output from each bit of the register of a number of bits configured for each dot by the memory cell is converted from digital to analog instead of performing an OR operation, and the brightness of the image pattern is changed by the output. , the superimposed state of the overlapping image patterns can be visually recognized. That is, since the output of analog conversion differs depending on the number of times of superimposition, the brightness of the overlapped portions differs depending on the state of superimposition, and as a result, the state of superimposition can be accurately recognized visually.

(Example) The present invention will be described in detail below using the drawings.

FIG. 3 schematically shows a part of an image display device according to an embodiment of the present invention. The apparatus shown in the figure is provided with two graphic memories 4a and 4b, each of which stores image information of each dot on the display screen in 2 bits. The device shown in the figure also includes a 2-bit up/down counter 5, an OR++-6, 7, a digital-to-analog converter 8, and an Equipped with designated circuit 1°.

In the device shown in FIG. 3, each dot on the display screen has a 2-bit memory cell, so this 2-pin memory cell is considered to be a 2-pin register, and the memory cell of the graphic memory 4a is used as a lower bit, a graph. The memory cells of the ink memory 4b are considered to be upper bits. If nothing is displayed on the graphic display device, that is, nothing is written, it is "00", and it is incremented by 1 each time the dot is written, and by 1 each time it is erased. Subtract.

When writing an image signal in the apparatus shown in FIG. 3, first the X address signal and the Y address signal of the graph ink memories 4a and 4b corresponding to the dot position are sent to the X address designation circuit 1139 and the Y address designation circuit, respectively. Apply from 10.

As a result, a 2-bit read signal RO-R1 corresponding to the dot is obtained from each addressed graph ink memory 4a, 4b. These read signals Ro −
Rt is applied to the data output Do (lower bit) and Di (41st bit) of the amplifier down counter 5, and set in the respective bits of the amplifier down counter 5. For example, if the bit has already been written once, (DI, Do)=(0, l). Next, in order to count up the amplifier down counter 5 by 1, the switching signal UD is set to "1" and a clock signal is applied to CLK. As a result, the counter 5 is automatically assigned, for example, the above example (Dl,
Do ) = (0, l), the upper bit output Q1 of the counter 5 is "1" and the lower bit output Qo is "0".
becomes. Note that when the switching signal LID is "1", a count amplifier is performed, and when it is "0", a countdown is performed. The respective outputs Qo and Qz of the counter 5 are connected to an OR gate 6.
．． 7 respectively to the graph ink memory 4a.

4b is written to the dot where the reading was performed. In this manner, the contents of the 2-pin register constituted by each memory cell of each graphic memory 4a, 4b are incremented by 1 each time one recess write is performed. Note that when the same door 1 is overwritten four times, the amplifier down counter 5 overflows and the carry signal CR becomes 1, so that rlJ is sent to each graph ink memory 4a, 4b via the OR gate 6.7. is written.

The image signals written in this way are sequentially addressed according to a predetermined sequence, read out, and displayed, and the analog video signal sA for display is the signal Ro read out from each graph ink memory 4a, 4b. ,
An analog version of Rz using a DA converter is used. The video signal S^ is applied to the cathode of a cathode ray tube (CRT), not shown, through a video drive circuit, not shown, to determine the brightness of each corresponding dot (or pixel) on the screen. Therefore, the brightness of the nI portion changes depending on the value of the register corresponding to the dot, so that the superimposition situation can be visually recognized on the display screen.

When erasing the written image signal, the UD is set to rOJ, contrary to the count-up, and the count-down is performed in the same way as in the up-call I. Therefore, in the overlapping part, since writing has been performed at least twice, the contents of the register are "10" or more, so even if one pattern is erased, the information in the intersection part will be "00". There isn't. Since the image is not displayed only when the contents of the register are "00", the display of the overlapping part will not be lost even if one pattern is erased.

Note that by having two graph ink memory sides, it is possible to process triple intersections, but if you use three graphic memory planes, you can process seven folds, and if you use four planes, you can process 15 folds. It is.

Further, although the above description has been made regarding a monochrome case, it is clear that the present invention can also be applied to a color case. For example, by duplicating the graphic memory for each of the three primary colors, even if one of the overwritten patterns is erased, the overlapping part will not be lost.
Alternatively, it is possible to prevent the color of the superimposed portion from being different from the original color.

[Brief explanation of the drawing]

Figure 1 shows an example of a pattern in which lines intersect with each other.
Schematic diagrams illustrating an example in which one of the above patterns is erased in an image display device having only one graphic memory, and an example in which one of the above patterns is erased in a conventional image display device having a plurality of graphic ink memories; A schematic diagram illustrating an example of an overlapping pattern in which figure numbers and areas intersect with each other, an example of displaying the pattern on a conventional image display device having a plurality of graph ink memories, and a third
The figure is a principle block circuit diagram showing an embodiment of an image display device according to the present invention. 1.2...Line, 3...Intersection, 4a, 4b...Graph ink memory, 5...Associate down count, 6.7...Or gate, 8...Digital/analog 91% Vessel, 9...X
Address designation circuit, 10...Y address designation circuit, RO% R1...Read signal, sA...Analog signal, CLK...
Clock signal, UD... switching signal.

Claims (1)

[Claims] In an image display device having a graphic memory for storing an image pattern corresponding to a display screen and displaying a multivalued graph ink pattern based on a read signal from the graph ink memory, a plurality of the graphic memories are provided. A plurality of memory cells corresponding to the same position in each graph ink memory constitute a plurality of bit registers for each dot, and each time a pattern is stored in the dot, one is added to the contents of the register. An amplifier down counter that subtracts one from the contents of the register each time a pattern is erased, and a digital-analog converter that converts the readout output from the register into an analog signal are provided, and the output from the digital-analog converter is provided. A double-image display device characterized in that the brightness of the image pattern is changed depending on the image pattern.