SU1439671A1 - Apparatus for displaying information on television indicator screen - Google Patents

Abstract

The invention relates to computing and can be used to display information from a computer. The purpose of the invention is to increase the speed of the device. The device contains a synchronization unit 1, a counter 2 addresses, the first 3, second 9 and third 13 switches, the first 4, second 5, three

Description

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ft and fourth 1I registers, a group of 7 OR elements, the first 8. and the second 12 code converters, the first 0 and second 15 RAM blocks, the address formers 14 and the video signal 16, the television indicator 17 with corresponding links. The device provides faster speed when modifying iK groups

The invention relates to computing and can be used to display information from a computer,.

The purpose of the invention is to increase the speed of the device.

Figure 1 shows the structure of the proposed device; Fig. 2 shows encoding formats for color characteristics of an image; FIG. 3 shows the distribution of color attribute fields in the first RAM block.

The device contains a synchronization unit 1, an address counter 2, the first switch, 3, the first register 4, the second register 5, the third register 6, a group of 7 OR elements, the first converter 8 codes, the second switch 9, the first RAM block 10, the fourth register P, the second converter 12 codes, the third switch 13, the address generator 14, the second RAM block 15, the video signal generator 16 and the television indicator 17,

The device works as follows

At synchronization unit 1, a mixture of damping and synchronizing pulses required for operation of a video signal generator 16 is outputted at the first output, and frame sync pulses are output at the second output. Horizontal sync pulses at the third output and clock sync pulses at the fourth output that set the sampling rate along the line of a TV scan,, along the X axis of the coordinate system of the displayed raster,

The counter 2 of the address, based on the inputs to the fuel, line symbols stored in the second memory block 15, for which the format code is entered in the second register 5, and the write mask code in the third register 6. selective recording of groups of luminance and color traits in the first 10 and second 15 blocks of operational capacity. 3 il.

At the first output, the address for the first memory block 10 (image) is generated at the first output, and the second output - the sync signal with the frequency of the address change, and the leading edge of the sync signal corresponds to the address switching.

Switch 3 switches the addresses. When the signal at the control input is zero, it switches information from the first input of switch 3, which is the first information input of the device, to the output, and from a single control signal, information from the second input of switch 3, all bits of the switched address, except for the three least significant bits of the Y coordinate, arrive bit by bit, starting with the highest one, respectively, at the second output of the switch.

Register 4 provides storage of the current value of the color code recorded in block 10 of the image memory. At a single value at the control input, the contents of register 4 are zeroed out. All eight outputs of the latter are single-digit, the first output corresponding to the most significant bit of the color code, and the eighth to the least significant bit.

Register 5 is stored for storing the value of the access format for block 10 of the image memory. With a single value on the control block, the contents of the register are reset to zero, which corresponds to the 0th format, in which the minimum number of pixels belonging to one

raster line, but with a maximum color code resolution (FIG. 2a). If the control input of the register is zero, in addition to the 0th format, values corresponding to the 1st format can also be written in it (Fig. 2b) , 2nd format (FIG. 2b) and 3rd format (FIG. 2d), specifying the ability to access, respectively, the military, quadrupled and eightfold increased number of picture elements. The increase in the number of image elements available for modification with a single reference to the block 10 of the image memory occurs at the same time due to an increase in the number of lines in the modifying fragment of the image with a corresponding reduction in the size of the recorded color code. The first output of register 5 is the least significant bit, and the second output is the most significant bit of the binary code corresponding to the value of the access format,

In register 6, the write mask is entered. With a single value at the control input, the contents of register 6 are reset to zero, which corresponds to the absence of masked bits, i.e., no signs that prohibit writing. The register size 6 is designed to store the recording mask for a fragment of the maximum area covered by a single treatment in format 3,

A group of 7 elements OR forms write signals for non-masked bits at a zero value of the signal at the first control input of the device. The total size of the outputs of the group of 7 elements OR is equal to the size of its first input.

The second code converter 8 is designed to convert the color code in accordance with the access format and the values of the three lower-order bits of the Y coordinate. The need for such a conversion is associated with the order of placing the image elements in the memory block 10. Fig. 3 shows a fragment of the image memory, repeated in the direction of the Y coordinate with a frequency of eight raster lines. When accessing in the 0th format, converting a color code is reduced only to rearranging its bits in accordance with

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the values of the least significant bits of the Y coordinate, which are fed to the second ones — control the current inputs of the first converter of 8 codes. In format 2, the next bit Y,, in format 3 is additionally masked by all three lower bits of Y, they are masked. Consequently, in format 3 on all information outputs of the first converter of 8 codes, there will be the value of the higher digit of the color code supplied to the first information input of the first transform of JFC 8 codes. Similarly, in the 2nd format, the information outputs of the first converter of 8 codes are four times duplicated bits of the color code, and in the 1st format, double duplication of the four higher bits of the color code. The signs of masking the bits of the Y coordinate are computed based on the values of the mpadade and the high bits of the format fed to the first control inputs of the first converter of the 8 codes.

The third switch 13 (recording signals) provides for the formation, in accordance with the values of the format of the recording signals, to the image memory unit 10. If we consider the recording mask as consisting of M lines of K bits in each, where M in this case is equal to eight, and K is determined by the number of image elements available for one volume of 20

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If you try to save memory to block 10 in the 0th format, then using the switch 13 of the recording signals, only the first line of the recording mask is used as the recording mask in the 0th format, in the 1st format - the first two lines, in the 2nd format - the first four lines, in the 3rd format - all eight lines of the recording mask, &

Memory block 10 is designed for. storing information relief describing the displayed image. A distinctive feature of storing information in it is its location (FIG. 3), which allows multi-format access (FIG. 2). The connection of the control inputs of the memory block 10 is determined by the placement of the higher bits of the color code involved in the recording 1st, 2nd and 3rd formats. Connection of lower address inputs of memory block 10, which are actually three low-order bits

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Y coordinates, but with different masking options (zero for the lower address inputs one through three and one for inputs four through six), to the first three address inputs of memory block 10 are also determined by the location of the highest color code bits, B 0 format, the second address inputs of the 10 unit of the unit receive the same identical address values; in the 1st, 2nd, and 3rd formats, the Y coordinates are different with lower-order bits,

The fourth register 11 receives information on the falling edge of the clock signal at the second control input and shifts it at the falling edge of the clock sync pulse at the first control input, which ensures the sequential output of the color code values for the individual picture elements to the second code converter 12.

The second code converter 12 is used for rearranging the color code bits read from the image memory block 10 so that the first bit of the output of the converter 12 is always the most significant bit of the code and the eighth one is the low bit, according to which the code bits are ordered colors and on the remaining bits of the output of the second converter 12 codes.

The second switch 9 at the zero value of the signal at the control input switches the output information from the first input, which is the address input of the device.

The address shaper 14 is designed to organize multi-format access to the second memory block 15 (chromaticity), which allows to speed up the formation of the required information relief in it. The address generator 14 makes it possible to uniquely assign a new value to the image element of a color recorded with a reduced code color color in all cells of the second memory block 15 of the chromaticity whose higher bits of the address match the recorded color code bits and which should be recorded the same color value. For example, to uniquely specify a color in the 3rd format, regardless of what values, and in what formats, assign

396716

These elements of the image previously, it is necessary that the 128 cells of the color memory block 15, having the same high-order bit address, contain the same information, which requires 128 calls to the color memory block 15. Writing the zero sign in the former 10 address and the required

the value of color per cell, whose address has zero values in the seven least significant bits, allows instead of 128 references to be limited to only one. Similarly, color values recorded in the 1st and 2nd formats are set.

The second memory block 15 serves to transcode color information.

20 and allows a substantial increase in the number of reproducible color shades. The number of cells in the memory block 15 and, accordingly, the maximum number of simultaneously reproduced color shades or semitones are determined by the chromaticity code depth. The maximum number of color shades available for visualization by the device is determined by the 30 cell width of the memory block 15.

Video signal generator 16 generates an analog video signal based on digital values input

35 of the memory block 15,

With a single signal at the second control input of the device, it is visualization of the contents of the image storage unit 40 10. The registers 4-6 are zeroed, the switches 3 and

9 commute to the output information, respectively, from the counter 2 addresses and the second converter 12 codes. For

45 complete erasing of block contents

In this mode, a zero signal must be supplied to the first control input of the device in this mode. The erase process is synchronized with the television.

5Q scan signal at the first control output device. The signal from the second control output of the device can be used to strob the signal on the first control signal.

gg the input of the device, which allows to combine the process of visualization of the contents of the memory block 10 with its erasure. The recording should be made at a zero signal value.

on the second control TP (eat device output.

To translate the device into a recurring record of a new image, a zero signal is supplied to the second control input of the device, which switches switches 3 and 9 to receive information from the device inputs. In register 4, the required color code value is entered, in register 5, the format value. In register 6, a recording mask is formed, and depending on the format, the entire register or only part of it is used. The required information value is fed to the first information input of the device, and then using the zero pulse supplied to the first control input of the device, the information is stored in the memory block 10.

The formation of the information relief in the memory unit 13 is also performed at a zero value of the signal at the second control input of the device. In this case, the required format value is entered into register 5, a code that is actually a color code is supplied to the device’s address input, and the corresponding color of the displayed color shade (or a semitone when displayed on a monochrome television indicator) is sent to the device’s fifth information input 30. ), after which a recording signal is supplied to the third control input of the device. After completing the formation of the information relief in memory blocks 10 and 15 on the second control

The code converter, the address driver, the video driver, the output of which is connected to the video input of the television indicator, the clock input of the video driver, is connected to the first output of the synchronization unit, the second output of which is connected to the reset input of the address counter, and is the output of the device or connection to the frame synchronization input of the television indicator, the input Codes of the device coordinates is the first informatrix input of the first switch, the second information input of which is connected En with the first output of the address counter, the first clock input of which is connected to the third output of the synchronization unit, the fourth output of which is connected to the second clock input of the address counter, the shift control input of the fourth register and the clock input of the address generator, the output of the address counter overflow is connected to the record control input the fourth register, the information input of the second register is an input device format, the input of which color code is the information input of the first register, the outputs of which connected to the information inputs of the first code converter, the outputs of the first group of which are connected to the control inputs of the third switch, whose information inputs are connected to the outputs of the block of OR elements, the first input of which is the recording control input

a unit entry is set to one device; an input is the mask code that allows the new image to be visualized.

Thus, in the proposed device, a significant increase in speed is achieved due to the possibility of modifying the color characteristics of groups of elements.

Claims (1)

Claims 50 45 A device for displaying information on a television indicator screen comprising a synchronization unit, an address counter, first, second and third switches, first, second, third and fourth registers, first and second blocks of RAM, a block of OR elements, first and second code converters , address driver, video driver, the output of which is connected to the video input of the television indicator, synchronizer input of the video driver, is connected to the first output of the synchronization unit, the second output of which is connected It is connected to the reset input of the address counter and is the output of the device or connection to the frame synchronization input of the television indicator. The input of the device coordinate codes is the first informatrix input of the first switch, the second information input of which is connected to the first output of the address counter. to the third output of the synchronization unit, the fourth output of which is connected to the second clock input of the address counter, the shift control input of the fourth register and the clock input f The address lamer, the address overflow output of the address is connected to the control input of the fourth register, the information input of the second register is an input. Device format whose color code is the information input of the first register whose outputs are connected to the information inputs of the first code converter. The outputs of the first group of which are connected with the control inputs of the third switch, the information inputs of which are connected to the outputs of the block of elements OR, the first input of which is the input m recording control is the third register information input, the outputs of the third switch are connected to the control inputs of the first memory block, the address input of which is connected to the first output of the first switch, the control input of which is connected to the control input of the second switch, inputs Setting zero of the first, second and the third register, and is the control input of the operating modes of the device, the address input of which is the information input of the second switch, the information input of the video signal generator la n By connecting the output of the second block of RAM memory, characterized in that in order to improve performance ustroyst va. the outputs of the second register are connected to the control inputs of the first group of the first code converter and to the first control inputs of the group of the address generator, the output of which is connected to the address input of the second RAM block, whose information input is connected to the input Color code of the device, the second control input the recording of which are the control inputs of the second memory unit and the address driver, the outputs of the group of the first switch are connected to the control inputs of the second group of the first converter ovatel codes and the control inputs of the second code converter, the output of the third register is connected to a second input of OR block elements, 439671 10 the outputs of the second group of the first code converter are connected to the address inputs of the first block of operational memory, the information inputs of which are connected to the outputs of the third group of the first code converter, the outputs of the first block of RAM are connected to information inputs 10 of the fourth register, the outputs of which are connected to the information inputs of the second converter, the outputs of which are connected to the information inputs of the group of the second switch, the outputs of which are connected to the information inputs of the address generator, the output of the address counter overflow is the output of the device for connection to the horizontal input synchronization of the television indicator. About format h / 2 Fi $, 2 L / Format 1 Mffftf 3 Junior Town Once / iodine color FIG. five ff 3 2 C, ft03Jt