JPS60198916A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor integrated circuit device constituted by MOSFETs (insulated gate field effect transistors). The present invention relates to techniques that are effective for use in semiconductor integrated circuit devices that form semiconductor integrated circuit devices.

[Background technology]

Conventionally, liquid crystal display devices with a dot matrix configuration have been
For example, "Electronic Materials 1 Magazine, October 1980 issue, page 1, 21
~ page 43, is publicly known.

In a display device using a liquid crystal display panel with a dot matrix configuration, pixel data is formed by a microprocessor and stored in RAM (random access memory).
The signal electrode is driven by writing data into the signal electrode and repeating the data at a constant cycle to straddle the data. In such a display operation, serial image data read from the RAM is shifted and converted into a parallel signal by a register, thereby forming a drive signal for each signal line f11 pole.

On the other hand, on the scanning electrode side, the scanning electrode selection operation is sequentially switched every serial/parallel conversion period by the shift register. For this reason, the semiconductor integrated circuit device for driving the signal rri pole and the semiconductor integrated circuit device for driving the scanning electrode are each constituted by separate semiconductor integrated circuit devices. The inventor of the present application has developed a semiconductor integrated circuit device for driving signal electrodes by adding an ability to directly supply the output of the shift register from the semiconductor integrated circuit device for driving signal electrodes to a driving circuit. It was discovered that it can also be used as an integrated circuit device.

That is, by writing logic "1" into the shift register at every one-screen display timing and shifting it at every serial/parallel conversion operation, the scanning electrode selection signal can be formed. In this case, it is conceivable to provide a gate circuit that bypasses the input of the flip-flop circuit to its output, but this poses a problem in that the circuit becomes complicated.

[Internality of the invention]

An object of the present invention is to provide a semiconductor 5WII circuit device equipped with a novel flip-flop circuit that has a function of holding an input signal according to a predetermined control signal and a function of outputting the input signal as it is in real time. .

The above-mentioned objects and novel features of this invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.

[1 Summary of the Invention] A brief summary of typical inventions disclosed in this application is as follows.

That is, the feedback loop is constituted by a clocked inverter circuit, and the first . By configuring the second latch circuit in a cascade configuration and selectively supplying a predetermined timing signal to the clocked inverter circuit according to the control signal, input capture in the first launch circuit and the second launch circuit is achieved. An information retention operation in which the operation and information retention operation are performed in a complementary manner, and a signal through operation in which the first and second latch i-paths are brought into a common ratio input acquisition state are selectively performed. .

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a 797917977 circuit used in a semiconductor integrated circuit device according to the present invention.

Each circuit in the figure is manufactured using the known MO3 collector circuit manufacturing technique iFt.
It is formed on a semiconductor substrate, such as single crystal silicon, although it is not specifically formed by the semiconductor substrate.

The input signal is supplied to the input terminal of the inverter circuit IVI via the clocked inverter circuit C11, that is, the input clocked inverter circuit CfV1 of the first latch circuit. The output signal of this inverter circuit IVI is fed back to the input side via a clocked inverter multicircuit CIV2 forming a positive feedback loop. This constitutes the first launch circuit. Similarly, long inverter circuit CIV3. CIV4 and inverter circuit I
A second latch circuit is configured by V2 and is connected in series to the first launch circuit.

The first of these. The above-mentioned locked-in hard circuit 1i18c+vt-CIV4 in the second latch circuit! : For example, the clock signal lJj is supplied by the following circuit. The clocked inverter circuit c IV 1 is supplied with the clock signal CL, and the positive feedback clocked inverter circuit CIV2 is supplied with the clock signal inverted by the inverter circuit IV3.

On the other hand, the output of the AND gate circuit G that receives the clock signal CL and the control signal C is inverted by the inverter circuit IV5 and supplied to the input clocked inverter circuit CIV3 of the launch circuit of WS2. Ru. Further, the clock signal supplied to the input clocked inverter circuit CIV3 is inverted by an inverter circuit IV4 and supplied to the positive feedback operation circuit CIV4 constituting the second latch circuit.

Next, the operation of the flip-flop circuit according to this embodiment will be explained according to the timing chart shown in FIG.

When the control signal C is at a high level (1!I logic "1"), the gate circuit G is opened, so when the clock signal CL becomes a high level, the manually operated clocked inverter circuit CIVI of the first latch circuit is in the operating state. , and supplies a high-level input signal to the input of the inverter circuit Vl. At this time, the clocked inverter circuit CI constituting the feedback loop
V2 becomes inactive and its output becomes a high impedance state, and the inverter circuit IVI forms a high-level output signal in accordance with the output signal of the input clocked inverter circuit CIVI (not shown).

On the other hand, since the clock signal supplied by the inverter circuit IV5 to the input clocked inverter circuit V3 of the second latch circuit becomes low level, this clocked inverter circuit CIV3 is in a non-operating state.

Furthermore, since the clocked inverter circuit CIV4 forming the feedback loop is activated by the inverter circuit IV5, it holds the previously captured signal (for example, the low level output signal Q).

Next, when the clock signal CL becomes low level, the input clocked inverter circuit CIVI in the first latch circuit becomes inactive, and the clocked inverter circuit CIV2 forming the feedback loop becomes active. The above-mentioned captured signal is held. On the other hand, in the second launch circuit, contrary to the first launch circuit, the manual clocked inverter circuit CIV3 is in the operating state, and the clocked inverter circuit CIV4 forming the feedback loop is in the non-operating state. , the above output signal Q
changes to high level according to the output signal (high level) of the first launch circuit.

Similarly, while the control signal C is at high level,
When the clock signal CL is at a high level, the first latch circuit takes in the input signal, and the second latch circuit holds the previously taken in information, and when the clock signal CL is at a low level. When it changes to
Conversely, the first launch circuit holds the captured information, and the second latch circuit captures it.

With this, the first. Since the second latch circuit performs the information holding operation, it functions as a flip-flop circuit.

Further, when the control signal C is set to a low level, the output signal of the gate circuit G is fixed at a low level regardless of the clock signal CL. In this state, when the clock No. 48 CL is fixed at a high level, both the input clocked inverter circuits CIVI and CIV3 of the first and second latch circuits become operational, and the clocked inverter circuits CIV2. Both CIV4 become inactive.

As a result, the input (No. 6) is directly sent as an output signal Q in real time through the clocked inverter circuit CIVI, the inverter circuit IV2, the clocked inverter circuit CIV3, and the inverter circuit IV2.

FIG. 3 shows a block diagram of an embodiment of a semiconductor integrated circuit device according to the present invention.

Each circuit block in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known method for manufacturing a semiconductor integrated circuit device.

Semiconductor collection in the same figure! I[! The circuit arrangement is for driving a scanning line electrode or a signal line electrode of a dot-structured liquid crystal display panel constituted by a scanning im'i trench and a signal line electrode. That is, this semiconductor integrated circuit device includes a shift register SR, a latch circuit FF using the flip-flop circuit shown in FIG. The driving circuit 1i'&DV forms a driving signal using multi-value pulses for AC driving the liquid crystal. Voltages v1 to v4 are power supply voltages for forming the multivalued pulse. Since the method of AC driving the liquid crystal in this manner is well known, detailed explanation thereof will be omitted.

When the semiconductor integrated circuit device of this embodiment is used as a signal line electrode driving device in the liquid crystal display panel, the control signal C of the latch circuit FF is set at a high level (i
T! ! Fix it to I (“l”).

In order to supply display data in parallel according to the scanning timing of the scanning electrodes, the 8 elements in one line of dot configuration are
It is serially supplied to the data input terminal of shift register SR in synchronization with shift clock signal φ. When this shift register SR takes in pixel data for one line, the latch circuit FF takes in the pixel data in parallel using the clock signal CL. While the corresponding pixel data is being captured, the captured pixel data continues to be supplied to the drive circuit DV.

By repeating this operation, pixel data is supplied in synchronization with the sequentially selected scanning line electrodes, thereby displaying an image by making the dots at the intersections of the scanning line electrodes and the signal line electrodes bright and dark. It is something.

On the other hand, when the semiconductor integrated circuit device of this embodiment is used as a scanning line electrode driving device in the liquid crystal display panel, the control signal C of the launch circuit FF is set to low level (logic "0"), and the clock signal CL is set to low level (logic "0"). at a high level (
Fixed to logic “1”). As a result, the latch circuit FF
performs the operation of supplying the input signal as is to the output terminal as described above, and the shift register SR
Logic "1" is supplied to the data input terminal Din at each display timing of one screen, and a signal similar to the clock signal CL supplied to the launch circuit FF when used as the signal line electrode driving device is supplied. shift clock signal φ
Supply as. As a result, at the first scanning timing, the logic "1" supplied to the shift register SR is
is supplied as is to the latch circuit FF, and the first scanning line electrode is placed in the selected state. Hereinafter, the shift register SR is set to logic "l" for each serial/parallel conversion of the signal line electrode.
are shifted one after another, so that the selection operation of the scanning 1fAN pole described above can be performed.

〔effect〕

11) The first . The second launch circuit is in a cascade configuration, and the first... By providing a function for bringing both the second launch circuit and the second launch circuit into an input receiving state, it is possible to obtain a flip-flop circuit having an information holding function and a signal through function.

(2) The above m-thread function uses the inverter circuit array that realizes the flip-flop function as it is, so the effect of simplifying and simplifying the circuit can be obtained. In particular, in the semiconductor integrated M1 circuit, the No. 48 path can be formed in one configuration, so the layout can be simplified.

(3) By connecting the flip-flop circuit to the liquid crystal display panel driving device, it is possible to selectively use the flip-flop circuit for the signal line driving device and the scanning line driving device.

(4) According to (3) above, the scope of application of semiconductor integrated circuit devices for driving liquid crystals is expanded, and as a result, mass production thereof can be achieved.゛The invention made by the present inventor has been described in detail based on examples, but this invention is not limited to the above examples, and can be modified in various ways without departing from the gist thereof. Needless to say, for example, in the embodiment circuit shown in FIG. 1, the inverter circuit IV4 may be omitted and the clock signal obtained from the output terminal of the gate circuit G may be supplied to the clocked inverter circuit CIV4. may also be
The control signal C causes the first. The logic circuit that complementarily performs the input signal fetching operation and the information holding operation in the launch circuit of ff12, or switches both latch circuits to the input signal fetching operation, can take various embodiments.

[Application field]

This invention provides a drive f for signal electrodes of a liquid crystal display panel.
In addition to liquid crystal display driving devices that form a li.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a flip-flop circuit used in a semiconductor integrated circuit device according to the present invention, FIG. 2 is a timing diagram for explaining its operation, and FIG. FIG. 2 is a block diagram showing an example in which the method is applied to a liquid crystal display driving device. DV...drive circuit, FF...launch circuit, SR...shift register, G...and gate circuit, CIVI-CI
V4...Clocked inverter circuit, IVI~IV5...
・Inverter circuit box 1 Figure 2 Figure 3

Claims (1)

[Scope of Claims] 1. The 1st. Second
of these launch circuits, the first of these. By arranging the second launch circuits in a cascade configuration and selectively supplying a predetermined timing signal to the clocked inverter circuit according to the control signal, the input take-in operation and performance in the first launch circuit and the second launch circuit can be controlled. an operation that causes the holding operation to be performed in a complementary manner; 1. A semiconductor integrated circuit device comprising a flip-flop circuit that can be switched to bring both a second launch circuit into an input receiving state. 2. The semiconductor integrated circuit device according to claim 1, wherein the flip-flop circuit receives a serial-parallel converted output of data formed by a shift register. 3. The semiconductor integrated circuit device according to claim 2, wherein the shift register and flip-flop circuit form a drive signal for a dot-structured LCD.