JPS60178566A - Access control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a plurality of central processing units, a channel control device, and the like. a) Regarding an access control method in a data processing system having a control device and a main storage device.

An access control method that enables synchronous access to a plurality of devices, especially those with different access control systems [Technical background] A conventional system configuration diagram is shown in FIG. In the figure.

CPIJO and CPIJI are central processing units, CHPO.

CHPI is a channel control device, MCUO, MC1J1 is a storage control device, MStJO, MSUI, MStJ2, M
StJ3 is a main storage device. In a conventional system configuration, controlling access to synchronously set data in a plurality of devices within the system is not very difficult. For example, C
When sending data from P tJ O to CHPO and CHP 1, the access is sent to the MC[J, for example, MC CHPO
, CHP 1 at the same time.However, as recent information processing devices are required to be smaller and faster, the space for cables between the devices is also becoming limited. For example, FIG. 2, which will be described later, is an example of a system configuration in which the number of cables is reduced. The symbols of each component in the figure are the same as those shown in FIG.

The basic operation of this system is to process the access to the access destination (10) to the control device to which the device is connected.

In this system. The following methods can be considered for controlling access to synchronously set data in multiple devices. In other words, when extending access to the 1a device and sending data to a device connected to the self-storage control device, it is only necessary to prioritize each of the two storage control devices and send data to each device. However, this control has the following drawbacks.

- In order to synchronize, it is necessary to take priority at the timing when priority can be taken by the self-memory control device, so the holding time of the register that holds access becomes longer, resulting in a decrease in performance.

(2) It uses a bus to send accesses to other storage control devices, and monopolizes registers that hold accesses from other storage control devices, leading to performance degradation.

[Object and structure of the invention]

An object of the present invention is to improve the above-mentioned drawbacks and provide a means for synchronously setting data in a plurality of devices without deteriorating performance.

Therefore, the present invention provides a plurality of mutually connected storage control devices, a plurality of central processing units, a channel control device 9, a main storage device, and a channel control device, each of which is connected to one of the plurality of storage control devices. Prepare.

and a data processing system in which data transfer between the central processing unit, the channel control device, and the main storage device is performed via the storage control device, and the above-mentioned 1.
a first pipeline controlling access to the q device;
A second pipeline for performing necessary control in the own device when accessing a main storage device connected to another storage control device, and at least one other of access from a device connected to the own device. determines the priority of access to the main storage connected to the storage controller.

A first priority determination circuit that sends the access to another storage control device, accesses from devices connected to the own device, and accesses sent from the first priority determination circuit of other storage control devices. At least determine the access priority of the main memory connected to the own device,
In a storage control device having a second priority determination circuit that sends the access to a first pipeline and a second pipeline of another storage control device, a central processing unit or a channel control device connected to the storage control device itself. The system is equipped with an identification circuit that identifies accesses that set data in synchronization with multiple devices in the system in step 7, and when the identification circuit recognizes the access, the access is automatically performed. This access control method is characterized in that priority is determined and processed only in the second priority determining circuit of the device.

Further, the storage control device is provided with an identification circuit that identifies data transfer access from the central processing unit to the channel control device, and when the corresponding access is recognized, the central processing unit that is the source of the access is connected. Record(,!
It is characterized in that only the second priority determination circuit of the Wil+ control device determines the priority order and processes it.

[Embodiments of the invention]

The details of the present invention will be explained below based on examples.

FIG. 2 will be described as an embodiment of the system of the present invention. Central processing unit CPtJO, CPUI, channel control unit C
HPO, CHP1. Storage control units MCUO, MCU1.
Main storage devices MSUO, MSU1, MSU2. Consists of MSU3. However, in this embodiment, CPU0. C.H.P.
O, MSUO.

M S tJ 1 are each connected to MCUO to constitute one access control system, and CPIJI, c11P
], MSIJ2. MStJ3 is each MC[J]
The two are connected to form another access control system. Furthermore, an interface is provided between M CLJ O and M CIJ 1 to transfer control information, addresses, data, and the like.

For example, cpuo self-system (7) MS IJ O, MS
When accessing any of IJI, MC
The IJO processes the access request and
1 and controls data transfer. However, CP[J
O is other system MSU2. When accessing any of MStJ3, MCUO further transfers the access request from CP[JO to MC[JI, and access control is performed via both 5M0UO and MCUI.

Figure 3 is a detailed configuration diagram of MCUO and MCtJl. In Figure 2, l is MC[Jo, 2 is MCIJl, 3 to 6 are control interface lines for transferring control information and addresses, etc., and 7 and 8 are data. This is an interface line for transfer. Further, in the MCUO, 103 to 106 are registers, 107 and 108 are access request self/other identification circuits, 109 is a self-MCU priority determination circuit, and 110 is an access request self/other identification circuit;
J 41 is a destination decision circuit, 111 is the own M CtJ pipeline, 112 is another MCU pipeline, and 113 is an execution control circuit.

114 to 120 are registers, and ]21 to 124 are selectors. Reference number 203 in MCU 1
The first digit of each element from 224 starts with II 2 II, but the reference number 103 in MC1, JO
Since these elements closely correspond to each of the elements 124 to 124, their explanations will be omitted.

The data bus for data transfer access from the CPU to the CHP is shared with the address bus for access to the MCU,
Register 1 (via 13, 203).

CP [No matter which M C1, the C HP connected to J is accessed from J, this CPU
Priority is taken in the MCU connected to the own device, and at the same time input to the pipeline that controls access to the MS [J connected to the own device, that is, the own MCU pipeline, other MCUs [J--also control code,
Address information is sent.

The access is to the local MC [CH connected to J)
If the access is to , the data is transferred under the control of the own M C1, J bits line, and the other M (', II
If the access is to a CHP connected to the CHP, other M in the MCII to which that CHP is connected (",
Data transfer is performed under the control of the IJ pipeline.

In M CIJ O, access request self-other identification circuit 1
07.108 are CP [, J O and CH
1] Identify whether the access request from 0 belongs to the own system (MCII O) or the other system (MCIJI), and issue the access request according to the jak-specific results.

Own M c IJ priority determination circuit 109 or other MCIJ
It is transferred to the priority determination circuit 110. Note that the access request self/other identification circuits 107 and 108 handle all system J, same) 1 access requests, and data transfer requests to the CHP as their own systems, and transfer them to the own M CIJ 4M destination determination circuit I09.

The own MC[J priority determination circuit 109 determines the own system's (: I)
[From J0, CHPO and other devices to the own CP
The priorities are determined for the access requests directed to tJo, CHPO, MSUO, and MSUI, and information on one selected access request is supplied to the own MCU pipeline 111 and the register 114.

Other MCI priority determination circuit 11O
The priority order is determined for access requests directed from the PO to devices of other systems, and the register 115° interface line 3. It is transferred to the own MCtJ priority determination circuit 209 of the MCUI via the register 205 of the MCUI.

The own MCU pipeline 111 and the I/MCU pipeline 112 control data transfer based on access requests. The own M CLJ pipeline 111 controls access to the own system device for the access selected by the own MCU O, and controls access to other MCU pipelines] 12
When access is selected by MCLJI of another system, register 214. Interface line 6. It receives the control information 11 via the register 106 and controls access to its own devices on behalf of its own MCU pipeline 111. In the latter case, other MCU priority determination circuit 210. Register 215, interface line 5. Register 105. Own M
Unlike the case where C[J priority determination concave NIII O9 is used, the execution timing of MCUO and MCI; .

The execution control circuit 113 controls own and other pipelines 11.
1,112.

Data read from M S LJ O or M S tJ 1 is transferred to CPU 0 or CHPO, or data is exchanged with MCIJI via interface line 7.8. Registers 117 to 120 and selectors 122 to 124 are in charge of these data transfers.

The register 114 is the own MCIJ priority selection time Pr 109
The control information, address, etc. of the access request selected by is transferred to the M S tl O and MSUI, and also transferred to the MCtJl via the interface line 4 and sent to other MCtJ pipelines 212 via the register 206 .
control.

The selector 121 and register 116 transfer data output from their own or other pipelines 111 and 112 to CHPO when accessing Cl1PO.

Although the above explanation has been made focusing on MCtJO for convenience, it can be applied to MCtJl in exactly the same way.

Next, circuit operation will be explained using a specific example.

(Example of operation in which IICPUO reads data from MSLJ2) MCIJO receives an access request from CP (JO) into the register 103.

■ The access request self-other identification circuit 107 determines that the received access request should be sent to MCtJl, and
The other MCU priority determination circuit 110 selects an access to be sent to CtJl, and the access is sent to MCUI. MC [
Jl accepts the access to register 205.

■ MCUI will process the received access request for 1MS LJ.
MSIJ2-\ is selected by the priority determination circuit 209 for selecting the access to be sent to the own MC [), and the access is sent to the own M
Input to CU pipeline 211.

■ MCIJO prepares for data transfer from MCUI according to the report from register 214 of MCIJI.
Access to other MC1 and J pipelines 112 is performed manually. M CtJ 1 transfers the data from MsU2 to its own MC.
It is received under the control of the information of the U pipe line 211.

(≦) MCUI transfers data from MStJ2 to its own M[]
l] M C[J
Send to O.

■ M CtJ O is other M CIJ pipeline 11
Data from MC[Jl is controlled by the information in 2.
Send to tJO.

(21CP (Example of operation in which IO transfers data to CHPO and CHPl for the same purpose) ■' Access from CP IJ O is register 1 ()
Set to 3.

■'-H The access is performed by the access request self-other identification circuit 10.
Based on the judgment made in step 7, the priority order is determined in the own MCIJ priority determining circuit 109 and inputted to the own MCU pipeline 111, and also sent from the register 114 to the MCUl, and inputted to the other MCtJ pipeline 212.

2' Data flowing to the pipeline of the address is sent to CHP O under the control of the own MCU pipeline 111.

■' CI (to P l, other M CtJ pipeline 2
12, the data flowing to the address pipeline is sent out.

With this control, data transfer access to the CL (PI) does not need to involve the other MCU priority determination circuit 110 and the own MCU priority determination circuit 209, and the MCLJO
, MC01, and the own MCtJ priority determination circuit 109 in MCCLJO.
Once the priorities are determined.

Other M C1, J pipelines in M CLJ l 212
The input is always guaranteed and therefore synchronized.

Note that the present invention is not limited to the embodiments described above, and can be implemented in a system having any number of central processing units, channel control units, control units described above, and main storage units.

〔Effect of the invention〕

As described above, according to the present invention, in a system in which there are multiple access control systems that determine priorities for access requests, in the case of peer access requests, the priority is determined only in one place. By enabling synchronous access, the efficiency of the 1-7° system J-U is increased.
I can do things.

4, and one song ffW 'f'4. Explanation: Fig. 1 is an overall configuration diagram of a conventional system, Fig. 2 is an overall configuration diagram of an embodiment of the system of the present invention, and Fig. 3 is an MCLIO,
It is a detailed configuration diagram of MC[JI.

In the figure, 1 is MCUo, 2 is MCtJl, and 3 to 8 are MC
interface lines between 0, 103 to 106 and 11
4 to 120 are registers, 107 and 108 are access request self/other identification circuits, 10!1 is a self-MC[J priority determination circuit, 110 is an other MCIj priority determination circuit, and 111 is a self-MCIj priority determination circuit.
CtJ pipeline, +12 is other MC [J pipeline, 113 is execution control time i? L121 to L124 indicate selectors.

Patent applicant Tomi±1t11 Co., Ltd. Representative patent attorney Fumihiro Hase (one other person) Figure 1 No. 212]

Claims (1)

[Claims] (1) A plurality of mutually connected control devices 1a. a plurality of central processing units, channel control devices, each connected to any one of the plurality of control devices;
A data processing system that is equipped with a main storage device, and in which data transfer between a central processing unit, a channel control device, and the main storage device is performed via a storage control device, and is connected to its own device. .9 A first pipeline that controls access to the device, and a second pipeline that performs necessary control on the own device when accessing the main storage device connected to other storage control devices. , at least other records 4 among the accesses from 'Zi& connected to the self-device.
a Determine the priority order of access to the main memory connected to the control device, and perform other steps 4. ? A first priority determination circuit that sends the access to the control device, access from a device connected to the device itself, and other notes 1. Determine the priority order of access to the device 1a connected to at least the device 1a above the access sent from the first priority determination circuit of the control device a, and 1.a Storage side with a second priority determination circuit that sends the access to a second pipeline of the controller? i
The +ll device is equipped with an identification circuit that identifies accesses from the central processing unit or channel control device connected to the device to synchronously set data for multiple devices in the system, and An access control system characterized in that when a corresponding access is recognized by an identification circuit, the access is processed with a priority of 111α in a second priority determination circuit of the own device. (2. In the access control system according to claim 1, the identification circuit includes an identification circuit for identifying data transfer access from the central processing unit to the channel control device, and when the corresponding access is recognized, An access control method characterized in that priority is determined and processed only in a second priority determination circuit of a storage control device to which a central processing unit that is an access source is connected.