JPS60176106A - Sequence controller - Google Patents

Abstract

PURPOSE:To utilize a capacity of a register twice, three times or over by storing once a storage data of the register to other memory set especially and putting other storage data again into the register. CONSTITUTION:To which area of a memory 4 set especially the data is to be stored is decided by block identification E. A data to be stored in a block 4a is written in addresses 5000-5377 of a register 1c, the block 4a is designated by a block designation byte and the data is stored in the memory 4a by using a memory address C. Then the data of the addresses 5000-5377 of the register 1c is rewritten and stored similarly in a block 4b. In taking out the data conversely, when a read command is given to the memory 4, a block identification signal, a memory address and a data are fed to a sequence controller main body. The data is stored again to the addresses 5000-5377 of the register by using the memory address as a pointer.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a sequence controller (programmable controller).

<Prior art> A sequence controller is equipped with an input card for accepting various inputs from the outside, and an input/output memory (input/output relay) that is connected via a bus to an output card for outputting data to the outside and transmits data. ing.

Further, the sequence controller has an internal battery-backed register in which the sequence program is stored. By the way, the registers are limited, have poor expandability, and are usually fixed.

<Object of the Invention> The present invention controls data transmission in the input/output memory based on the register of the sequence controller, thereby temporarily storing data stored in the register in another memory specially set. The purpose of the present invention is to double, triple, or more utilize the register by storing other stored data in the register again.

<Example> Hereinafter, the configuration of the present invention will be described with reference to the drawings.

FIG. 1 shows the system configuration of a sequence controller to which the present invention can be applied, where l represents the sequence controller main body and 2 represents an input/output card. and,
The sequence controller main body l has a user memory la
, an input/output memory 1b, and a register lc, and the input/output memo IJ1b is the card n of the input/output card 2. +nl
l''2 1nB, n4'+n5 or n6 is electrically connected to bus 3.

Now, in this embodiment, any card among the seven cards of the input/output card 2 has a register!
Install J (RAM or ROM).

The memory has a storage capacity that is at least an integral multiple of the storage capacity of the register IC of the sequence controller 1, that is, a number of bits that is an integral multiple of the storage capacity of the register IC of the sequence controller 1, and is capable of storing different stored data of the register lc of the sequence controller 1. can.

Specifically, let's explain this specific memory setting with reference to Figure 2.

In the figure, lc is a register of the main body of the sequence controller, and the addresses are 5000 to 5377. The register 1c stores first process data A, second process data B, and first process data N (only one of the process data is stored).

Further, in the figure, 4 is a specially set memory.

Note that this memory 4 is backed up by a built-in battery (not shown).

The input/output memory lb has, in addition to memory address C and memory data D, block identification E and write/read command F information. In this case, the memory 4 is divided into four parts, and it is necessary to decide in which area of the divided blocks 4a, 4b, 4c, and 4d the data will be stored, and in which area the data will be stored.
Exists for instructing data writing or reading.

In the figure, the solid line connecting the register lc (first process data A), the input/output memo IJ1b, and the memory 4 (block 4a) is a line for inputting the first process data A to the block 4a. In the figure, the broken line connecting the register lc (second process data B), the input/output memory 1b, and the memory 4 (block 4b) indicates that the second process data B is input to the block 4b. It's a line.

Note that the area in the memory 4 in which data is stored is determined by the block identification E. In this embodiment, if the block identification E contains "O○", the block 4a is stored with "O○".
If there is "l", it is stored in block 4b, if "02" is stored in block 4C, and if "03" is stored in block 4d.

In this way, first, addresses 5000 to 5 of register lc are
377, the data to be stored in the block 4a is written, the block 4a is designated by the block designation byte, and the data is stored in the memory I74 by the memory address C. next,
The data at addresses 5000 to 5377 of the register lc is rewritten and similarly stored in block 4b.

Conversely, when data is to be retrieved, a read command is given to the memory 4, and the block identification signal, memory address, and data are sent to the sequence controller main body. Using this memory address as a pointer, data is stored again in the registers at addresses 5000 to 5877.

FIG. 3 shows specific input/output signal assignments. In the same figure,
G is data point (Relayco, 100), H is data (Relayco, 101), ■ is data identification (Relayco, 1)
02) and H are write and read commands (Relayco, 108
).

Two examples of actual sequence controller programs are listed below. FIG. 4 is a write program, and FIG. 5 is a read program.

Effects> As described above, in the sequence controller of the present invention, since the number of registers in the main body is limited, there is no need to compensate for the lack of registers with a host computer data link, etc., and data backing can be performed at low cost. It can be used in various ways, which is advantageous for the recent production of a wide variety of products in small quantities. Of course, it can be easily operated without the hassle of storing data using a cassette or the like.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram of a sequence controller to which the present invention can be applied, FIG. 2 is a block diagram of a sequence controller according to an embodiment of the present invention, and FIG. 3 is a signal diagram of the sequence controller according to the embodiment of the present invention. 4 and 5 are ladder diagrams of sequence programs. Agent Patent Attorney Aihiko Fukushi (and 2 others) No. 1[2]
I Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Scope of Claims] 1. A sequence controller having an input/output memory and a register, comprising a storage means for storing a plurality of types of data stored in the register connected to the input/output memory, the register and the register being connected to the input/output memory. A sequence controller characterized in that data is transferred between storage means.