JPS6016731A - Pll circuit device - Google Patents

Abstract

PURPOSE:To quicken a lock speed by selecting a time constant of a low pass filter at the unlock state so as to be minimized for the lock time and changing over the said time constant at the lock state so as to minimize an FM noise. CONSTITUTION:When a PLL loop is in the unlock state, a discriminating circuit 6 detects the state and controls changeover switches 7, 8 so as to connect a low pass filter 4 between a phase comparator 1 and a VCO2. The low pass filter 4 consists of a lag/lead filter where the time constant is selected so as to attain the unity of the damping coefficient, and even if the FM noise is increased, the lockup time is decreased. When the PLL loop transits to the lock state, the discriminating circuit 6 detects it, the changeover switches 7, 8 connect a low pass filter 5 having a damping coefficient of nearly 0.3 so as to decrease the FM noise and improve the performance. Thus, the lockup time is reduced without deteriorating the performance.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PLL circuit device, and its purpose is to shorten lock amplifier time without degrading performance.

The general properties of PLL circuits are as follows:
trJ, damping coefficient η = 1.0 will be the fastest,
On the other hand, Flvl noise increases and P
The performance of LL deteriorates. On the other hand, F)7il of the PLL circuit
j sound is minimum when damping coefficient η-0,3, PLL
The performance is maximized, but the lock-up time becomes longer.

The present invention shortens the lockup time and
The purpose is to improve the characteristics of

FIG. 1 shows a block diagram of a general PLL circuit and a lag-lead type low-pass filter. In the figure, 1 is a phase comparator with a transfer function Kp, 2 is a VCO (voltage controlled oscillator) with a transfer relationship Kv, and 3 is a frequency divider with a frequency division ratio N.

The low-pass filter LPF is composed of resistors R1, R2 and a capacitor C.

Here, the time constant of the above low-pass filter LPF is PLL
The relationship with the damping coefficient η of the loop is as follows: % Formula % Figure 2 shows an embodiment of the present invention, where 1゜2.3 corresponds to the same sign in Figure 1 as χ J. ,ru. 4 is a low-pass filter consisting of a bleed filter whose time constant is selected so that η = 1, and 6 is a lagret filter whose time constant is selected so that η = 0.3.
It is a lock determination circuit with a low-pass filter and a 6-digit PLL loop, and outputs an output signal ``1'' in a locked state and outputs an output signal ``1'' in an unlocked state. 7 is a cut-off l switch controlled by the output signal of the lock determination circuit 6;

When the output signal of the lock determination circuit 6 is ゛°○pa, the output terminal of the phase comparator 1 is connected to the low-pass filter 4.

The output terminal of the phase comparator 1 is connected to the low-pass filter 6 when the output signal of the lock/ζ lock determination circuit 6 is 1'''.

8 is a changeover switch controlled by the output signal of the lock determination circuit 6, which connects the output terminal of the low-pass filter 4 to VCO2 when the position is 0°, and connects the output terminal of the low-pass filter 6 to the VCO2 when the position is 1°. Connect to VCO2.

Next, the operation of this embodiment will be explained. When the PLL loop is in the unlocked state, the determination circuit 6 detects this state, controls the changeover switch 7.8, and controls the phase comparator 1.
A low-pass filter 4 is connected between C02 and C02. Even if the FM noise increases, the damping coefficient is increased to shorten the lock-up time.

When the lock state is entered in this way, the judgment circuit 6
detects this and connects a low-pass filter 5 instead of the low-pass filter 4 to reduce FM noise and increase the performance of the PLL.1.As is clear from the above embodiment, the present invention allows the PLL loop to When in the unlocked state, select the time constant of the low-pass filter so that the locking time is the shortest] 7. When in the locked state, switch the time constant of the low-pass filter to the time constant that minimizes F, M @ sound,
Eliminating the drawbacks of the conventional technology, the locking speed is fast and the FM
It is designed to minimize noise. Therefore, this circuit is useful in devices that use this circuit, such as a Rinconvex wireless power supply device that uses PLL to perform AFC.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a general PLL circuit, and FIG. 2 is a block diagram of a PLL circuit device according to an embodiment of the present invention. 4.6... -Low pass filter, 6- Lock judgment circuit, 7,8...... Selector switch.

Claims (1)

[Claims] Two low-pass filters with different damping coefficients are provided between the phase comparator and the VCO (voltage-controlled variable frequency oscillator), and the above-mentioned low-pass filter is selected by determining whether the PLL loop is in an unlocked or locked state. A PLL circuit device provided with means for