JPS60163465A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable elements to be made fine without the decrease in source voltage by a method wherein the improvement in drain withstand voltage and hot carrier withstand voltage is realized by applying processes only of film adhesion, anisotropic etching, and one time ion implantation without the need of a new mask. CONSTITUTION:A gate oxide film 3 is formed on a P type Si substrate 1 having a channel implantation 2. Thereafter, an Si thin film 4 is deposited on the gate oxide film 3, and the high-concentration diffusion of phosphorus is carried out to the thin film 4. A photosensitive resin film 6 is applied thereon, and the part of gate conductor is formed by etching the laminated films 3 and 4. After removal of the resin film 6, the whole wafer is coated with an oxide film 18, which is then removed by being left only in the side wall of the gate conductor. Source and drain diffused layers are formed by phosphorus ion implantation and further arsenic ion implantation from above. At this time, an impurity region of lower concentration reaches immediately under the gate, but that of higher concentration is not immediately under the gate. Next, the whole wafer is covered with a protection film of phospho-silicate glass 5. Then, holes to form contacts are bored in the source and drain parts, and source and drain electrodes 7 are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to an MIS field effect transistor that is suitable for increasing the withstand voltage of an MIS field effect transistor and has excellent hot carrier resistance. .

[Background of the invention]

A conventional MIS field effect transistor is shown in Fig. 1(a).
However, as the gate length becomes shorter, M
When an IS type field effect transistor operates, the electric field at the drain end becomes extremely large, resulting in 1) source-train breakdown voltage, 2)
Hot carriers generated at the drain end and a drop in breakdown voltage due to a injection become a problem. In addition, in FIG. 1, 1 is a semiconductor substrate.

2 is channel implantation, 3 is gate film, 4 is
is a gate electrode, 5 is an insulating film, 7 is an electrode, and 9 is a source or drain region. As shown in FIG. 2, in a device with an effective channel length of 1 μm, the hot carrier breakdown voltage drops to about 4V, so it is necessary to increase this breakdown voltage. In Figure 2, 1
0 indicates drain breakdown voltage, 11 indicates hot carrier breakdown voltage,
For comparison, a drain breakdown voltage of 10' and a hot carrier breakdown voltage of 11' of an MIS type field effect transistor having a normal double diffusion layer, which is known as a high breakdown voltage structure.

Furthermore, the drain breakdown voltage 10' and the hot carrier breakdown voltage 11' of the MIS field effect transistor according to the present invention are also described. Furthermore, it is very difficult to form a MIS field effect transistor in the submicron region with a normal double drain structure because the diffusion layer wraps around directly under the gate.

[Purpose of the invention]

An object of the present invention is to provide a structure of a MIS type field effect transistor that has a high breakdown voltage even if the element size is small.

[Summary of the invention]

The present invention is based on the results of analysis to apply a conventional double drain structure to a MIS field effect transistor in the submicron region. FIG. 1(b) is a cross-sectional view of a transistor having a conventional double drain structure. . In FIG. 1(b), 1 is a p-type semiconductor substrate, 2 is a channel implantation, 3 is a gate oxide film, and 8 to 9 are gate electrodes 4.
This is an n-type impurity region formed using the mask as a mask. Here, 9 is a high impurity diffusion layer, and 8 is a low impurity moisture diffusion layer. A feature of the conventional double drain structure is that impurities of high and low concentration are diffused using the gate electrode 4 as a mask, so that both diffusion layers reach directly under the gate. FIG. 3 shows the analysis results of the electric field in the channel direction when a voltage of 5 V is applied to the drain, 5 V to the gate, and -3 V to the substrate.

These patterns are determined by device formation dimensions and impurity concentration.

Although it may change depending on the applied voltage, etc., the feature of the present invention is that the peak does not exist below the gate. 14 is a MIS type field effect transistor with a standard structure as shown in FIG. 1, 15 is a case having a conventional double drain structure, and 16 is a case according to the present invention. The internal electric field strength of the device is strongly correlated with the impurity distribution in the diffusion layer, and in the conventional double drain structure where this distribution is gently sloped,
The electric field becomes smaller. Furthermore, in the present invention, where the high concentration impurity region is not directly under the gate, the effective channel is increased, resulting in a smaller electric field than in the conventional double train structure. In addition, in the case of the present invention, the position where the maximum electric field is applied is shifted to the inside of the drain.
There is no gate electrode on this.

Therefore, there is no gate oxide film into which high-energy carriers generated by a high electric field should be injected. In other words, variations in transistor characteristics due to hot carrier phenomena are less likely to occur, and the hot carrier breakdown voltage is increased. Furthermore, since the high concentration impurity region is surrounded by the low concentration impurity region, the junction capacitance is also reduced.

[Embodiments of the invention]

The present invention will be explained in more detail below using examples.

Example 1 As shown in FIG. 4(a), a gate oxide film 3 of 20 nm in thickness is formed on a P-type Si substrate 1 of lOΩ·l having a channel implantation 2. After that, 300nm S
An r thin film 4 is deposited on the gate oxide film 3, and a high concentration of phosphorus is diffused into the silicon thin rIA4 by thermal diffusion using POCQ as a source.

A photosensitive resin film 6 is applied thereon, a pattern is formed by photolithography, and the laminated films 3 and 4 are etched by microwave plasma etching to form a gate conductor portion.

Next, as shown in FIG. 4(b), the photosensitive resin film 6 is removed, and the entire wafer is covered with a 250 nm thick oxide film 18.
This oxide film 18 was removed by anisotropic etching, leaving it only on the sidewalls of the gate conductor. At this time, an oxide film 18 with a width of about 0.25 μm remained on the sidewalls of the gate conductor. After that, from above, 60KeV, 6X1013cn-'
Phosphorus ions are implanted, followed by annealing at 1000° C. for 20 minutes, and then arsenic ions of 80 KeV, 5×10 15 cm −2 are implanted, and annealing is performed at 950° C. for 30 minutes to form source and drain diffusion layers. At this time, the depth of the diffusion layer was approximately 0.2 μin in the high concentration impurity region and approximately 0.3 μm in the low concentration impurity region. Therefore, the low concentration impurity region reaches just below the gate, but the high concentration impurity region is not directly under the gate, and the low concentration impurity region is oxidized onto the gate conductor sidewalls. If the diffusion layer is formed to surround the high concentration impurity region without leaving 18, the diffusion layer will wrap around directly under the gate, making it difficult to form a short channel MIS type field effect transistor. Form.

Next, as shown in FIG. 4(C), the entire wafer is covered with a protective film of phosphosilicate glass 5. Drill holes in this to make contacts to the source and drain parts.

Source and drain electrodes 7 were provided.

According to this embodiment, as shown in FIG. 2, both the drain breakdown voltage and the hot carrier breakdown voltage are improved.

1μ! Even a MIS type field effect transistor having an effective channel length of n or less can be used without lowering the power supply voltage.

Example 2 As shown in FIG. 5(, ), a gate oxide film 3 of 20 nm is grown on a P-type substrate 1 of 10Ω with a channel implant 2, and then a 300 nm Si thin film 4 is grown. is deposited, and a high concentration of phosphorus is diffused into the silicon thin film 4 by thermal diffusion using POcQ,l as a source.6 Then, 200 nm of 5isNa 2 is deposited thereon.
A pattern is formed by photolithography, and the laminated films 12, 4.3 are etched by reactive ion etching.

After Shikaru, from above Kono, 60 K e V v 6
Implant phosphorus ions at x 10 cm-' and
C, 20 minutes of annealing and further 80KeV, 5X1
01S (J-" arsenic ion implantation, 950'C, 3
Anneal for 0 minutes to form source and drain.

Next, as shown in FIG. 5(b), the Si thin film 4 was thinned by about 0.5 μm by isotropic etching.

After removing the Si, N4 film 12, a protective film and electrodes were formed as shown in FIG. 4(c).

In this example as well, the same structure as in Example 1 was obtained, and similar effects were obtained.

Example 3 As shown in FIG. 6, on a P-type Si substrate, as shown in FIG.
Form the gate conductor section as shown in FIG. Thereafter, an oxide layer 18 having a thickness of 300 nm is formed by selective oxidation to cover the gate conductor portion. Thereafter, a source and a drain were formed as in Example 1, and a protective film and electrodes were formed as shown in FIG. 4(C).

In this example, the same structure as in Example 1 was obtained, and similar effects were obtained.

Other Examples In the example shown in FIG. 7, the gate electrode material is tungsten.
7, and has a gate conductor on which a channeling prevention film 11, such as an St or N4 film, is formed. Furthermore, the source and drain diffusion layers are silicided with Pt (19L).

In this example, not only the effect of Example 1 but also the parasitic resistance of the diffusion layer was reduced, and very good characteristics were obtained.

〔Effect of the invention〕

According to the present invention, by adding a film deposition, anisotropic etching, and one-time ion implantation without requiring a new mask, the drain breakdown voltage can be improved by about 3V and the hot water resistance can be increased by about 3V. The carrier breakdown voltage is improved, and elements can be miniaturized without reducing the power supply voltage.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional MIS field effect transistor and an MIS field effect transistor with a normal double diffusion layer, and Figure 2 is a graph of the effective channel length dependence of drain breakdown voltage and hot carrier breakdown voltage. , FIG. 3 is a graph of the internal electric field along the channel, FIG. 4 is a sectional view showing the first embodiment of the invention, FIG. 5 is a sectional view showing the second embodiment of the invention, and FIG. 6 is a sectional view showing the second embodiment of the invention. The figure is a sectional view showing a third embodiment of the invention, and FIG. 7 is a sectional view showing another embodiment of the invention. l...Si substrate, 2...channel implantation, 3...gate oxide film, 4...Si gate, 5
... Phosphorsilicate glass, 6... Photosensitive resin film, 7...
Source/drain electrode, 8... n-diffusion layer, 9...
n''' diffusion layer, 10... Drain breakdown voltage in conventional MIS type field effect transistor, 10'... Drain breakdown voltage when having a normal double diffusion layer, 10'... When using the present invention drain breakdown voltage, 11... conventional MI
Hot carrier breakdown voltage of S-type field effect transistor, 11
'...Hot carrier breakdown voltage when having a normal double diffusion layer, 11'...Hot carrier breakdown voltage when using the present invention, 12...-8t, N4 film, 14...Conventional M
Channel direction electric field in IS type field effect transistor, 15... Channel direction electric field when having a normal double diffusion layer, 16... Channel direction electric field when using the present invention, 17... Tungsten gate, ￥I 1 Fig. 2 Electric 4-Yanenoshi &I'P 笥〕f,, 3 Fig. 4 Fig. R) Fig. 5 (11) ￥i に 口 No. 7 Continuation of Fig. 1 page ■Inventor Horiuchi Katsutada Kokubunji □ Central Research Institute 0 authors Hitoshi Kume Kokubunji City 1η Central Research Institute 0 inventors Toru Kaga Kokubunji City 11 Central Research Institute @ Inventor Yasuo Ikura Kokubunji □ Central Research Institute

Claims (1)

[Scope of Claims] In a MIS field effect transistor formed on a semiconductor substrate of a first conductivity type, at least one of its source and drain is of a highly doped second conductivity type and is not directly under a gate conductor. and the semiconductor field. A semiconductor device comprising a second semiconductor region of low concentration surrounding the gate conductor and extending directly below the gate conductor.