KR960001342B1 - Semiconductor memory device - Google Patents

Abstract

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Description

Semiconductor memory

1 is a cross-sectional view of an essential part of an EPROM which is an embodiment of the present invention.

2 is an enlarged cross-sectional view of a FET constituting a memory cell of the EPROM shown in FIG.

FIG. 3 is a diagram showing impurity concentration distribution in semiconductor regions constituting the FETs of FIG.

4 to 11 are cross-sectional views of essential parts showing the manufacturing method of the EPROM shown in FIG. 1 for each manufacturing step.

12 is a sectional view of an essential part of an EPROM which is another embodiment of the present invention.

BACKGROUND OF THE INVENTION Field of the Invention [0001] The present invention relates to a semiconductor memory device, and more particularly, to a technique effective by applying to a semiconductor memory device having a non-valatile memory function.

EPROM (Erasable and Programmable Read Only Memory) is known as a semiconductor memory device having an ultraviolet (erase) type nonvolatile memory function. The EPROM has a floating gate electrode and a control electrode stacked on it, and has a field effect transistor (storage) that stores information in the form of a charge. FET) constitutes a memory cell. In EPROM, it is one of the important technical problems to improve the storage efficiency of information, to shorten the storage time and to reduce the calling time.

The improvement of the storage efficiency is achieved by increasing the electric field strength near the drain region of the FET and increasing the injection amount of the hot carrier to the floating gate electrode. The shortening of the call time consists of reducing the ON resistance of the channel of the FET to increase the amount of current flowing between the source and drain regions.

In order to increase the electric field strength near the drain region and reduce the ON resistance of the channel, it is conceivable to shorten the FET of the memory cell. However, when a fine FET having a channel length of about 1.5 μm or less is formed, a threshold voltage fluctuates significantly due to a short channel effect.

On the other hand, in the peripheral circuit of the memory array of the EPROM, it is considered to adopt a LDD (Lightly Doped Drain) structure for the FET. In other words, in order to alleviate the electric field strength at the drain junction, the drain region is composed of a semiconductor region having a high impurity concentration and a semiconductor region (hereinafter referred to as a lightly doped region) provided at a lower side with a lower impurity concentration than this region. To construct. In this case, it is considered that the memory cell applies this configuration in order to simplify the manufacturing process.

However, adopting the LDD structure in the FET of the memory cell causes the following problem.

Since the lightly doped region of the FET of the memory cell is formed by the same manufacturing process as the FET lightly doped region of the peripheral circuit, it is formed with a low impurity concentration of about 1 × 10 ¹³ atoms / cm ² . For this reason, low impurity concentrations are formed between Pn junctions between the semiconductor substrate and the lightly doped region to decrease the electric field strength in the vicinity of the drain region, thereby reducing the memory efficiency of the memory cell.

The writely off-off region has a resistance value of about 2 K? / □ which is 20 to 100 times larger than the high impurity concentration region in the drain region. For this reason, since the amount of current flowing between the source region and the drain region of the FET decreases, the call speed and margin of the memory cell decrease.

As a technique to solve these problems, US Patent Application No. 736,770, May 22, 1985 (Japanese Patent Application No. 59-102555). In this technique, the write-off area of the FET of the memory cell is composed of impurity concentration higher than that of the FET of the peripheral circuit.

However, the inventors believe that it is necessary to further improve the storage efficiency and to always maintain the degree of integration.

It is an object of the present invention to provide a technique capable of improving the storage efficiency of an EPROM.

Another object of the present invention is to provide a technology capable of improving the degree of integration of EPROM.

Another object of the present invention is to provide a technology capable of achieving high integration, high memory efficiency, and high speed call of EPROM.

It is another object of the present invention to provide a technique capable of improving the integration of EPROM, high memory efficiency, high speed recall, and at the same time improving the electrical characteristics of peripheral circuit elements.

It is still another object of the present invention to provide a technique capable of improving the injection efficiency of charge into a field effect transistor that accumulates information in the form of charge on the floating gate electrode.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Among the inventions disclosed in the present application, an outline of representative ones will be briefly described as follows.

The memory cell is constituted by an MISFET having an LDD structure, and a semiconductor region having a conductivity type similar to that of a semiconductor substrate and having a higher impurity concentration is formed below the write-off region on the drain side. This increases the electric field strength in the vicinity of the drain region, resulting in an increase in the amount of hot carriers generated, thereby improving storage efficiency.

EXAMPLE

Fig. 1 shows a cross section of the essential part of the EPROM which is an embodiment of the present invention. FIG. 1 shows the FET Qm constituting the memory cell on the left side and the complementary metal insulator field effect transistor (MISFET) Qn and Qp constituting the peripheral circuit on the right side.

In FIG. 1, 1 is a p ⁻ type semiconductor substrate made of single crystal silicon, and 2 is an n ⁻ type well region. 3 is a field insulating film, and is provided on the main surface of the semiconductor substrate 1 or the well region 2 between semiconductor elements. 4 is a p-type or n-type channel stopper area | region, and is provided in the main surface of the semiconductor substrate 1 or the well area | region 2 between semiconductor elements. The field insulating film 3 and the channel stopper region 4 electrically separate the semiconductor elements.

The MIS type FET Qm constituting the memory cell of the EPROM is provided in the semiconductor substrate 1 in the region surrounded by the field insulating film 3 as shown in FIG. MISFET Qm is a semiconductor substrate 1, a first gate insulating film 6, a floating gate electrode 7, a second gate insulating film 8A, a control gate electrode 9, one n-type and n ⁺ type semiconductor regions 10 and 12. Source and drain regions.

The n-channel MISFET Qn or p-channel MISFET Qp constituting the peripheral circuit of the EPROM is provided at the periphery of the semiconductor substrate 1 or the well region 2 in the region surrounded by the field insulating film 3. The MISFET Qn is composed of a semiconductor substrate 1, a gate insulating film 8B, a gain electrode 9, a source and a drain region consisting of one n ⁻ and n ⁺ type semiconductor regions 10A and 12. The MISFET Qp is composed of a well region 2, a gate insulating film 8B, a gate electrode 9, and a source and a drain region serving as one p ⁺ type semiconductor region 13.

Hot electrons are injected into the gate electrode 7 so that the threshold voltage of the MISFET Qm becomes high. Thus, the MISFET Qm having a high threshold voltage corresponding to the information # 0 'and the MISFET Qm having a low threshold voltage corresponding to the information # 1' can be configured. The gate electrode 7 is comprised by the conductive layer formation process of a 1st layer, for example, is comprised from the polycrystalline silicon film.

The control gate electrode 9 and the gate electrode 9 are constituted of a conductive layer forming process of the second layer. For example, a high melting point metal silicide (MoSi ₂ , TaSi ₂ , TiSi ₂ ) is formed on the polycrystalline silicon film. And a polycide film provided with a WSi ₂ ) film. The control gate electrode 9 and the gate electrode 9 are composed of a single layer polycrystalline silicon film, a high melting point metal (Mo, Ta, Ti, W) film, a high melting point metal silicide film, and a black composite film thereof. Also good. The control gate electrode 9 is integrally formed with the control gate electrode 9 of the other memory MISFET Qm arranged in the extending direction to form a word line of the EPROM memory array. The gate electrode 9 of the MISFET Qn and Qp may be configured by the same manufacturing process as the floating gate electrode 7 of the memory MISFET Qm. The n-type semiconductor region 10 of the MISFET Qm and the n ⁻ type semiconductor region 10A of the MISFET Qm are used as the writely do-off region. That is, the memory MISFET Qm or MISFET Qn of the LDD structure is configured. The semiconductor regions 10 and 10A are provided on the main surface of the semiconductor substrate 1 between the semiconductor region 12 and the channel forming region.

An enlarged cross section of an important part of the MISFET Qm configured as described above is shown in FIG. 2, and specific impurity concentration distributions of the semiconductor region 10, the semiconductor region 12, and the like are shown in FIG.

The semiconductor region 10 of the MISFET Qm is configured to have a higher concentration than the semiconductor region 10A of the MISFET Qn. As indicated by reference numeral 10 in FIG. 3, the semiconductor region 10 is composed of, for example, an impurity concentration of about 10 ¹⁹ to 10 ²⁰ atoms / cm ³ , and a low depth of synthesis of about 0.1 to 0.15 μm. The semiconductor region 10A is configured, for example, at about 10 ¹⁸ atoms / cm ³ . The semiconductor substrate 1 is composed of an impurity concentration of about 10 ¹⁵ atoms / cm ³ .

The semiconductor region 12 of the MISFET Qm is composed of, for example, an impurity concentration of 10 ²⁰ atoms / cm ³ or more, as indicated by reference numeral 12 in FIG. ³ , and a junction depth of about 0.25 to 0.4 μm.

The p-type semiconductor region 5 having an impurity concentration higher than that of the semiconductor substrate 1 is provided under the main surface of the semiconductor substrate 1 under the MISFET Qm gate electrodes 7 and 9, that is, under the channel region.

This semiconductor region 5 abuts at least the drain region at the end of the channel side of the drain region. For this reason, the semiconductor region 5 is formed below the semiconductor region 10 of the drain region and below the channel region.

Article as it indicated by reference numeral 5 in FIG. 3, 10, ^16-10 is composed of an impurity concentration of about ¹⁷ atoms / cm ^3. The peak of the impurity concentration in the semiconductor region 5 is about the same or deeper than the semiconductor region 10. For this reason, even if the semiconductor region 5 is provided, the impurity concentration of the channel formation region of the memory MISFET Qm, that is, the surface of the semiconductor substrate 1 under the gate electrode can be reduced. Therefore, the threshold hold voltage of the memory MISFET can be prevented from being increased, thereby reducing the resistance of the channel formation region.

By providing the semiconductor region 5 under the lightly doped region (semiconductor region 10) on the drain side of the memory MISFET Qm, the pn junction between the drain region (semiconductor region 12) and the semiconductor region 5 can be formed at a high impurity concentration. It can be done by joining. As a result, extension of the depletion region toward the semiconductor substrate 1 is suppressed.

Since the depletion of the depletion region can be suppressed, the electric field strength in the vicinity of the drain region of the memory MISFET Qm can be increased. Therefore, the amount of generation of hot carriers (electrons) serving as information can be increased, so that the storage efficiency of the memory cells can be improved.

In addition, by suppressing the depletion region, punch-through between the source region and the drain region (semiconductor region 12) can be prevented (punch through voltage is sufficiently high).

Since the effective channel length of the memory MISFET Qm can be sufficiently secured, the short channel effect can be suppressed.

By employing the LDD structure in the memory MISFET Qm, the effective distance of the write-off-off region (semiconductor region 10) toward the channel forming region is smaller than that of the semiconductor region 12, so that the effective channel length can be sufficiently suppressed.

The lightly doped region (semiconductor region 10) of the memory MISFET Qm is formed to have a higher impurity concentration than the lightly doped region (semiconductor region 10A) of the MISFET Qn, and the electric field strength in the vicinity of the drain region is increased to generate hot carriers. It can be configured to the most suitable impurity concentration. Therefore, the storage efficiency to the memory cell can be improved. On the other hand, the MISFET Qn can constitute the semiconductor region 10A at the most suitable impurity concentration. In other words, it is possible to suppress the short channel effect in the MISFET Qn and to suppress the occurrence of hot carriers.

By providing the semiconductor region 5 under the lightly doped region (semiconductor region 10) on the source side of the field effect transistor Qm, the drain region is a collector region and the semiconductor substrate 1 is a base region and a source region. The impurity concentration of the base region of the parasitic lateral bipolar transistor having the emitter region as the emitter region can be increased, and the injection efficiency of electrons from the emitter region can be reduced. Therefore, the operation of the parasitic linear transistor can be prevented. Therefore, the break drown voltage between the source region and the drain region (between the semiconductor regions 12) of the memory MISFET Qm can be improved.

The memory MISFET Qm of the present embodiment is a principle of operation (storage at a punch-off point) injecting hot carriers generated near the drain region into the floating gate electrode 7. As a result, hot holes generated at the same time as the hot electrons become substrate currents. Since the parasitic latent bipolar transistor is easy to operate with the resistance of the substrate current and the semiconductor substrate 1, it is particularly effective to provide the semiconductor region 5 below the writely off-off region toward the source region as described above.

By employing the LDD structure in the memory MISFET Qm, the active distance to the channel forming region of the writely off-off region (semiconductor region 10) is smaller than that of the semiconductor region 12, so that the floating gate electrode 7 and the source region or drain region are different. Coupling capacity can be reduced.

The characteristics of the memory MISFET Qm are determined by the LDD section (semiconductor region 10) and the semiconductor region 5. Therefore, the impurity concentration of the source region (semiconductor region 12) of the memory MISFET and the source line (not shown) of the EPROM memory cell array formed integrally therewith can be configured to have a high or deep junction depth. Therefore, the resistance value of the source line can be reduced.

The semiconductor region 5 may be formed to have a peak of impurity concentration at a position shallower than the pn junction made by the semiconductor region 12, as indicated by reference numeral 5 'in FIG. In this case, although the threshold hold voltage of the memory MISFET Qm is slightly higher, the junction capacitance between the semiconductor region 12 and the semiconductor region 5 having a high impurity concentration in the source region or the drain region can be reduced.

14 is an insulating film which covers a semiconductor element, 15 is a contact hole, and is provided by removing the insulating film 14 in the upper part of predetermined semiconductor region 12 or 13. As shown in FIG. 16 is a conductive layer and is electrically connected to a predetermined semiconductor region 12 or 13 through a connection hole 15, and is configured to extend the upper portion of the insulating film 14 in a predetermined direction. The conductive layer 15 connected to the semiconductor region 12 used as the drain region of the memory MISFE T Qm may constitute the data line DL extending in the direction crossing the word line.

The configuration of the memory array is shown in US patent application 736,770.

A specific manufacturing method of the EPROM of this embodiment will be described.

A p ⁻ type semiconductor substrate 1 made of single crystal silicon is prepared. Then, an n ⁻ type well region 2 is formed in the main surface of the semiconductor substrate 1 main surface serving as the p-channel MIS FET Qp forming region.

After that, the field insulating film 3 and the p-type or n-type channel stopper region 4 are formed on the main surfaces of the semiconductor substrate 1 and the well region 2 between the semiconductor elements.

Thereafter, as shown in FIG. 4, the gate insulating film 6 is formed on the main surfaces of the semiconductor substrate 1 and the well region 2.

The gate insulating film 6 becomes the first gate insulating film of the memory MISFET Qm. For example, it becomes a silicon oxide film by a thermal oxidation technique, and forms the film about 250 350 micrometers in thickness.

As shown in FIG. 5, a p-type semiconductor region 5 is formed in the main surface portion of the semiconductor substrate 1 in the memory MISFET Qm forming region. The semiconductor region 5 can be formed by introducing, for example, boron having an impurity concentration of about 1 × 10 ¹² atoms / cm ² by an ion implantation technique. At this time, boron is not introduced into the MISFET formation region of the peripheral circuit by covering it with a resist film (not shown). The region 5 is formed to have a peak of impurity concentration at a position deeper than the junction depth of the drain region at a position deeper than that of the lightly doped region formed by the following process. Therefore, for example, an injection energy of about 150 KeV is used. Next, a process of forming the gate insulating film 6 shown in FIG. 4 is followed by a low energy ion implantation technique for adjusting the threshold hold voltage of the memory MISFET Qm to the shallow main surface of the semiconductor substrate 1 through the gate insulating film 6. P-type impurities such as boron or n-type impurities such as phosphorous or arsenic may be introduced.

After the semiconductor region 5 is formed, the first conductive layer in the manufacturing process is formed on the field insulating film 4 and the gate insulating film 6 in the memory MISFET Qm forming region. By chemical vapor deposition (CVD), a polycrystalline silicon film is formed on the entire upper surface of the semiconductor substrate, and phosphorus is introduced into it. In order to form the floating gate electrode of the memory MISFET Qm, the conductive layer is patterned into a predetermined shape to form the conductive layer 7A. This process removes the gate insulating film 6 in the MISFET Qn and Qp formation regions of the peripheral circuit.

Thereafter, as shown in FIG. 6, the second gate insulating film 8A covering the conductive layer 7A is formed in the memory MISFET Qm forming region. The gate insulating film 8B is formed in the main surface portions of the semiconductor substrate 1 and the well region 2 in the MISFET Qn and Qp formation regions in the same manufacturing process. The gate insulating films 8A and 8B are, for example, silicon oxide films by a thermal oxidation technique. The gate insulating film 8A is formed to have a thickness of, for example, about 250 to 350 kV, and the gate insulating film 8B is formed to have a thickness of about 200 to 300 kV, for example.

After the gate insulating films 8A and 8B are formed, impurities are introduced into the main surfaces of the semiconductor substrate 1 and the well region 2 through the gate insulating film 8B to adjust the threshold voltage of the MISFET Qn and Qp. For example, boron of about 1 × 10 ¹² atoms / cm ² is introduced by ion implantation of energy of about 30 KeV.

At this time, since the channel portion of the memory MISFET Qm is covered by the conductive layer 7A, boron is not introduced.

In other words, by using the conductive layer 7A as a mask, the threshold hold of the memory MISFET Qm is controlled independently of that of the peripheral MISFETs Qn and Qp without increasing the process.

Thereafter, the conductive layer of the second layer in the manufacturing process is formed on the entire substrate first upper surface, and the conductive layer is patterned into a predetermined shape.

For this reason, as shown in FIG. 7, the conductive layer 9A is formed in the memory MISFET Qm formation region, and the gate electrode 9 is formed in the MISFET Qn and Qp formation regions. The conductive layer 9A and the gate electrode 9 are formed by, for example, CVD to form a polycrystalline silicon film into which phosphorus (P) is introduced, and a polyside film having a high melting point metal silicide film formed by a spotter thereon. do.

After the process of forming the conductive layer 9A and the gate electrode 9 shown in FIG. 7, a mask 17 for forming the floating gate electrode and the control gate electrode of the memory MISFET Qm is formed. The mask 17 uses, for example, a photoresist film. The mask 17 covers the peripheral circuit region, that is, the MISFET Qn and Qp formation regions, and at the same time, the EPROM memory cell array has the shape of a word line or a control gate electrode. The mask 17 is used to etch the conductive layers 7A, 9A and the second gate insulating film 8A to form a floating gate electrode 7, a control gate electrode 9 or a word line (not shown). At this time, the etching of the insulating film 8B and the semiconductor substrate 1 in the peripheral circuit region can be prevented.

This is because this etching is separated from the etching for the gate electrode 9.

Thereafter, using the mask 17 as a mask, as shown in FIG. 8, the n-type semiconductor region 10B is self-aligned to the gate electrodes 7, 9 in the main surface portion of the semiconductor substrate 1 in the memory MISFET Qm forming region. To form). The semiconductor region 10B is configured to form a lightly doped region having a higher impurity concentration than the lightly doped region of the MISFET Qn of the peripheral circuit. The semiconductor region 10B is formed by an ion implantation technique of energy of about 80 KeV using arsenic of about 1 × 10 ^{13 to} 1 × 10 ¹⁵ atoms / cm ² so as to have an impurity concentration most suitable for generating hot carriers. . By using arsenic as an impurity in the semiconductor region 10B, a shallow junction is formed, so that even when the ion implantation amount is reduced, the surface concentration can be made relatively high. Since the impurity concentration gradient can be made steeper than phosphorus, the electric field strength can be increased to increase the memory efficiency.

The annealing for activating the implanted arsenic to form the semiconductor region 10B is performed after removing the mask 17. However, in FIG. 8, mask 17 and region 10B are shown for convenience.

Thereafter, an insulating film (silicon oxide film) 8C is formed to cover the floating gate electrode 7, the control gate electrode 9, the gate electrode 9 and the like by thermal oxidation. The insulating film 8C may be formed so as to cover at least the side wall of the floating gate electrode 7. As a result, leakage of electrons accumulated in the floating gate electrode 7 can be prevented, thereby improving information retention characteristics. In addition, the insulating film 8C can prevent contamination by heavy metals.

As shown in FIG. 9, a mask 18 is formed to cover at least the p-channel MISFET Qp of the peripheral circuit. The mask 18 is, for example, a resist film. Thereafter, an n ⁻ -type semiconductor region 10A is formed on the gate electrode 9 in the main surface of the semiconductor substrate 1 in the n channel MISFET Qn forming region of the peripheral circuit. Semiconductor region 10A forms MISFET Qn of LDD structure. In the semiconductor region 10A, the gate electrode 9 is used as a mask, for example, phosphorus (P) of about 1 × 10 ¹³ atoms / cm ² is introduced by an ion implantation technique of energy of about 50 KeV, and extended diffusion is performed. It is finished.

Then, annealing for activating the implanted phosphorus to form the semiconductor region 10B is performed after removing the mask 18. However, in Fig. 9, mask 18 and region 10B are shown for convenience.

In the present embodiment, phosphorus (P) is also injected into the memory MISFET Qm formation region.

The mask 18 may also be formed in the memory MISFET Qm forming region, and phosphorus for forming the semiconductor region 10A may not be injected into the semiconductor region 10B. After ion implantation of phosphorus for the region 10A and removal of the mask 18, an insulating film 11 is formed on the sides of the floating gate electrode 7, control gate electrode 9 and gate electrode 9.

The insulating film 11 is a mask that defines a portion 12 of the source and drain regions of the n channel MISFET Qm and Qn. The insulating film 11 is, for example, anisotropic such as reactive ion etching on a silicon oxide film formed on the entire surface of the substrate by CVD under a high temperature of about 600 to 800 ° C. and a low pressure of about 1.0 Torr. It can form by performing etching.

Thereafter, a new mask 19 is formed to cover the P channel MISFET Qp of the peripheral circuit. The mask 19 becomes a resist film, for example. Thereafter, as shown in FIG. 10, n ⁺ type semiconductor region 12 is formed on the control gate electrode 9 or the gate electrode 9 and the insulating film 11 in a self-aligned manner on the main surface of the semiconductor substrate 1 in the n channel MISFET Qm and Qn formation regions. do. The semiconductor region 12 is introduced by an ion implantation technique of about 80 KeV using arsenic ions of about 1 × 10 ¹⁶ atoms / cm ² , for example, using a control gate electrode 9 or a gate electrode 9 and an insulating film 11 as a mask. It can be formed by performing tensile diffusion.

The annealing for activating the implanted phosphorus to form the semiconductor region 10B is performed after removing the mask 18. 9, mask 18 and region 10B are shown for convenience.

In this step of forming the semiconductor region 12, n channel MISFETs Qm and Qn are completed.

The impurity concentration of the semiconductor region 12 is determined in this process.

In the memory MISFET Qm, the impurity concentration of the semiconductor region 12 can be increased irrespective of the impurity concentration of the semiconductor region 10 that determines the storage efficiency and the call efficiency.

As a result, the resistance value of the semiconductor region 12 and the source line formed integrally therewith can be significantly reduced, thereby reducing the area of the source line extending the memory cell array. In addition, since the resistance value of the source line can be reduced, the call efficiency can be improved.

In the embodiment, arsenic is used to form the semiconductor region 12 in order to make the junction depth shallow and achieve short channeling. On the other hand, since phosphorus is used to form the semiconductor regions 10 and 10A, the impurity concentration gradient is not steep, and in particular, the internal pressure of the junction of the lightly doped region can be sufficiently secured.

After the process of forming the semiconductor region 12 shown in FIG. 10, as shown in FIG. 1, a p ⁺ type semiconductor region 13 is formed on the main surface of the well region 2 of the MISFET Qp forming region. The semiconductor region 13 may be formed by introducing diffusion of BF ₂ of about 1 × 10 ¹⁵ atoms / cm ² by ion implantation of energy of about 80 KeV using, for example, a gate electrode 9 and an insulating film 11 as a mask. There is a number. In general, the p-type impurity has sufficiently spread below the insulating film 11 because of its large diffusion rate.

In the process of forming this semiconductor 13, MISFET Qp is completed. In forming the semiconductor region 13, the n channel MISFET Qm and Qn formation regions are covered with a mask (not shown) which becomes a resist film.

After the process of forming the semiconductor region 13 shown in FIG. 11, an insulating film 14 made of, for example, in-silicate glass (PSG) is formed by CVD, and a connection hole 15 is formed therein by etching. Then, as shown in FIG. 1, the conductive layer 16 is formed to be electrically connected to the predetermined semiconductor region 12 or 13 through the connection hole 15. As shown in FIG.

The conductive layer 16 is formed of, for example, an aluminum film formed by a spotter technique or an aluminum film containing Si or Cu.

Thereafter, a final passivation film (not shown) is formed, for example, a PSG film. The formation method of the insulating film 14, the connection hole 15, the conductive layer 16, and a final stabilization film is based on a well-known method.

According to the novel technique disclosed in the present application, the following effects can be obtained.

(1) The memory cell of the EPROM is constituted by an MISFET having an LDD structure, and at least under the right-drain-off region on the drain side, a semiconductor region having the same conductivity type as that of the semiconductor substrate or the well region and having a higher impurity concentration than that. It was.

As a result, the electric field strength in the vicinity of the drain region can be improved, and the amount of generated hot carriers as information can be increased, so that the storage efficiency of the EPROM can be improved.

In addition, since the Pn junction between the drain region and the semiconductor region can be formed at a high impurity concentration, the depletion of the depletion region can be suppressed, so that the effective channel length of the MISFET can be sufficiently secured and the short channel effect can be suppressed.

Since the LDD portion has a small diffusion distance toward the channel formation region and can secure an effective channel length sufficiently, it can be suppressed by a short channel effect. As described above, since the area occupied by the field effect transistor can be reduced, the degree of integration can be improved.

(2) In addition to the configuration of (1) above, the write-off area of the write-off area of the memory MISFET is formed at a higher impurity concentration than the write-off area of the MISFET constituting the peripheral circuit.

As a result, the write-off-off region can be formed at the most suitable impurity concentration for generating hot carriers by increasing the electric field strength in the vicinity of the drain region, thereby improving the storage efficiency to the memory cell.

In addition, since the impurity concentration in the write-off region of the memory cell MISFET can be increased, the resistance value between the source region and the drain region can be reduced, thereby speeding up the call and increasing the call margin.

(3) In addition to the configuration of (1) above, the semiconductor region is also formed below the writely do-off region on the source side of the memory MISFET. As a result, the injection efficiency of the minority carriers toward the source region can be reduced, so that the breakdown voltage between the source region and the drain region of the MISFET can be improved. Therefore, the electrical reliability of the EPROM can be improved.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, this invention is not limited to the said Example, Of course, a various deformation | transformation is possible in the range which does not deviate from the summary.

For example, as shown in FIG. 12, a semiconductor region 18 having a lower impurity concentration than the semiconductor region 5 may be formed under the semiconductor region 12 of the memory MISFET Qm. The semiconductor region 18 is formed to lower the junction capacitance between the source or drain region of the memory MISFET Qm and the semiconductor substrate. This semiconductor region 18 may be formed in a step before or after the semiconductor region 12 by ion implantation using the same mask as the semiconductor region 12 (gate electrode 9 and insulating film 11). Further, for example, the semiconductor region 5 is selectively formed in the portion of the semiconductor substrate 1 that should be below the gate electrode 9 and the insulating film 11 of the memory MISFET Qm in the process shown in FIG. The semiconductor region 18 is formed by masking the gate electrode 9 and the insulating film 11 by ion implanting boron ions with a large energy and a small dose. Alternatively, the semiconductor region 5 is formed as shown in FIG. 5, and then n-type impurities such as phosphorus are formed as if the semiconductor region 5 is somewhat negated using the gate electrode 9 and the insulating film 11 of the memory MISFET Qm as masks. Is introduced to form the semiconductor region 18.

The memory MISFET Qm or the MISFET Qn of the peripheral circuit may be formed in a p ⁻ type well region having a higher impurity concentration than that formed in the semiconductor substrate 1. When two well regions of n-type and p-type are formed, and the MISFET is formed in any well region, n-type other than the p-type of the conductive type of the semiconductor substrate 1 may be used.

The present invention is not limited to the EPROM, and can be widely applied to a FET having a floating gate electrode and injecting a hot carrier to accumulate information in the form of charge thereon.

Claims (25)

A first semiconductor region of a first conductivity type formed on one surface of a semiconductor substrate, a floating gate electrode formed on the first semiconductor region, a control gate electrode formed on the floating gate electrode, and the two gates Two second semiconductor regions of a second conductivity type formed in the first semiconductor regions on both sides of the electrode, and function as source and drain regions of the MISFET of the second semiconductor region, each of the second semiconductor regions being And a second region having an impurity concentration lower than an impurity concentration of the first region and extending deeper than the second region to the first semiconductor region of the first region. A storage MISFET formed between at least the channel region of the MISFET and the first region of the first semiconductor region and at least the two gate electrodes; A third semiconductor region formed below the two regions, having a first conductivity type, having an impurity concentration higher than that of the first semiconductor region, and being in contact with the second region serving as the drain region of the MISFET; A semiconductor memory device included. The method of claim 1, further comprising an insulating film formed on side wells of the two gate electrodes, wherein the second region is self-aligned to the two gate electrodes, and the first region is A semiconductor memory device formed in self-alignment with two gate electrodes and the insulating film. The semiconductor memory device according to claim 1, which is formed under said second semiconductor region of said third semiconductor region. 6. The semiconductor memory device according to claim 5, wherein a portion formed under the first region of the third semiconductor region has a lower impurity concentration than other portions. The semiconductor memory device according to claim 1, wherein the peak of the impurity concentration in the third semiconductor region is deeper than the second region. 8. The semiconductor memory device according to claim 7, wherein the peak of the impurity concentration in the third semiconductor region is at the same position as the junction between the first region and the semiconductor substrate. 8. The semiconductor memory device according to claim 7, wherein the first and second degree typical p-type and n-type semiconductor devices, respectively. The semiconductor memory device according to claim 9, wherein the first and second regions are formed by introducing arsenic as an impurity. A first semiconductor region and a fourth semiconductor region of a first conductivity type formed on one surface of a semiconductor substrate, a floating gate electrode formed on the first semiconductor region, and a control gate electrode formed on the floating gate electrode And two second semiconductor regions of the second conductive type formed in the first semiconductor regions on both sides of the two gate electrodes, one side of the second semiconductor region being a source region and the other being a drain region, A second semiconductor region is formed of a first region and a second region, the first region is formed separately from the region under the two gate electrodes, and the second region is the first region and the two gate electrodes. A storage MISFET formed between the bottom region and having a lower impurity concentration than the first region, the at least one second under the two gate electrodes; A third semiconductor region formed in the first semiconductor region, having a higher impurity concentration than the first semiconductor region, and formed in contact with the drain region, the fourth semiconductor region formed on the semiconductor substrate; A fifth semiconductor region of the second conductive type formed in the fourth semiconductor region on both sides of the gate electrode and the gate electrode, wherein the fifth semiconductor region is composed of a third region and a fourth region, and A third region is formed separately from the region under the two gate electrodes, and the fourth region is formed between the third region and the region under the gate electrode and is lower than the third region and the second region A semiconductor memory device comprising a MISFET having a lower impurity concentration. 12. The semiconductor memory device according to claim 11, wherein an impurity concentration of the first region is equal to an impurity concentration of the third region. The method of claim 12, wherein the first and second conductivity types are p-type and n-type, respectively, and the first, second and third regions are formed by introducing arsenic as impurities. The fourth region is formed by introducing phosphorus as an impurity. The semiconductor device according to claim 11, further comprising a sixth semiconductor region of a second conductivity type formed on the first main surface of the semiconductor substrate, a gate electrode formed on the semiconductor substrate, and the sixth semiconductor region on both sides of the gate electrode. And a MISFET formed in said sixth semiconductor region, said seventh semiconductor region being two first conductive types formed therein, said first and second conductive types being p-type and n-type, respectively. 15. The device of claim 14, further comprising an insulating film formed on a sidewall of a gate electrode of each MISFET formed in said first, fourth, and sixth semiconductor regions, wherein said second and fourth regions comprise said gate electrode. Self-aligned with each other, the first and third regions are formed in the gate electrode and the insulating layer, and the seventh semiconductor region uses the gate electrode and the insulating layer as a mask to introduce impurities. The semiconductor memory device formed by. A first semiconductor region of a first conductivity type formed on one main surface of the semiconductor substrate, a floating gate electrode formed on the semiconductor substrate, a control gate electrode formed on the floating gate electrode, and the two gates A channel region in the first semiconductor region below the electrode and two semiconductor regions of a second conductivity type formed in the first semiconductor region on the opposite side of the two gate electrodes, the source of the second semiconductor region and Each of the second semiconductor regions has a first region and a second region having an impurity concentration lower than an impurity concentration of the first region, the first region being the first semiconductor region; It is formed to extend deeper than the two areas, and is formed to be self-aligned with the two gate electrodes of the second area, the first area and the It has an impurity concentration higher than that of the memory MISFET and the first semiconductor region formed between the channel regions, and is disposed at a predetermined depth of the first semiconductor region, and the peak of the impurity concentration is the maximum depth of the second region. Formed in contact with the second region and extending below the first region of the source and drain regions, and formed in at least the two gate electrodes and the first semiconductor region below the second region. A semiconductor device comprising a third semiconductor region of the first conductivity type. A first semiconductor region of a first conductivity type formed on one main surface of the semiconductor substrate, a floating gate electrode formed on the semiconductor substrate, a control gate electrode formed on the floating gate electrode, and the two gates Two semiconductor regions of a second conductivity type formed in the first semiconductor region on the opposite side of the electrode, wherein the second semiconductor region functions as a source and drain region of the MISFET, and each of the second semiconductor regions And a second region having an impurity concentration lower than an impurity concentration of the first region, wherein the first region extends deeper than the second region into the first semiconductor region. A memory MISFET formed between at least the first region and the channel region of the MISFET in the first semiconductor region and the fire of the first semiconductor region The first region of the source and drain regions such that the impurity concentration is higher than the water concentration, and the peak of the impurity concentration is at a depth greater than or equal to the maximum depth of the second region and in contact with the first region of the source and drain regions; And a third semiconductor region of a first conductivity type extending downward and formed in at least the two gate electrodes and the first semiconductor region below the first region. A first semiconductor region of the first conductivity type formed on one main surface of the semiconductor substrate, a control gate electrode formed on the first semiconductor region, and a control gate electrode formed on the floating gate electrode, and the opposite sides of the two gate electrodes. Two semiconductor regions of a second conductivity type formed in the first semiconductor region, wherein the second semiconductor region functions as a source and a drain region, and each of the second semiconductor regions is a first region and the first region. And a second region having an impurity concentration lower than an impurity concentration of the second region, wherein the first region extends deeper into the first semiconductor region than the second region, wherein the second region is at least the first region and the channel. Has an impurity concentration higher than that of the memory MISFET and the impurity concentration of the first semiconductor region formed between the formed portions of the first semiconductor region, A peak of water concentration is at a depth greater than or equal to the maximum depth of the second region and extends below the first region of the source and drain region to be in contact with the first region of the source and drain region, and at least the two gates And a third semiconductor region of a first type typically disposed under the first and second regions and formed in the first semiconductor region, wherein an impurity concentration of the first semiconductor region in which the channel is formed is the third semiconductor region. And a third semiconductor region formed below the second region of the source and drain to be in contact with the second region. 20. The semiconductor device according to claim 19, wherein the third semiconductor region is disposed at a predetermined depth in the first semiconductor region. The semiconductor device according to claim 20, wherein the third semiconductor region is arranged to surround the first region. The semiconductor device according to claim 21, wherein the first conductivity type is p-type and the second conductivity type is n-type. The semiconductor device according to claim 22, wherein said memory MISFET has an LDD structure. 24. The apparatus of claim 23, further comprising an insulating film formed on sidewalls of the two gate electrodes, wherein the first region is self-aligned with the two gate electrodes and the insulating film, and the second region. Is a self-aligning semiconductor device formed on the two gate electrodes. A semiconductor device according to claim 24, wherein said storage MISFET comprises memory cells of an erasable and programmable read only memory (EPROM). 26. The semiconductor device of claim 25, wherein the first semiconductor region is a p well region disposed on a semiconductor substrate. 27. A semiconductor device according to claim 26, further comprising a MISFET formed in a fourth semiconductor region of a first conductivity type formed on a main surface of the semiconductor substrate, wherein the MISFET comprises a gate electrode formed on the semiconductor substrate and the gate electrode. Two fifth semiconductor regions of a second conductivity type formed in the fourth semiconductor regions on both sides, each of the fifth semiconductor regions having an impurity concentration lower than that of the third region and the third region; And a fourth region, wherein the fourth region has an impurity concentration lower than that of the second region, is formed self-aligned to the gate electrode, and has at least a portion of the fourth semiconductor region formed with channels. A semiconductor device formed between three regions. The semiconductor device according to claim 27, wherein the MISFET in the fourth semiconductor region constitutes a peripheral circuit of the EPROM.

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