JPS60158670A - Thin film transistor and its manufacturing method - Google Patents

Abstract

PURPOSE:To prevent contamination during processes, and to reduce mask processes to numbers the same as or fewer than the conventional devices by continuously depositing an amorphous Si film, a gate insulating film and a conductive film for a gate electrode in the same chamber by using plasma CVD, etc. CONSTITUTION:First and second main electrode regions 1, 2 and 11, 12 in a T1 consisting of a metallic film and an n<+> amorphous Si film (a-Si film) and first and second main electrode regions 101, 102 and 111, 112 in a R2 are formed on an insulator substrate 10. a-Si films 3, 103, gate insulating films 4, 104 and conductive films 5, 105 for a gate electrode are deposited, and unnecessary sections are removed. The conductive film 105 for the gate electrode in a thin-film transistor (TFTT2) extends up to a section in the vicinity of the second main electrode 2 in a TFTT1. A metallic film is deposited to form a wiring between the gate electrode 105 in the TFTT2 and the second main electrode region 2 in the TFTT1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thin film transistor (TPT) that is highly reliable and easy to manufacture, and a method for manufacturing the same.

TPT mainly using amorphous Sj (α-8i) is
Due to the low temperature at which it is produced, it is expected to be applied to large-area, inexpensive electronic devices such as liquid crystal display devices and image sensors. However, large-area devices and cost reductions require simplification of the manufacturing process. On the other hand, improving reliability is also considered a must.

FIG. 1 shows an example of a conventional TPT manufacturing process. 1st
In the step (α), the first lattice film, which becomes a drain or drain, is placed on an insulating substrate 10 made of quartz or the like. The second main electrode regions 1 and 2 are n
A cross section formed of a multilayer film of +α-s7, gold, and metal film 70 is shown. The first #second main current moderation regions 1.2 are separated from each other via an insulator, which is the substrate 10, and the mutual distance therebetween approximately corresponds to the channel length. FIG. 1(b) shows a cross section in which α-8 (film 3 is deposited on the entire surface by plasma OVD, optical OVD, ion beam deposition, molecular helix deposition, etc., and unnecessary parts are removed. α-
S (film 3 is doped with hydrogen or fluorine to suppress the level density in the forbidden band to be low. However, in this process, α-
Since s4 is exposed to the outside air, there is a problem that the surface is easily contaminated. In FIG. 1 ((+), after depositing a silicon oxide film to become the gate insulating film 4 in the same manner as the α-si film described above,
1st. A state in which contact holes are provided on the second main electrode regions 1 and 2 is shown. Again, there is a problem that the gate insulating film 4 is exposed to the outside air. As shown in FIG. 1(d), gold R (multilayer film) such as A4, Of, MOpM1, etc. is deposited to form the gate electrode 5 and the first. The external wiring 21 and 22 for the second main IIt poles 1 and 2 are provided to complete the process. In the conventional example described above, the surfaces of the a-Bi film 3 and the gate insulating film 4 on which the channel is formed are exposed to the outside air, which causes n1 contamination, which in turn causes the threshold voltage and its temperature fluctuation. Also, the mask process is 4
It is also effective to reduce costs.

The present invention has been made in view of the problems of the conventional process of slanting, and provides a TPT structure in which α-"srs gate insulating film and conductive film for gate electrode can be deposited without being exposed to the outside air. It also has the purpose of simplifying the wiring process by utilizing the high resistance of the α-Si film.

The present invention will be explained in detail below using the drawings. In Figure 2, 2
An example of the manufacturing process when TFTTI and T2 are adjacent to each other will be shown. In FIG. 2(α), the first and second main abrasive regions 1, 2, 11, 12 of T1, which are made of a metal film and an n+α-Si film, and the main abrasive regions 1, 2, 11, 12 of T2, and 1.
Second main electrode regions 101 , 102 and 111 , 112
(not shown). In FIG. 2<b>, c-8jli3, 103, gate insulating film 4,
104 shows a cross section in which unnecessary portions are removed by the same mask process after depositing conductive films 5 and 105 for gate electrodes. Le+α
-8i) Parts of 11, 12, 111, and 112 tend to be partially removed in this process. In this example, T.F.
The gate electrode conductive film 105 of TT2 extends close to the second main electrode 2 of TFTTl. In this case, the length of the field a must be longer than the channel length of TPTT2, and the width must be narrower than the channel width. Figure 2 (0)
So, gold! AU is deposited to form the gate electrode 10 of TFTT2.
2(d) shows a cross section in which wiring or other wiring is formed between the second main electrode region 2 of TPTT1 and the second main electrode region 2 of TPTTl, and FIG. 2(d) shows a plan view thereof. In this example, the mask process is performed three times, which simplifies the process. The disadvantage is that the gate electrode area is larger than the conventional one, but the α under the gate insulating film
- Since the resistance is high, the increase in gate capacitance and the increase in gate leakage current are substantially small compared to the conventional technology.

Furthermore, the second main electrode 2 of TPTTl and M of TFTT2
l, the second main electrodes 101 and 102 are α-841141
Although short-circuited through 03, substantially c-sj
Due to the high resistance of #03, it is possible to select the dimensions of the gate electrode extension portion of T F T'T 2 so as to have almost no influence on #1 electrically. In the present invention, α-s4 membrane 3.
103, the gate insulating films 4 and 104 can be deposited consecutively in the same chamber or in separate chambers (when used in-line) without being exposed to the outside air by using plasma OVD, etc., so there is no need to worry about contamination. Electrode 5
, 105 can also be continuously deposited by using, for example, n+α-s4. Furthermore, as a gate electrode, n
-It is effective to reduce the resistance if metals such as M, Or, Mll, W, Tα or their silicides are deposited next to s4. FIG. 3 shows a process sectional view of another embodiment of the present invention. FIG. 3(b) is a cross section of the first and second main electrode regions 1, 2 formed on the insulating substrate 10, and FIG. 3(b) shows the α-s4 film 3, A cross section of the deposited gate insulating film 4 and gate electrode conductive film 5 is shown. FIG. 3(C)
Then, in the same shape, gate electrode 5, gate electrode #2R4, α
-S4 Shows a state left in the form of islands on the membrane 3. FIG. 3(d) shows that after the field insulating film 6 is deposited on the entire surface, contacts for each electric body are opened, and the first. 2nd main power supply 1, 2
, wirings 21 , 22 , and 25 of the gate electrode 5 are completed, and the completed state is shown. The field insulating film 6 is plasma OVD.

In addition to low-temperature deposited silicon oxide and silicon nitride films such as 0VDt photo-coated films, coated oxide films and coated films such as polyimide are also used. Because of this field insulating film 6, the masking process is the same as the conventional one, but the insulation between each electrode and wiring can be more completely achieved.

FIG. 4 shows an embodiment in which the present invention is applied to a vertical TFTK. In Figure 4 (c), after forming the first main electrode region 1 (e.g. n+a-Bi/cr) on the substrate 10, the insulation M16 and the second main electrode region (e.g. M6/n+G-8()) are formed on the substrate 10. 2 is deposited, and the second main electrode region 2 and the insulating film 16 are patterned so as to partially overlap the first main electrode region 1. In FIG. 4(b), α-day i
Membrane 3, gate insulation B4. The gate electrode 5 is successively deposited, leaving these three layers on the side surfaces of the insulating film 16.

FIG. 4 ((+)) shows a completed cross section after depositing a field insulating film 6, forming contact holes, and making wires.

In this example, the channel length is approximately equal to the thickness of the insulating film 16, but it can also be applied to a case where the side surfaces of the insulating film 16 are smoothed. In the conventional method for manufacturing vertical ff1 TFTs, the α-Si film was patterned after α-Si deposition and a gate insulating film was deposited, so that the gate insulating film played the role of a field insulating film. Therefore, it was not possible to obtain a sufficiently thick field insulating film, and one additional mask process was required to make the gate and field insulating films different in thickness. According to the present invention, there is an advantage that the thickness and quality of the field insulating film can be selected independently with the same number of mask steps as in the conventional method.

As described above, according to the present invention, it is possible to realize a TPT that is resistant to contamination during the process and can be manufactured using a mask process that is equal to or less than the conventional mask process. Also, the film thickness of the field insulating film and gate insulating film is 1. It has the advantage that the film quality can be selected independently. Although the explanation has mainly been given using a-EJi as an example, polycrystalline s
6. The present invention can also be applied to other semiconductor thin films, and the present invention is industrially important.

[Brief explanation of the drawing]

Figure 1 (υ~Cd) is a cross-sectional view of the conventional TPT manufacturing process.
Figures 2 (α) to (+1) are cross-sectional views of the manufacturing process of TPT according to the present invention, Figure 2 (d) is a plan view, and Figure 3 (α)
-(d) and FIGS. 4(α)-(6) are sectional views for explaining other embodiments of the present invention. 11. first main electrode region, 21. Second main electrode region 30. α
-s4 membrane 40. Gate insulating film 5. . Gate electrode 6,16. , insulating film 10. , more than 1,000 boards Figure 3 Figure 4

Claims (5)

[Claims] (1) The first insulators are spaced apart from each other with an insulating material in between. The second main electrode region, the 011 insulator and the fitl
A thin film transistor comprising a semiconductor thin film provided in contact with the main electrode region, a gate insulating film and a gate electrode provided on the surface of the semiconductor thin film opposite to the side in contact with the main electrode region, the gate electrode; A thin film transistor characterized in that a gate insulating film and a semiconductor thin film are formed in substantially the same shape. (2) The thin film transistor according to claim 1, wherein the first and second main electrode regions are spaced apart from each other in the vertical direction with an insulating thin film interposed therebetween, and is an fcR type thin film transistor. (3). A first step of forming first and second main electrode regions separated from each other with an insulating substrate or i8 green film in between, a second step of depositing a semiconductor thin film, a third step of depositing a gate insulating film, and a gate. a fourth step of depositing a conductive film for an electrode; a fifth step of selectively etching the conductive film for the gate electrode, the gate mucogreen film, and the semiconductor thin film using the same mask; A method for manufacturing a thin film transistor, which includes a sixth step of wiring in the first or second main electrode region of the transistor. (4) Said 2. Third. 4. The method for manufacturing a thin film transistor according to claim 3, wherein the fourth step is performed continuously without being exposed to the outside air. (5) After the fifth step of Sil, an insulating film is deposited on the entire surface, and a contact hole f is formed on a part of the first and second main electrode regions and the gate electrode. A method for manufacturing a thin film transistor according to claim 3 or 4.