JPS60153079A - Pattern generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention is directed to a pattern generation device, which effectively decomposes character patterns, graphic patterns, etc. into line segments having a length longer than a predetermined length and blocks that cannot be represented by the line segments. The present invention relates to a pattern generation device having means for storing the patterns and synthesizing them in accordance with an output request.

<Prior art> 1. With the advancement of Japanese language processing technology, character pattern generators not only memorize - as in the past, but also, for example, can find typefaces other than Mincho. There is a growing demand for higher functionality, such as by using it for text, or by changing the font size for ruby and footnotes.

However, if characters are stored as dot patterns for each font or size, the memory capacity becomes enormous.
Although there will be a trend toward higher memory density and lower prices in the future, this cannot be said to be a good idea.

Therefore, a method has been developed to break down the character pattern into several types of line segments and compress the tails for high-speed generation.In that method, all character patterns are treated as line segments, so one
It would be a shame to make the dots into line segments.

<Purpose of the Invention> Therefore, in the pattern generation device of the present invention, a line segment is defined as a line segment consisting of continuous dots of a predetermined slice level or higher, and the line segment is divided and stored vertically or horizontally, and
The slice level below the predetermined slice level is stored as a matrix block in order to optimize the compression of pattern data.

Examples Hereinafter, the configuration of the present invention will be described with reference to the drawings.

FIG. 1 is a block configuration diagram of a pattern generation device according to an embodiment of the present invention, in which 101 is a CPU (central processing module M) that controls input and output of stored pattern data;
2 is a memory in which a control program is stored, and 103 is a vertical line pattern.

Memory for storing and layering horizontal line segments and blocks, 104
is the memory 103 under the control of the CPUl0I.
A pattern generation logic 105 generates a pattern from data transferred from the pattern generation logic 10.
This memory stores the pattern generated in step 4.

Figure 2 shows the structure of the data stored in the memo IJ-103, in which (a) shows M line segment information, (b) shows horizontal line segment information, and (c) shows the horizontal line segment information. represents block information.

That is, in the same figure (a), 5Xli, J SXαl+j is the starting address of the vertical line segment, xoi ex+i eXαi is the end point address of the vertical line segment, In the same figure (b), 5yo1. j Syll, j SyβzrJ is the starting address of the horizontal line segment, yOJ y1j eyβJ is the end point address of the horizontal line segment, It shows.

Further, in FIG. 2(c), l-n5n represents the coordinate position of a block, and block patterns IJ, .

FIG. 3 is a flowchart showing the processing contents of the pattern generation logic 104.

FIG. 4 shows the pattern generation logic 104 and the memo IJ.
, -105 in more detail.

FIG. 5 shows a dot pattern representing a block.

As shown in the figure, a block is expressed as a 3×3 matrix, and the dots composing the matrix are
n2 +ns +n+ +n! +na h117
The blinking or lighting information of r n8r n is the block pattern 1. ..., stored in the block pattern γ.

? 1JJ6 is a specific example of a dot display using a dot pattern representing the above-mentioned blocks.

FIG. 7 shows a specific example of a character pattern to be generated.

! FIG. 8 shows a block dot pattern excluding the vertical and horizontal line segments of the character pattern shown in FIG. 7.

As shown in Fig. 7, the character pattern is represented by a tono. In the figure, the character ``open'' is expressed, but this character ``open'' is
The method for generating patterns will be explained.

In the figure, 5XO-3XI°"Xa represents the vertical line segment of the character ``open'', and Syo, Syl...Sy represent the horizontal line segment of the character ``open''. Then, the vertical line segment S X 6 h S X yo... SX month and the horizontal line segment Syo of the same character "open".

The arrangement of Syl...syu is determined by the coordinate axis 11J. In this manner, the line segments are converted into coordinates in advance and stored in the memo IJ-103.

The blocks shown in FIG. 8 are stored in the memory 103 as coordinates (rn, n) in a 3×3 matrix and a blocking pattern represented by the matrix. In the figure, eight types of blocks are displayed.

Next, the process of generating a pattern from the memo u-103 will be specifically described.

The CPU 01 extracts line segment information from the memo IJ-1, 03 and transfers it to the pattern generation logic 104. The pattern generation logic 104 performs generation processing based on the transferred data, and then notifies the CPUI O1 of the completion of the processing. Then, the CPU I O1 sequentially transfers data for vertical line segments, horizontal line segments, and blocked dot patterns to the pattern generation logic 104, and the generated patterns are stored in the memory 105. These are illustrated in a flowchart in FIG.

Here, the operation of the pattern generation logic 104 that receives data from the CPU I O1 and generates a pattern will be explained.

In FIG. 4, information on the 5 bus 452 is converted into data from the CPU by an output control signal 451 and sent to registers 410 and 41.
1,412 cents sequentially.

These three registers indicate the start address and end point address of a vertical line segment, and are called the vertical stroke column register, vertical stroke row register, and vertical stroke end point register, respectively. The signal of the vertical stroke column register 410 is output from the column address buffer 4 selected by the output control signal 462.
16 to the memory 441 as a column address signal. The starting point address in the row direction is set in the vertical stroke row register 411, and the vertical stroke end point register 4
12 is set to the row address corresponding to the end point. The data in the vertical stroke row register 411 is preset in the presettable counter 413 by a preset signal 3455 sent by the clock and timing generation circuit 415, and the data in the row address buffer 417 selected by that signal or the output control signal 462 is preset. The row address signal bus 457 is connected to the memo U-441 via the row address signal bus 457. The black level data is selected by the multiplexer 440 and written into the memory 441K by the write data signal 458. A comparator 414 compares the output of the presettable counter 413 and the output of the vertical stroke end point register 412 by 11ffL, counter 4
．． If the output of -13 is larger, it will be 1 loaf.
- The completion of the transfer is reported to the timing generation circuit 415, and the timing generation circuit 415 turns on the transfer ready signal 453 in order to receive the next vertical stroke. The comparator 4
14, while the output of the counter 413 is less than the output of the register 412, the counter 413 is incremented by the clock signal "455" outputted from the timing generation circuit 415 and sequentially written to the memory 441.

The circuit configuration for the horizontal line segment is the same as that for the double vertical line segment. That is, on the output side @ polarized code 451, the information from C1) U to the data signal bus 452 or the registers 420, 421,
4.22, the upper nod is sequentially increased.

These three registers indicate the starting point address and end point address of the horizontal line segment, and are called the horizontal stroke row register, yellow stroke column register, and horizontal stroke end point register, respectively. The signal of the horizontal stroke row register 420 is output from the row address buffer 4 selected by the output control signal 462.
The PA is connected to the memory 441 via the row address signal 26.

A starting point address in the column direction is set in the horizontal stroke column register 421, and a column address corresponding to the end point is set in the horizontal stroke ending point register 422. The data in the horizontal I/loaf column register 421 is based on the preset signal 45 sent out by the clock and timing generation circuit 425.
4-4.1 The column address signal is preset in the presettable counter 423 by 5 and transferred to the column address buffer 427, which is selected by the output control signal 462, on the column address signal 456. connected to. The data stored in the memory 441 is selected as a black level by the multiplexer 440, and is switched by the input data signal 458. The comparator 424 compares the output of the presettable counter 423 with the end of the horizontal stroke and the output of the disc 422, and when the output of the counter 423 becomes sharper, it reports the completion of one stroke to the timing generation circuit 425, and The timing generation circuit 425 transfers ready 4 to receive the next horizontal transfer.
Turn on g-53453. As long as the output of the counter 423 is not smaller than the output of the register 422 in the comparator 424, the counter 423 is incremented by a clock signal 455 outputted from the timing generation circuit 425, and sequentially written into the memory 441.

The dot pattern information represented by the matrix is set by the output control signal 451 and the data signal bus 452 in the block row address register 43o1 block 2. Addresses in the row and column directions corresponding to the starting point of the dot matrix are set, and the block pattern is a block pattern. It is set in the registration disk 432. The block row address register 430 and block column address register 431
The output signal is multiplied by a necessary multiplying factor by multipliers 433 and 434 in order to generate a starting point address to the memory 441, and then sent through a row address buffer 438 and a column address buffer 1439 selected by an output control signal 462. Connected to Memo U-441. When this memory address is set, the clock and timing generation circuit 437
For example, the output of the block pattern register 432 configured as a parallel-in/serial-out shift register is written one dot at a time via the multiplexer 440 as write data in the memory 441. When one dot is completed, a clock signal J8'460 is output, and the column direction counter 435 and row direction counter 436 are incremented. When this operation is performed for the number of dots in the matrix, the counter 436 issues a count stop signal 5459, reports the completion of writing for one matrix pattern to the timing generation circuit 437, and outputs a request to send the next matrix pattern to the CPU. do. By repeating this operation a necessary number of times, the pattern can be stored in the generated pattern storage memory 441.

The above embodiments have been described in which graphic patterns can be generated using a memory that has been stored in advance as vertical line segment information, horizontal line segment information, and blocking pattern information.

<Effects> As described above, the pattern generator of the present invention provides the following effects. In other words, for example, when displaying kanji dot patterns, conventional systems store all patterns as strokes, so even strokes of one or two dots can be uniformly handled with one stroke's worth of memory. Therefore, it may not be said that the latent features of the kanji pattern are effectively utilized.
A block representation is adopted for the dots, and the configuration of the block can be optimized by taking the number of history by numerical calculation or by changing the size. It is possible to respond flexibly. As such, the present invention is advantageous for multifment generator compression techniques that generate multiple types of truncations from a particular basic compression pattern.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the pattern generator of the present invention;
FIGS. 2(a), (b), and (c) are data explanatory diagrams of the pattern generator, FIG. 3 is a flowchart showing the processing contents of the pattern generator, and FIG. 4 is a more detailed diagram of the pattern generator. Fig. 5 is a block diagram expressed by dots, Fig. 6 (a), (b)
, (c), (d), (e), (f),
(g), (h), and (i) are diagrams showing examples of dot pattern display, Figure 7 is a pattern diagram of the character "open", and Figure 8
The figure is a partial pattern diagram of the character "open". 101-CPU, 102 Memory, 103-Memory, 104-Pattern generation logic, 105 Memory~
, 410 - Vertical stroke row disc, 411 Vertical stroke row disc, 412 Vertical stroke end point disc,
413-・Prisenokbulkaunk, 414 Comparator,
415 - Clock and timing generation circuit, 416
Column address buffer, 417 Row address buffer, 4
2 0-=ti4 stroke ij resik, 421-
[Stroke string register, 422 @stroke end register, 423 pre'J+,), >, tuple counter,
424 Comparator, 425... Black, red and timing generation circuit, 426 Row address buffer 1, 427 ・
Column address buffer, 430・Block row address register, 431 Block column address register, 432・
・Block pattern register, 433... multiplier,
434 Multiplier, 435 Counter, 436 Counter, 437 Clock and timing generation circuit, 438
- Row address buffer, 439 - Column address buffer, 440 - Multiplexer, 441... Generation pattern storage memory, 451... Output control signal, 452 - Data signal, 453 Transfer ready signal, 454 Clock signal 'j, '455... Preset reliability, 456...
Column address signal, 457...Row address signal, 458
Write data signal, 459... count stop signal, 460 clock signal, 46 clock signal,
462...Output control signal. Lee (embedded patent attorney Aihiko Fukushi (and 2 others)), 2
Figure 4 Figure 5 Figure (a) (b) (d (d) (e) (f) Scales Figure 7

Claims (1)

[Scope of Claims] 1. A pattern generation device that generates patterns such as characters, figures, etc. in dots, which is provided with means for classifying dot patterns into blocks above a predetermined slice level and other blocks, storing and outputting the patterns. A pattern generator characterized by: