JPS60143395A - Multicolor display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention uses light emitting diodes of three different colors (hereinafter referred to as LEDs) as unit elements, and
The present invention relates to a multicolor display device that displays a pattern to be displayed in multiple colors by using a matrix display panel in which EDs are arranged in a matrix.

[Prior art]

2. Description of the Related Art Conventionally, there is a display device in which LEDs emitting various colors such as red, green, or blue are formed into units and these LEDs are combined to perform multicolor display. However, in this type of display device, when performing multicolor display by combining the emitted light colors of each LED, each LED is driven to emit light at a constant duty, so the brightness of each display color may become uneven. However, there were problems in that display quality was impaired due to uneven brightness, and that it was not possible to display arbitrary patterns in multiple colors. [Summary of the Invention] The present invention was made in view of the above points. The purpose of this is to use LEDs of three different colors as unit elements, and to use a matrix display panel in which these three colors of LEDs are arranged in a matrix, it is possible to display an arbitrary pattern. To provide a multicolor display device capable of displaying images in multiple colors without unevenness.

In order to achieve such an object, the present invention uses LEDs of three different colors as unit elements, and uses LEDs of these three colors as a unit element.
A matrix display panel in which are arranged in a matrix,
A three-color pattern signal generation circuit that generates arbitrary pattern signals for each row of LEDs arranged on the matrix display panel corresponding to the pattern to be displayed on the matrix display panel, and a combination of colors based on color information. a color signal generation circuit that generates color signals of three colors each having a duty of one integer fraction of the number; and a color signal generation circuit of each of the three colors generated by this color signal generation circuit. (1) A selection drive circuit that sequentially drives each row of LEDs arranged on a display panel; a drive circuit that sequentially drives each row of LEDs arranged on the matrix display panel in synchronization with each pattern signal generated by the three-color pattern signal generation circuit; The pattern is displayed in multiple colors. Hereinafter, embodiments of the present invention will be explained in detail using one page.〇 [Embodiment] Fig. 1 is a block diagram of a circuit configuration shown in -Embodiment 7 of a multicolor display device according to the present invention. , a case is shown in which the pattern to be displayed is divided into three zones and each zone is multi-colored using a combination of red, green and blue. In the figure, LEo 2.3 and 4 of three colors exhibiting red, green and blue, respectively, are used as unit elements, and these LEDs 2 to 4 share one of the row selection lines X1 to Xn and are independent for each color. Triple column selection line Yrl
~Yrm, Yf1~Yfm and Yb1~Ybm
A matrix display panel arranged in a square shape is connected to each of the above-mentioned LEs.
For convenience, D 2 to 4 are LEo 2 to 4 in the 1st row and 1st column.
11°311, 411, and hereinafter, the numerical values in each row and two columns are similarly indicated by subscripts.

Further, 10 is a clock generator that generates clock pulses of a predetermined frequency, and 11 is a hexadecimal counter that counts the clock pulses sent out from the clock generator 10.
This output pulse φ has a period of 6To, where the period of the clock pulse is To. 12 is an n-ary row counter that receives the pulse φ from the hexadecimal counter 11;
13 is a row decoder for decoding the output from the row counter 12; 14 is a drive circuit consisting of transistors 141 to 14n connected to each row selection life Xl to Xn of the matrix display panel 1; By using the decoded output of the row decoder 13 as a scanning signal and turning on and off the respective transistors 141 to 14n, the row selection lines X] to Xn of the matrix display panel 10 are sequentially driven. Note that each row counter 122 row decoder 13. The drive circuit 14 constitutes a row drive circuit 15.

Further, reference numeral 16 denotes a scanning circuit consisting of an m-ary counter, a decoder, etc. which inputs the pulse φ from the hexadecimal counter 11, and this scanning circuit 16 uses the scanning output from each pattern signal generation circuit described later. There are many types that sequentially read out pattern signals.

17. 18 and 19 are red, green, and blue pattern signal generation circuits that generate any pattern signal corresponding to the pattern to be displayed on the IJ display panel 1. These pattern signal generation circuits 17 ~19 is
Each LED 211~2nm, 311~ arranged on the matrix display panel 1 by the scanning output from the scanning circuit 16.
3. An arbitrary pattern signal is sequentially generated for each row corresponding to nm and 4u to 4 nm.

In this case, each of the pattern signal generation circuits 17 to 19 is a normal matrix board having input terminals x1 to xn in X rows and output terminals y1'')'m in column Y, which correspond to the first column and row of the matrix display panel 1. 20 to 22, and these input terminals x1 to xn are to be sequentially scanned by the scanning output of the scanning circuit 16.
Output the pattern signal set in each row to terminals y~ym
It is configured to be removed.

In addition, 30 is the above-mentioned matrix) Three color red signals R1-Rm, green signals 01-Gm and blue signals B1-Bm synchronized with the pulse φ are used as color information to be displayed on the IJ display panel 1.
This input circuit 3 is an input circuit to which input is time-divided.
0 is an OR circuit 31r with m inputs.

It is composed of 31f and 31b. Reference numeral 32 inputs the time-divided red signal R2, green signal G, and blue signal B input through each of the OR circuits 31r to 31b, and based on these color information, a red signal having a duty of 1/integer of the number of the combined colors. R2 is a color signal creation circuit that creates a green signal G and a blue signal B, respectively. When a signal of one color is inputted as color information, this color signal creation circuit 32 converts the color signal of duty 1 into two colors. When a combination is used, a color signal with a duty of μ is created, and when a combination of three colors is used, a color signal with a duty of 1/3 is created. A specific example thereof is shown in FIG. Here, 33 decodes the red signal R2 green signal G and blue signal B input as color signals from each of the OR circuits 31r to 31b.
This decoder 33 is a BCD decoder, and if the high level of each color signal is H'' and the low level is 11L)I, these red signal R1 green signal Table 1 34 calculates the pulse φ of the hexadecimal counter 11 for a long time. A BCD decoder is used to decode the pulse, and each output terminal 0a-Of outputs a repetitive pulse having a duty of 2, as shown in FIG. 3(a) to (f). 35 is a combination of pulses from the BCDf coder 34 to each LED 2 to 4 of the matrix display panel 1.
The OR circuit 35a is a combinational circuit consisting of OR circuits 35a to 35f for creating a signal having a predetermined duty to select and drive the pulses obtained at each output terminal On, Oc, and Od of the BcD decoder 34. Similarly, the OR circuit 35b inputs the pulses of the output terminals Ob, Od, and Of, respectively.
5a and 35b are AND gates 36d of a gate circuit 36, which will be described later for duty-dedicated pulses when two colors are combined;
Input to 36f, 36h, 36e, 36J36j, respectively. The OR circuit 35c is the same as each of the OR circuits 35a.
The OR output of + 35 b is input, and the pulse of duty 1 at the time of one color is input to 36 a, 36 b, and 36 c. Further, the OR circuit 35d receives pulses from the output terminals oa and Od of the BCD decoder 34, the OR circuit 35e receives pulses from the output terminals ob and Od, and the OR circuit 35f receives pulses from the output terminals Oc and Of. Then, ``These OR circuits 35d~3
5f is for inputting pulses of duty 2 to each (and goo) 36j to 36t when three colors are combined. Reference numeral 36 denotes AND gates 36a to 36t for selecting pulses of a predetermined duty generated from the combinational circuit 35 based on the decoded output of the BCD decoder 33.
37 is an OR circuit group consisting of OR circuits 37r, 37F, and 37b that take out the outputs of each ant game (36a to 36t) selected by the gate circuit 3G. -) 36a, 3
6d, 361 and 36j, the OR circuit 37b receives the outputs of AND gates 3Gb, 36e, 36f and 36k, and the OR circuit 37b receives the outputs of AND gates 3Gb, 36e, 36f and 36k.
The outputs of 36r, 36h, and 36t are respectively input, and these OR circuits 37r to 37b provide one color, two colors of multicolor information.
A red signal R, a green signal G, and a blue signal B each having a duty of 1/integer according to the color or the combination of three colors are taken out.

On the other hand, in FIG. 1, reference numeral 41 indicates the color signal generation circuit 32.
The red signal R, the green signal G, and the blue signal B created by the pattern generation circuits 17 to 19 selectively control the red signal R9, the green signal G, and the blue signal B, respectively, according to the pattern signals generated from the pattern generation circuits 17 to 19, and display them on the matrix display panel 1 based on the selected color signals. Arranged 3
Color LE0211~2nm, 31? This is a selection drive circuit that drives −3 nm and 411 to 4 nm. This selection drive circuit 41 is connected to column selection lines Yrl to Yrm of the matrix display panel 1.

Consisting of AND gates 421-42m, 431-43m and 441-44m connected to Yf1-Yfm and Ybl-Ybm, respectively, these AND gates 4
One input side of 21-42m, 431-43m, and 441-44m is connected to the output side of OR circuit 37r, 379', and 37b, respectively. The other input sides of the AND gates 421 to 42m are connected to the output terminals y1 to ym of the matrix board 20, and the input sides of the AND gates 431 to 43m are connected to the output terminals y1 to ym of the matrix board 21, respectively. 441-44
The input side of \m is each output terminal y1 of the matrix port 22
~ym are connected to each other. Note that 50 is a protection circuit consisting of a current limiting resistor 51 inserted between the selection drive circuit 41 and each column selection line of the matrix display channel 1.

Next, the operation of the above embodiment will be explained. Here, for convenience, the pattern to be displayed is divided into three zones, one zone is colored red, another zone is colored a mixture of red and green, and yet another zone is colored red, green, and blue. The case of displaying multiple colors using white in combination will be explained.0 And, as shown in the figure, the matrix node 20 of the red pattern signal generation circuit 17 has an input terminal x1 for each row.
Boards 25 (indicated by circles) are set at all intersections between ~ and k % m column output terminal Vk”
The board 25 is connected to the intersection with ""jm, and the matrix node 22 of the blue pattern signal generation circuit 19 has input terminals x1 to xn in each row and output terminals yz"'-ym in the L"m column.
It is assumed that the boards 25 are set at the intersections with the .

Thus, the clock pulses generated from the clock generator 10 are counted by the hexadecimal counter 11, and the pulses φ
is input to the row decoder 13 (and also to the scanning circuit 16) via the row counter 12, and the decoded output of the row decoder 13 turns the transistors 141 to 14mft11M7 of the drive circuit 14 on [Ih1-
The row selection lines X1 to Xn of the matrix display panel 1 are sequentially scanned, and the scanning output of the scanning circuit 16 in synchronization with this scanning is used to generate each pattern signal generation circuit 17.
.about.19 matrix ports 20 to 22 are read out and scanned row by row.

Therefore, pattern signals corresponding to preset boards 25 are sequentially read out row by row from the output terminals y1 to ym of each of the matrix ports 20 to 22, and the selection drive circuit 4
1 each and gate 421-42m.

It is input to 431-43m and 441-44m, respectively, and turns them on. At this time, for example, 1 is read out from the output terminals y1 to ym of the matrix node 20.
The pattern signal of the row is the AND gate 421-42m.
are sequentially turned on, and the output terminals yk and ym of the IJ board 21 are turned on and the output terminals y and j of the IJ board 21 are connected to the AND gate 43.
~43m to the output terminal of matrix pod 22 y z
The pattern signal for ry m is the AND gate 44t~
44m are respectively turned on.

Therefore, as color information, red signals R1 to Rm, 1 signal 01
%Gm and green signal B1%Bm, first red signal R1
~R1 (When only -1 is input to the color signal generation circuit 32 through the OR circuit 31r of the input circuit 30, the BCD decoder 33 of this color signal generation circuit 32 converts the input red signal R into I
tHII, green signal G as ``ILI+, green signal B as N+:
T, the output ■ becomes 'H' as shown in Table 1, and this output is input to the AND gate 36a of the gate circuit 36.The AND gate 36a is then connected to each output terminal Oa to Oa of the ECD decoder 34. Figure 3(a) obtained in Of
The pulse shown in ~(f) is the OR circuit 35 of the combinational circuit 35.
Since the signals are input sequentially through a to 35c, the output is a continuous duty 1 pulse. Therefore, this pulse is sent to the column selection line Yrx of the matrix display panel 1 through the OR circuit 37r and the selection drive circuit 41, and is sent to the column selection line Yrx of the matrix display panel 1, driving the LED 211 to emit light. LE0212~'l 1k-1 are sequentially driven based on ~Rk-1. Next, when the red signals Rk to Rz-t and the green signals Gk-Gl, -1 are input to the BCD decoder 33 through the OR circuits 31r+31r, the decoder 33 sets the red signal R to "H".

The green signal G is 'H', the blue signal B is tTl, the output ■ is 1'' as shown in Table 1, and the output ■ is the gate circuit 3.
6 Antogame) is input to 36d and 36e.

Then, in this ant game) 36d, the pulses shown in FIGS.
5a, and the AND gate 36e also receives the third signal obtained from the output terminals Ob, Od and Of.
Since the pulses in Figure (b) l (d) and (f) are input through the OR circuit 35b, these AND gates 3
5d, 3(io) alternately input pulses from the BCD decoder 34 to OR circuits 37r and 37f.

Therefore, these pulses pass through the gates 42 and 43k of the selection drive circuit 41 and are sent to the column selection lines Yrlk and Yf'zk of the TRIX display panel 1, and drive each LED 2xk and 3tk to emit light at duty A. Then, in the same manner, the above red signals Rk+1 to Ft
t-1. Green signals Gk+1 to Gt-s are sequentially driven.

Furthermore, as color information, red signal RL"-Rm, green signal G
When t=G m and the blue signal B t-B m are input to the BCD decoder 33 through the OR circuits '31r, 3N' and 31b, this decoder 33 inputs the input red signal R to 1'' and the green signal G to 6H. ”, Green signal B 6H”
Then, as shown in Table 1, the output (2) is I ('', and the output is the ant game of the gate circuit 36) 36j.

36 and 36t. Then, this AND gate 36j has an output terminal C)a of the BCD decoder 34.
, Od are inputted through the OR circuit 35d, and each ant game is inputted through the OR circuit 35d.
) 36 and 31 have output terminals Ob and Oe as shown in Figure 3 (
The pulses shown in b) and (,) are input through the OR circuit 35e, and the pulses shown in FIG.
The pulses shown in c) and (f) are input through the OR circuit 35f. Therefore, these anime games) 36r
-31 sequentially input pulses from the BCD decoder 34 to OR circuits 37r-37b. Therefore, these pulses are applied to the AND gates 42t and 43t of the selection drive circuit 41.
and 441 to the column selection lines Yrst, Yf11- and Ybxt of the matrix display panel 1, and each LED 2t43xt and 41t is driven to emit light at duty 2, and the above red signal Rt-1-
1~Rm, each LED 21t+1~21m based on the green signal (:, J, +s-Gm and the green signal Bt+1~Bm,
31t+1 to 31m and 411+s to 41m are sequentially driven.

As described above, according to the above embodiment, when the rows of the matrix display panel 1 are sequentially scanned by the scanning signal of the drive circuit 15, the pattern signal corresponding to the pattern to be displayed is generated from each of the pattern signal generation circuits 11 to 19. are read out row by row and selected by the pattern signals of the AND gates 421 to 4m, 431 to 43m, and 441 to 44 of the selection drive circuit 41.
Turn off each m in turn.

Red signals R1xRm, 1 signals 01 to Gm and blue signals B1 are turned off and synchronized with each pattern signal.
By selecting ~Bm, the LEDs 2111-2n are arranged in the matrix display panel 1 by color signals having a duty that is an integer fraction of the number of combinations of the red signal R2, green signal G, and blue signal B.

Light emission can be driven by sequentially scanning 311 to 3 nm and 411 to 4 nm row by row. Therefore, one zone of the pattern to be displayed on the matrix display panel 1 is displayed in red by LE0211 to 2nk-z, and another zone is displayed by LED 21k to 2nL-1.
It is displayed in a mixed color by a combination of two colors: red of LED 3xk~3nA-1 and green of LED 3xk~3nA-1, and another zone is displayed with red color of LED 21t~2nm and green of LED 31t.
It can be displayed in white by a combination of three colors: green of ~3 nm and blue of LED 411~4 nm. Furthermore, an arbitrary pattern can be displayed in multiple colors according to the pattern signals set in each of the pattern signal generation circuits 17 to 19.

In the above embodiment, the pattern to be displayed is divided into three zones and each zone is displayed in multiple colors. However, each pattern signal generation circuit can generate pattern signals such as arbitrary characters and symbols. By generating this, it is also possible to display arbitrary characters or symbols in multiple colors.

In this case, each pattern signal generation circuit may be a combination of a processor and a RAM (random access memory) in addition to the matrix board.

〔Effect of the invention〕

As explained above, according to the multicolor display device of the present invention,
LEDs of three different colors are used as unit elements, and these three
When driving a matrix display panel in which colored LEDs are arranged in a matrix, each LED is driven to emit light using a color signal having a duty of one integer fraction of the number of combined colors of color information. This has effects such as being able to make the brightness of displayed colors uniform and displaying arbitrary patterns in multiple colors.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing a circuit configuration of a multicolor display device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a specific example of the color signal generation circuit of FIG. 1. , and FIGS. 3(a) to (f) are timing charts obtained at the output terminal of the BCD decoder to explain the operation of the color signal generation circuit of FIG. 2. 1.φ fist matrix display panel, 211~2nm...
・-Red LED, 311~3nm・・Green L
EI), 411~4ny11 m m a m Blue LED, 10・Fist work・Clock generator, 11...-6
Advance counter, 15...drive circuit, 16...scanning circuit, 17-19...pattern signal generation circuit, 30
... Input circuit, 32 ... Color signal creation circuit, 41
...Selection drive circuit. Patent applicant: Koito Seisakusho Co., Ltd. Agent: Masaki Yamakawa (and one other person)

Claims (1)

[Claims] LEDs of three different colors are used as unit elements, and these three
A matrix display panel in which colored LEDs are arranged in a matrix, and an arbitrary pattern signal is generated for each row of the LEDs arranged on the matrix display panel in accordance with the pattern to be displayed on the matrix display panel. A color pattern signal generation circuit, a color signal generation circuit that generates color signals of three colors each having a duty of one integer of the number of colors to be combined based on color information, and a color signal generation circuit created from this color signal generation circuit. The color signals of the three colors are selected according to the pattern signals generated from each of the pattern signal generation circuits, and the rows of LEDs arranged on the matrix display panel are respectively selected based on the selected color signals. A selection drive circuit that sequentially drives each LED, and a drive circuit that sequentially drives each row of LEDs arranged on the matrix display panel in synchronization with each pattern signal generated by the three color pattern signal generation circuit. A multicolor display device characterized in that an arbitrary pattern is displayed in multiple colors based on color information.