JPS60141019A - Logic circuit - Google Patents
Logic circuitInfo
- Publication number
- JPS60141019A JPS60141019A JP58247022A JP24702283A JPS60141019A JP S60141019 A JPS60141019 A JP S60141019A JP 58247022 A JP58247022 A JP 58247022A JP 24702283 A JP24702283 A JP 24702283A JP S60141019 A JPS60141019 A JP S60141019A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- logic circuit
- application terminal
- drive current
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（４支術分里１・）
本発明は論理回路、特に騎動市流の選択しゃ断がｄＪ能
な電流切換型の論理回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit, and particularly to a current switching type logic circuit that is capable of selectively shutting off the circuit in a dynamic manner.
（従来技術）
従来のこの神の論理回路の一例を示す第１図により概略
説明する。従来の論理回路には、ベースを信号印加端子
１０とし、コレクタが負荷抵抗ＲＩケ介して第ｌの箱１
辻源端子１１に接続された人力トランジスタ１と、エミ
ッタがか１記人力トランジスタ１のエミッタに共通接続
され、コレクタが負前抵抗几２を介１７て弔ｌの市、圧
源端子１１に接続され、ベースを基準電圧印加端子１５
とＪ−る基準トランジスタ２と、コレクタが口ｊ１記共
通接続きれたエミッタに接続され、エミッタが抵抗几３
を介して第２のｍ）：ｌ−源端子１２に接続され、ペー
スケ定宙圧印加節１．子１６とする８１ｔ ＊ＪＪ電流
規定トランジスタ３で構成され、入力トランジスタ１の
コレクタから否定論理出力を出力端子１３に収り出し、
一方ｆｉ’、ｌ ６Ｊトランジスタ２のコレクタから肯
定論理出力を出力端子１４に収り出す電流切換型論理回
路が月１いられている。(Prior Art) An overview will be given with reference to FIG. 1, which shows an example of a conventional logic circuit. In a conventional logic circuit, the base is the signal application terminal 10, and the collector is connected to the lth box 1 through the load resistor RI.
The human-powered transistor 1 is connected to the power source terminal 11, and the emitter is commonly connected to the emitter of the human-powered transistor 1, and the collector is connected to the pressure source terminal 11 through the negative front resistor 2 17. and connect the base to the reference voltage application terminal 15
A reference transistor 2 is connected to the reference transistor 2, the collector of which is connected to the commonly connected emitter, and the emitter of which is connected to the resistor 3.
is connected to the second m):l source terminal 12 through the paceke constant air pressure application node 1. 81t *JJ current regulating transistor 3 as the child 16, outputs a negative logic output from the collector of the input transistor 1 to the output terminal 13,
On the other hand, a current switching type logic circuit that outputs a positive logic output from the collector of the fi', l6J transistor 2 to the output terminal 14 is installed once a month.
この回路において、帥記電圧源端子１２の電位を基準に
した定電圧印加端子１６の電“位ｋＶ６２とし、離動電
流規定トランジスタ３のエミッタ・ベース間のｌ１ｌｌ
−１方向笥、辻’ｋＶｐとすると、抵抗几３ に流、れ
る離動宵、流ｌは
１も３
で表わされる。また、電ｊ土源端子１１．１２間の電圧
をＶ１２とすると、この駆動電流■による消費電力Ｐは
Ｐ＝ｌ−Ｖ１２ ・・・・・・・・・・・・・・・ （
２）となり、この電力Ｐが論理状態のいか心にかかわら
ず常に消費されることになる。すなわち、このような電
流切換型論理（ロ）路では、論理状態のいかんにかかわ
らず常に一定の電流が流れるので、被駆動回路が信号を
必要としない場合でも常に一定の電力全無駄に消費する
欠点があった。この消費電力の増大は集積回路チップの
温度上昇を招き、製品の故障率や内部配線の寿命に悪影
響を与えることになり、妬集積化が進むにつれてこれは
ますます重大な欠点になってきた。In this circuit, the potential of the constant voltage application terminal 16 is set to kV62 with reference to the potential of the main voltage source terminal 12, and the l1ll between the emitter and the base of the separation current regulating transistor 3 is
-1 direction, if it is tsuji'kVp, then the flow 1 flowing into the resistance 3 is expressed as 3. Also, if the voltage between the power source terminals 11 and 12 is V12, the power consumption P due to this drive current ① is P=l−V12 ・・・・・・・・・・・・・・・ (
2), and this power P is always consumed regardless of the logic state. In other words, in such a current-switching logic circuit, a constant current always flows regardless of the logic state, so a constant amount of power is always wasted even when the driven circuit does not require a signal. There were drawbacks. This increase in power consumption causes an increase in the temperature of the integrated circuit chip, which adversely affects the failure rate of the product and the lifespan of the internal wiring, and this has become an increasingly serious drawback as integration increases.
（発明の目的）
本発明の目的は、被駆動回路が信号を必要としない論理
回路の駆動電流を選択的にしゃ断することにより上記欠
点を解決し、無駄な消費電力を削減できる論理回路を提
供することにある。(Object of the Invention) An object of the present invention is to provide a logic circuit in which the driven circuit selectively cuts off the drive current of a logic circuit that does not require a signal, thereby solving the above drawbacks and reducing unnecessary power consumption. It's about doing.
（発明の構成）
本発明によれば、ベースを４８号印加端子としコレクタ
が直接または第１の抵抗を介して第１の電圧源に接続さ
れた第１のバイポーラトランジスタと、エミッタがｈ共
架１のバイポーラトランジスタのエミッタに接続される
と共に電流規定回路全弁して第２の電圧源に接続されコ
レクタが直接または第２の抵抗を介して前記第ｌの電圧
源に接続烙れベースが基ｒ＄電圧印加端子に接続された
第２のバイポーラトランジスタを含んで成り前記第１あ
るいは第２のバイポーラトランジスタのコレクタ電位変
化を出力として収り出す論理回路においで、前記電流規
定回路にゲート金制佃１信号印加端子とする第ｌの電界
効果トランジスタを直列に挿入したこと全特徴とする論
理回路が得られ、またｎｉｉ記論理回路において、第１
あるいは第２のバイポーラトランジスタのコレクタ電位
変化をエミッタホロワ回路全弁して収り出す論理金儲え
、ロ１１記エミッタホロワ回路にゲートを制御信号印加
端子と３−る第２の電界効果トランジスタを直列に挿入
したこと全特徴とする論理回路が得られる。(Structure of the Invention) According to the present invention, the first bipolar transistor whose base is a No. 48 application terminal and whose collector is connected to a first voltage source directly or via a first resistor, and whose emitter is The base is connected to the emitter of the first bipolar transistor, and is connected to the second voltage source through the entire current regulating circuit, and the collector is connected to the first voltage source directly or through a second resistor. In a logic circuit that includes a second bipolar transistor connected to the r$ voltage application terminal and outputs a change in the collector potential of the first or second bipolar transistor as an output, the current regulating circuit is provided with a gate-feed control. A logic circuit is obtained in which the first field effect transistor serving as the first signal application terminal is inserted in series.
Alternatively, the collector potential change of the second bipolar transistor can be collected by all the emitter follower circuits to make logical money, and the second field effect transistor with the gate and the control signal application terminal in the emitter follower circuit described in B11 is connected in series. A logic circuit with all the features inserted is obtained.
（実施例）
へに第２図および第３図を用いて本発明にりいて説明す
る。第２図および第３図はそれぞれ本発明の第１および
第２の実施例を示す回路図である。(Example) The present invention will now be described with reference to FIGS. 2 and 3. FIGS. 2 and 3 are circuit diagrams showing first and second embodiments of the present invention, respectively.
第２図において、従来の論理（ロ）路と同じ構成要件に
は第１図と同じ判号葡付しである。第ｌの実施例は従来
例（第１図に図示）の駆動電流規定回路にゲートを制御
信号印加端子１７と接続した電界効果トランジスタ（以
下ＦＥＴ）４を直列に挿入したものである。すなわち、
ＦＥＴ４のドレイ／は抵抗Ｒａ”ｒ介して駆動電流規定
トランジスタ３のエミッタと接続され、ソースは第２の
電Ｆト源端子１２と接続される。この論理回路において
、Ｆ Ｅ ’ｌ’ ４の纒通抵抗を１（ＣＩとし、Ｒ′
３の抵抗値をＲ，７−Ｒ３−Ｒの ・・・・・・・・・
・・・・・・ （３）と設定すれば、Ｆ Ｅ ’］”
４が導通状態では、この回路の駆動筒、流は第１図の論
理回路と全く等しくなり、スイッチング特性等の特性も
全く等しくなる。一方、Ｆ’ Ｅ ’Ｉ’ ４がしゃ断
状態ではこの回路には駆動゛電流が全く流れないので、
ｖｎｎ電電力零になる。このことから各論理条件で不必
要な論理回路が存在すれば、それを選択的にしゃ断する
ことによりｌｔｌ費電力を目１１減できることがイフか
る。In FIG. 2, the same constituent elements as in the conventional logic circuit are labeled with the same symbols as in FIG. 1. In the first embodiment, a field effect transistor (hereinafter referred to as FET) 4 having a gate connected to a control signal application terminal 17 is inserted in series in the drive current regulating circuit of the conventional example (shown in FIG. 1). That is,
The drain of the FET 4 is connected to the emitter of the drive current regulating transistor 3 via a resistor Ra"r, and the source is connected to the second FET source terminal 12. In this logic circuit, the FET 'l'4's The thread resistance is 1 (CI, R'
The resistance value of 3 is R, 7-R3-R...
・・・・・・ If you set (3), FE']”
4 is in a conductive state, the drive tube and flow of this circuit are exactly the same as those of the logic circuit shown in FIG. 1, and the switching characteristics and other characteristics are also exactly the same. On the other hand, when F' E 'I' 4 is cut off, no drive current flows through this circuit, so
vnn electric power becomes zero. From this, it can be seen that if there is an unnecessary logic circuit under each logic condition, the LTL power consumption can be reduced by 11 times by selectively cutting it off.
このｒ＋Ｊ＊電力の削減は高集積化には非常に有利あり
、特に単４Ｓｔ論理回路の消費電力が大きい電流切換型
論理回路にとっては非常に効果が大きい。This reduction in r+J* power is very advantageous for high integration, and is particularly effective for current switching type logic circuits in which the power consumption of AAA St logic circuits is large.
次に第３図において、弗２の実施例は第１の実り５．６
のベースはそれぞれ入力トランジスタ１゜基準トランジ
スタ２のコレクタと接続され、コレクタは共に第１の電
圧源端子１１と接続され、エミッタはそれぞれ出力端子
１３．１４に接続されると共に抵抗１−Ｌ４，１（，５
ｉ介してＦＥＴ７のドレインに接続される。またＦＥＴ
７のゲートは制御信号印加端子１８と接続され、ソース
は第２の電圧源端子］２と接続される。なお第２の実施
例における厚木的な論理動作は１１１述の第１の実施例
の場合と金く同じであり、またＦＥＴ４，７のしゃ断状
態における消費電力の削減についても第１の実施例の場
合と全く同じ効果が得られる。Next, in Figure 3, the example of 弗2 is the first fruit 5.6
The bases of the input transistors 1 and 2 are respectively connected to the collectors of the input transistor 1 and the reference transistor 2, the collectors are both connected to the first voltage source terminal 11, and the emitters are connected to the output terminals 13 and 14, respectively, and the resistors 1-L4, 1 (,5
It is connected to the drain of FET7 via i. Also FET
The gate of 7 is connected to the control signal application terminal 18, and the source is connected to the second voltage source terminal]2. Note that the Atsugi logic operation in the second embodiment is exactly the same as that in the first embodiment described in 111, and the reduction in power consumption in the cut-off state of FETs 4 and 7 is also the same as in the first embodiment. Exactly the same effect can be obtained.
ｉ＋ ｉ 、弔２の実施例は、本発明２制限するもので
はない。すなわち特１−拍求の軛囲第（ＩＬ（２）項記
載の論理回路には第１．弔２の実施例の神神の変形（例
えば負荷抵抗）ｔ、、１４ｚの抵抗１直ケ零にしたりＦ
Ｅ’Ｌ’４．７のそれぞれのソース、ドレインの接続を
通にするなど）が掲えられ、これら変形にも本発明に４
１用できることは明らかである。The example of i+i and 弔2 is not intended to limit the present invention. In other words, the logic circuit described in Section 1-IL(2) has a modification (for example, a load resistance) of the god of the embodiment 2 (for example, a load resistance) t, Make it F
E'L'4.7), such as passing the connection between the source and drain of each of the
It is clear that it can be used for one purpose.
（発明の効−！Ｉ：）
本発明の論理回路によれば、電界効果トランジスタのケ
ートに印加される制御信号によ！７駆動電流ケ選択的に
しゃ［υ丁することが−ａＪ能なので、被翔匹動回路が
信号を必要としない場合には駆動電流をしゃ断すること
によって無駄な／１８１費電力を無くし、消費電力の削
減が図られるという効果が生じ、特に論理回路光１こり
の消費電力が大きい電流切換型論理回路の高集積化にと
って（伐極めて不ｊ効である。(Effects of the Invention! I:) According to the logic circuit of the present invention, the control signal applied to the gate of the field effect transistor! 7. Since it is possible to selectively shut off the drive current, if the driven circuit does not require a signal, the drive current is cut off to eliminate wasted power and reduce power consumption. This has the effect of reducing power consumption, which is particularly ineffective for high integration of current-switching logic circuits, which consume a large amount of power per logic circuit.
９Ｆ４１図は従来の論理回路の一例を示す回路図、第２
図および第３図はそれぞれ本発明の論理回路の第ｌおよ
び＠２の実施例を示す１用務図である。
図において、■・・・・・・入力トランジスタ、２・・
・・・・シ、（準トランジスタ、３・・・・・・駆動電
流規定トランジスタ、４．７・・・・・・電界効果トラ
ンジスタ（ＦＥＴ）、５．６・・・・・・バイポーラト
ランジスタ、ｌＯ・・・・・・信号印加端子、１１．１
２・・・・・・電圧ｆ＃節。子、１３．１４・・・・・
・出力端子、１５・・・・・・＆準電圧印加端子、１６
・・・・・・定電圧印加端子、１７，１８・・・・・・
側御信号印加端子、■８０．．・・駆動電流、Ｒ□、１
−Ｌ２・・・・・・負荷抵抗、Ｒ３、ｔ−ｔ３′ｌ几４
．几５・・・・・・抵抗、Ｖ１２・・・・・・電圧源端
子開型５圧、Ｖ６２・・・・・・定電圧印加端子電位、
■Ｆ・・・・・・エミッタ・ペース間１１１目方向１圧
。
第１図
ネ ２ 圀
／ｌFigure 9F41 is a circuit diagram showing an example of a conventional logic circuit.
3 and 3 are diagrams showing the first and second embodiments of the logic circuit of the present invention, respectively. In the figure, ■... Input transistor, 2...
. . . (quasi transistor, 3. . . Drive current regulating transistor, 4.7 . . . Field effect transistor (FET), 5.6 . . . Bipolar transistor, lO... Signal application terminal, 11.1
2...Voltage f# node. Child, 13.14...
・Output terminal, 15... & quasi-voltage application terminal, 16
...... Constant voltage application terminal, 17, 18...
Side control signal application terminal, ■80. ．．・・Drive current, R□, 1
-L2...Load resistance, R3, t-t3'l几4
．．几5... Resistance, V12... Voltage source terminal open type 5 voltage, V62... Constant voltage application terminal potential,
■F... 1 pressure in the 111st direction between emitter and pace. Figure 1 Ne 2 area/l
Claims (1)
は第ｌの抵抗を介して第ｌの電圧源に接続された第ｌの
バイポーラトランジスタと、エミッタが０１記第１のバ
イポーラトランジスタのエミッタに接続されると共に市
流蜆定回路ケ介して第２の市圧汎１に接続されコレクタ
が直接または第２の抵抗ケ介して前記＄１の電圧源に接
続きれベースが基ｒ＄電圧印加端子に接続された第２の
バイポーラトランジスタを食上で成り前記第１あるいは
第２のパイポー２トランジスタのコレクタ電位変化を出
力としてＪ１！ｉ！り出す論理１す回路において、前記
電血規定回路にゲートを制１ｌｌＩ信号印加端子とする
第１の電界効果トランジスタを部列に挿入したことを特
徴とする論理回路。 （２、特許請求の範囲第（１）項記戦の論理回路におい
て、第１あるいは第２のバイポーラトランジスタのコレ
クタ電位変化全エミッタホロワ回路を介して取り出す論
理を備え、拘１１記エミッタホロワ回路にゲートを制御
信号印加端子とする第２の電界効果トランジスタを直列
に押入したこと全特徴とする論理回路。(1) A first bipolar transistor whose base is a signal application terminal and whose collector is connected to a first voltage source directly or via a first resistor, and whose emitter is connected to the emitter of the first bipolar transistor 01. The collector is connected to the voltage source of $1 directly or via the second resistor, and the base is connected to the base r$ voltage application terminal. J1! i! 1. A logic circuit which is characterized in that a first field effect transistor having a gate as a control signal application terminal is inserted in a column of the electroblood regulation circuit. (2. The logic circuit as set forth in claim (1) is provided with a logic for extracting the collector potential change of the first or second bipolar transistor through the entire emitter follower circuit, and a gate is provided in the emitter follower circuit as set forth in claim 11. A logic circuit characterized in that a second field effect transistor serving as a control signal application terminal is inserted in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58247022A JPS60141019A (en) | 1983-12-28 | 1983-12-28 | Logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58247022A JPS60141019A (en) | 1983-12-28 | 1983-12-28 | Logic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60141019A true JPS60141019A (en) | 1985-07-26 |
Family
ID=17157235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58247022A Pending JPS60141019A (en) | 1983-12-28 | 1983-12-28 | Logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60141019A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61244120A (en) * | 1985-04-23 | 1986-10-30 | Nippon Telegr & Teleph Corp <Ntt> | Detecting and outputting circuit for logical signal |
| EP0207159A1 (en) * | 1984-11-12 | 1987-01-07 | Fanuc Ltd. | Voltage comparator of a type of low power comsumption |
| WO1989002677A1 (en) * | 1987-09-17 | 1989-03-23 | Fujitsu Limited | Emitter follower circuit |
| EP0416323A2 (en) * | 1989-09-04 | 1991-03-13 | Siemens Aktiengesellschaft | Signal level converter |
| EP0564390A2 (en) * | 1992-04-01 | 1993-10-06 | International Business Machines Corporation | High-speed bipolar-field effect transistor (BI-FET) circuit |
-
1983
- 1983-12-28 JP JP58247022A patent/JPS60141019A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0207159A1 (en) * | 1984-11-12 | 1987-01-07 | Fanuc Ltd. | Voltage comparator of a type of low power comsumption |
| JPS61244120A (en) * | 1985-04-23 | 1986-10-30 | Nippon Telegr & Teleph Corp <Ntt> | Detecting and outputting circuit for logical signal |
| JPH042009B2 (en) * | 1985-04-23 | 1992-01-16 | ||
| WO1989002677A1 (en) * | 1987-09-17 | 1989-03-23 | Fujitsu Limited | Emitter follower circuit |
| US4958094A (en) * | 1987-09-17 | 1990-09-18 | Fujitsu Limited | Emitter follower circuit with MOSFET |
| EP0416323A2 (en) * | 1989-09-04 | 1991-03-13 | Siemens Aktiengesellschaft | Signal level converter |
| US5122689A (en) * | 1989-09-04 | 1992-06-16 | Siemens Aktiengesellschaft | Cmos to ecl/cml level converter |
| EP0564390A2 (en) * | 1992-04-01 | 1993-10-06 | International Business Machines Corporation | High-speed bipolar-field effect transistor (BI-FET) circuit |
| EP0564390A3 (en) * | 1992-04-01 | 1994-03-09 | Ibm |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4412139A (en) | Integrated MOS driver stage with a large output signal ratio | |
| JP2559032B2 (en) | Differential amplifier circuit | |
| US4612458A (en) | Merged PMOS/bipolar logic circuits | |
| JPS60141019A (en) | Logic circuit | |
| JPS61154312A (en) | Drive circuit | |
| JPS6155810B2 (en) | ||
| KR0165986B1 (en) | BiCMOS logic circuit | |
| KR940005975B1 (en) | Output circuit | |
| JPS60236322A (en) | Mos transistor circuit | |
| JPS63266921A (en) | Power-on reset signal generating circuit | |
| JPH01154620A (en) | Semiconductor integrated circuit | |
| US4409561A (en) | Operational amplifier output stage driven by a single ended gain stage | |
| JP2636766B2 (en) | Logic circuit | |
| JP2730098B2 (en) | Semiconductor integrated device | |
| JP2541289B2 (en) | Output circuit | |
| JPH0650816B2 (en) | Gate circuit | |
| JPS61296819A (en) | Composite switch element circuit | |
| JPS6341451B2 (en) | ||
| JP3287286B2 (en) | Reference voltage generation circuit | |
| JPS6367817A (en) | Integrated circuit | |
| JPH025613A (en) | Three-state output circuit | |
| JPS61113319A (en) | Holding circuit | |
| JPH03160818A (en) | Switching circuit for electric characteristic | |
| JPH0821843B2 (en) | Output buffer circuit | |
| JPS61157024A (en) | Protection circuit of transistor |