JPS60134622A - Single phase static type j-k flip-flop circuit - Google Patents

Abstract

PURPOSE:To attain compatibility with TTL by adopting a specific circuit constitution comprising a dynamic loop and a static loop so as to decrease the number of components and simplify the constitution thereby providing a set/reset priority function. CONSTITUTION:The dynamic loop consists of unit bodies 31, 32, 33 and the static loop comprises units bodies 34, 35 and an MOS transistor (TR)36. In setting a J input signal and a K input signal both to a high level, the flip-flop circuit acts like a binary counter. In setting the J input signal to a high level and the K input signal to a low level, and in setting both the signals to a low level, and in setting the J input signal to a low level and the K input signal to a high level, the dynamic loop acts like a J-K flip-flop circuit. The dynamic holding state is held statically by the static loop. Through the constituting above, in setting a reset signal RESET and a set signal SET both to a high level, outputs signals Q, Q' go both to the high level and the reset/set priority type is attained.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention operates by a single-phase pulse signal, sets,
1-phase static type J- with reset priority function
Regarding frizzo flop circuits.

[Technical background of the invention]

Fig. 1 shows a conventional 1 system operated by a 1-phase pulse signal φ.
FIG. 2 is a circuit configuration diagram of a phase static type D flip-flop circuit. In this static type J-, the frizzo flop circuit is constructed by inserting a plurality of MOS transistors in series between the two electrodes of the power supply, that is, between the application point and the ground potential point, to form six unit circuits 11 to 16. Connect the output ends of two unit circuits 11 and 12 in common to form unit circuit 1.
3, the output terminal of this unit circuit 13 is connected to the input terminal of unit circuit 14, and further unit circuit 35.16 is connected to the input terminal of unit circuit 13.
The respective input and output terminals are connected by inverters 17 and 18, and the input terminals of both inverters 17 and 18 are connected to the output terminals of the unit circuits 12 and 13, and the output terminal of the unit circuit 14 and the ground potential are connected. A MOS transistor 19 (described later) is inserted between the M0
The dart of the S transistor 19 is connected to the output terminal of the unit circuit 13.

That is, in the unit circuit 11, three P-channel MO8 transistors lla, llb,
llc and two N-channel MOS) transistors
ld and lle are connected in series, and this P channel M0S transistor 110 and N channel MOS transistor lld
In the unit circuit 12, with the reading point as the output terminal, a P-channel MO8) transistor 11h, two P-channel MO8) transistors 12a, 12b and two N-channel MOS transistors 12c, 12d
' kUM series are connected, and the series connection point of P channel MO8) transistor 12b and N channel MOS transistor 12a is used as the output terminal. Therefore, the P-channel MOS transistor llh is shared by unit circuits 11 and 12. In the unit circuit 13, between VDD and GND, there are two P-channel MOS transistors 13h, 13b and two N-channel MOS transistors 13c, 1).
3df are connected in series, and the series connection point of the P-channel MO8) transistor 13b and the N-channel MOS transistor 13a is used as the output end. In the unit circuit 14, two P-channel MO8) transistors 1 are connected between VDD and GND.
4th, 14b and the N-channel MOS transistor 14c'ff are connected in series, and the I-column contact point of the P-channel MOS transistor 14b and the N-channel MOS transistor 14c is used as the output terminal.

And between the output terminal of the unit circuit 14 and GND,
Channel MOS) transistor 19 is connected.

In the unit circuit 15, two P-channel MO8) transistors 15a and 75 are connected between vDD and GND.
b and N channel MOS) transistors 150, 15
d are connected in series, and this P channel MO8) transistor 1
5b and the N-channel MOS) transistor 15o are connected in series, and the reading point is used as the output terminal. Two P-channel MO8s each between vDD and GND in the unit circuit 16)
transistors 16m, 16b and N-channel MOS)
The run rasters 16c and 16d are connected in series, and the series connection point of the P channel MO transistor 16b and the N channel MO transistor 16a is used as the output end. The signal A at the common output terminal of the unit circuits 11 and 12 is supplied to each gate of the P-channel MO transistor 13b and the N-channel MO transistor 13a of the unit circuit 13, and to the input terminal of the inverter 17. The above unit circuit 13
P channel MO8 of the signal B unit circuit 14 at the output end of
It is supplied to the input end of each dart inverter 18 of the range transistor 14b, the P-channel MO8 transistor 11b of the unit circuit 11, the ON-channel MOS transistor 12d of the unit circuit 12, and the N-channel MOS transistor 19. Signal CFi unit circuit 11 at the output end of the unit circuit 14
N-channel MOS) run raster 11e, unit circuit 1
2 P channel MO8) range meta 12a, unit circuit 1
30P channel MO8) transistor 13a.

P channel MO8) run raster 15a1 of unit circuit 16
N-channel MOS of unit circuit 16) transistor 16d
supplied to each dart. The output signal of the inverter 17 is supplied to each gate of the P-channel MOS transistor 15b and the N-channel MOS transistor 15c. Output signal of the above inverter 18 P channel MO8
) Transistor 16b and N-channel MOS) Supplied to each dart of transistor 16a. Furthermore, the J input signal is connected to the P channel MO8) transistor of the unit circuit 11.
The K input signal is supplied to each gate of the P-channel MOS transistor 12b and the N-channel MOS transistor 12c of the unit circuit 12 via the inverter 20. In addition, the 1-phase i4 pulse signal φ is the unit circuit 11 to 1.
6 P channel MO8) transistor lla, N channel MO8) transistor 1.9 d% P channel MOS transistor 14a, N channel MOS) range meta 14
c, , is supplied to each dart of N-channel MO8) transistor 15d and P-channel MO8) transistor 16th.

Next, the operation of the circuit configured as described above will be explained using the timing chart shown in FIG.

First, at the timing of t times, both the J input signal and the input signal are set to a high level (vDD level). At this time, φ is at a low level (GND level). Furthermore, assuming that signal B is at a low level at this time, MOS
) transistor 14b17- is turned on. At this time, since the MOS transistor 14a to which φ is input is also turned on, the signal C of the unit circuit 14 becomes at the cylinder level. When the signal C becomes high level, the MOS transistor Ile to which this signal C is input is not in the on state, and the MOS transistor Ild to which the J input signal, which is at a high level, is input is also in the on state.
Signal A becomes low level. When signal A becomes low level,
This signal A inputs the MOS) transistor 13b, but this MOS) transistor 13b1!
: MOS inserted between vDD)) Since high level signal C is input to transistor 13a, the output terminal of unit circuit 23 is cut off from both vDD and GND, but it becomes low level. A MOS to which the output signal of the inverter 18 that inverts the signal B input is input) run raster 16c
, MOS transistor J6d to which the signal C which is at a high level is input are both turned on, so the signal B is held at a low level by the unit circuit 16 during the t1 period when φ is at a low level. 18- It will happen.

Keno<? at the timing of t2 The pulse signal φ is inverted to high level. When φ becomes high level, this φ inputs MO
S) The transistor 14c is turned on, and the unit circuit 1
The signal cH of No. 4 is inverted to low level. When signal C is inverted and becomes low level, yikes! MOS that was on until )
The transistor 11e is turned off. Since φ is at a high level, the MOS transistor lla, which has been in an on state, is now in an off state and is cut off from both the output terminal of the unit circuit 1 and VDD and GND, but the level remains low until now. The MOS to which the output signal of the inverter 17 that inverts the signal A that is A is held at a low level by the unit circuit 15.

Furthermore, when the low level signals C and A are input to the MOS transistors 13a and 13b, both MO8)
The transistors 13h and 13b remain on, and the signal B of the unit circuit 13 is inverted to high level.

At the timing of t3 (the riz4 pulse signal φ is inverted to low level again. When φ becomes low level, the MOS to which this φ is input) is the run raster 11a, the MO to which the signal C is input.
S) A MOS to which the transistor 12h and the output signal of the inverter 20, which is at a low level, are input.) Each of the transistors 12b is turned on, and the signal A is inverted to the cylinder level.

When the signal A is inverted and becomes a high level, the MOS transistor 13b to which this signal A is input is not in an off state, and the MOS transistor 13d to which φ is input is also in an off state, but until now it has been at a high level. Signal Bvi-
MOS to which the inverting output signal of the inverter 18 is input
) Since both the MOS transistors 16° to which the transistor 16b1 φ is input are turned on, the signal B is held at a high level by the signal B unit circuit 16 during the period t8 when φ is at a low level. Further, when the signal B is at a high level, the MOS transistor 19 to which this signal B is input is turned on, and the signal C remains at a low level.

At timing 1, the pulse signal φ is inverted to high level. When φ becomes high level, this φ inputs MOS
) When the transistor 14c is not in the on state, the signal CFi continues to be at a lower level.

When signal C becomes low level, this signal C inputs MO
S) Transistor lle is turned off.

Furthermore, the MOS transistor Ile to which φ is input is also turned off, and the output terminal of unit circuit 1 is connected to vDD and GND.
It can be inferred from both that the output signal of the inverter 17 that inverts the signal A, which has been at a high level, is input to the MOS.) Run raster 15b, the MOS to which the signal C, which is at a low level, is input.) The transistor 1/ia Since both are on, the signal AFi unit circuit 15 is held at a high level during the ta period when φ is at a high level. When signal A is at a high level, the MOS transistor 13a to which this signal A is input is not in an on state, and the MOS transistor 13d to which φ is input is also in an on state, and signal B is at a low level. Invert.

At timing t6, the pulse signal φ is inverted to a lower level. When φ becomes low level, this φ inputs MOS
) Transistor 14h is not in the ON state, and the MOS transistor to which signal B, which is at a low level, is input.
4b is also turned on, so the signal C is inverted to high level. When the signal C becomes high level, the MOS transistor Ile to which this signal C is input is not turned on, and the MOS transistor 11d to which the J input signal is input is also turned on, and the signal A is inverted to low level. do. When signal A is inverted and becomes low level, this signal A inputs MO
S) The transistor 13a is in the off state, and the MOS transistor 13a is inputted with the signal C which is at a high level at this time.)
Since the transistor 13a is also turned off, the unit circuit 13
The output terminal of the transistor 16c is cut off from both VDD and GND, but the signal B' (MOS to which the output signal of the inverter 18 that inverts H is input), which has been at a low level, has become a high level. Since both the MOS transistors 16d to which the signal C is input are turned on, the signal B is held at a low level by the unit circuit 16 during the period t5 when φ is at a low level. In this state, the first timing 1. I'm back to this tl
If the period from tff to tff is one cycle, the same cycle will be repeated every time φ is reversed thereafter.

When both the J input signal and the 2 input signal are set to a high level in this way, the signal B becomes a 2-divided signal of φ. In other words, the above circuit operates as a binary counter.

Next, the operation when the J input signal is set to the cylinder level and the K input signal is set to the low level will be explained. First, when φ becomes high level at timing t6, this φ becomes the input M0S.
Transistor 14Q is turned on and signal C becomes low level.

When signal C becomes low level, this signal C inputs MO
S) The transistor Ile is not in the OFF state, and the MOS to which φ is input.) The transistor l1m is also in the OFF state, so the output terminal of the unit circuit 11 is cut off from both vDD and GND, but now 1 is at a high level. A MOS to which the output signal of the inverter 17 that inverts the signal A is input.
) MOS to which transistor 15b and signal C are input)
Both transistors 1.5a are in the on state, so φ
During the t6 period when A is at a high level, the signal A is held at a high level by the unit circuit 15. When the signal A is at a high level, the MOS transistor 13c to which this signal A is input
When the transistor 13d is turned on, the MOS transistor 13d to which φ is input is also turned on, and the coefficient B is inverted to a low level.

At the timing of tv, the pulse signal φ is inverted to a low level. When φ is inverted to low level, this φ inputs MO
S) The transistor 14m is turned on. At this time, since the signal B is at a low level, the MOS transistor 14b to which this signal B is input is also turned on, and the signal C is inverted to a high level. When the coefficient C is inverted and becomes high level, this signal C is input to the MOS transistor l.
le is turned on. At this time, since the M0S transistor 11du to which the @J input signal is input is in the on state, when the MO8) transistor lie is turned on, the signal A becomes low level. When the signal A becomes a low level, the MOS transistor 13a to which this signal A is input is turned off, and the MOS transistor 1 and 13a to which the signal C, which is at a high level, is input is also turned off. MOS to which the output coefficient of the inverter 18 that inverts the signal B, which has been at a low level until now, is input)
The transistor 16a is in the on state, and the MOS to which the signal C is input
) Since the transistor 16d is also turned on, the signal B is held at a low level by the unit circuit 16 for 19 periods during which φ is at a low level.

At timing t8, the pulse signal φ is again inverted to high level. When φ is inverted to a high level, the MOS transistor 14a inputted by this φ is turned on, and the signal C of the unit circuit 14 is inverted to low level. When the signal C is inverted and becomes a low level, the MOS transistor 11eFi to which this signal C is input is turned off. Furthermore, the MOS transistor llh to which φ is input is also turned off, and the output terminal of the unit circuit 11 is cut off from both VDD and GND. MOS transistor 15c to which the output signal is input and MOS transistor 15rl to which φ is input are both turned on, so the signal A is held at a low level by the unit circuit 15 during the t8 period when φ is at a high level. . When the signal A is at a low level, the MOS transistor 13b to which this signal A is input is turned on. Also, the MOS transistor 13 to which the signal C, which is at a low level at this time, is input.
When a is also in the on state, the signal BFi is inverted to high level.

At timing t., the pulse signal φ is inverted to a low level. When φ is inverted and becomes a low level, the MOS transistor 14a to which this φ is input is turned off, and the signal B
(MOS to which signal B is input) Lange 26-star 14b is also turned off, but MO to which signal B is input
Since the S transistor 19 is turned on, the unit circuit 1
The signal C of No. 4 remains at a low level. At this time, the output signal of the inverter 20 that inverts the input signal is input to the MOS transistor 12c, which is at a low level.
The S transistor 12d is also turned on, and the signal A remains at a low level. In other words, the signals A and C remain at a low level. Therefore, these signals A and C are input to the MOS transistor 1Sb.

13h are both in the on state, and the signal BFi remains at a high level.

If the J input signal is set to a high level and the K input signal is set to a low level in this way, the signal B becomes a high level with a delay of one bit of φ, and is held at this level thereafter.

Next, the operation will be described when the J input signal and the input signal are both set to a low level while the signals A, B, and C are at low, high, and similar levels. First, at the timing tlo, the pulse signal φ is inverted to a high level. When φ is inverted and becomes a high level, the MOS transistor 14c to which this φ is input is turned on, and the signal CFi remains at a low level. In addition, the MOS to which φ is input) range metal 11aFi is turned off, and the unit circuit 1 is turned off.

12 output terminals FivDD. At this time, the MOS transistor 15a receives the output signal of the inverter 17 that inverts the signal A, which was at a low level at the moment.
ON state, MOS input by φ) transistor 15r
tI when l is also on and φ is at a high level.
During the o period, the signal is held at a low level by the unit circuit 15.

If the signals A and C are both low level, the signals A and C
MOS) transistors 13b and 13 each input
m remains on, and signal B also remains at high level.

If signal B is high level, this signal B inputs MO
S) The transistor 19 is not turned on, and the signal C remains at a low level. Furthermore, the MOS to which this signal B is input
) The transistor 12d is also in the on state, and the output signal of the inverter 20 that inverts the input signal is input to the signal that is at a low level at this time.) The transistor 12e
Since the signal AFi remains on, the signal AFi remains at a low level. Therefore, each signal A, fl also at the timing of tl and tlo.

The CUs are held at low, high, and similar levels, respectively.

If both the J input signal and the 2 input signal are set to a low level in this way, the signal B will continue to maintain its previous state.

Next, with signals A, B, and C at low, high, and similar levels, J
The operation when the input signal is set to low level and the K input signal is set to high level will be described.

In this case, MO8) transistors llc and 12b are both on, and MOS) transistors 11d and 12a are both off. First, when the /4' pulse signal φ is inverted to a high level at the timing tlm, the MOS transistor 14c to which this φ is input is turned on, and the signal C remains at a low level. In addition, the MOS transistor 29-talla to which φ is input is not in the off state, and the output terminal of the unit circuit 11゜120 is cut off from vDD, but the output of the inverter 17 inverts the signal AV, which has been at a low level until now. MOS to which the signal is input) Transistor 15a must be on,
Furthermore, since the transistor J5d in which φ is input is also turned on, the signal is held at a low level by the unit circuit 15 during the t+m period when φ is at a high level. If both signals A and C are low level, each signal A
, C) transistors 13b and 13m are not in the on state, and the signal B remains at a high level. If signal B remains at high level, this signal B will cause input M
OS) The transistor 19 is not turned on, and the signal C becomes low level.

The Fi pulse signal φ is inverted to a low level at the timing tl. When φ is inverted and becomes a low level, the MOS transistor 11a to which this φ is input is turned on. The MOS to which the signal C, which is at a low level at this time, is input
) The transistor 12a is in the ON state, and is a MOS to which the output signal of the inverter 2O is input.
) Since the transistor 12b is also in the on state, the signal is inverted to a high level. When signal A reaches the cooperative level,
MOS to which this signal A is input) transistor J, yb
Fi off state, MOS input by φ) transistor 13
r1 is also turned off, and the output terminal of the unit circuit 13 becomes vD.
A MOS that is cut off from both D and GND, but receives the output signal of the inverter 18 that inverts the signal B, which has been at a high level.) A MOS in which the range meta 16bld is not on, and φ is also input.) A transistor 16a is also input. Since it is in the on state, the signal B is held at a high level by the unit circuit 16 during the tI4 period when φ is at a low level. Furthermore, if signal B is at a high level, this signal B inputs MO
S) The transistor 19 is turned on and the signal C becomes low level.

At the timing tIII), the fourth pulse signal φ is again inverted to high level. When φ becomes a high level, the MOS transistor 14c to which this φ is input is turned on, and the signal C remains at a low level.

At this time, the MOS transistor lla to which φ is input is turned off, and the output terminal of the unit circuit 12 is cut off from VDD, but the output signal of the inverter 17 that inverts the signal A, which is at an extremely high level, is turned off. The input MOS transistor 15b is not on, and the MOS transistor 15LL to which the signal C is input is also on, so the signal Au unit circuit 16 is at a high level during the period when φ is at a high level. is maintained. If signal A is at a high level, MOS transistor 1 to which this signal A is input
3c is on state, φ is input MOS) transistor J
Jd is also turned on, and signal B is inverted to low level.

At timing tl6, the pulse signal φ is inverted to low level. When φ becomes low level, this φ inputs MOS
) The transistor 14a is turned on. Furthermore, the MOS transistor 14b to which the signal B, which is at a low level, is input is also turned on, and the signal C! Invert - to high level. When the signal C is at a high level, the MOS transistor 1.9a to which this signal C is input is in the off state, and the MOS transistor 13rl to which φ is input is also in the off state, so the output terminal of the unit circuit 13 is vDD.

Although it is cut off from both GND, the output signal of the inverter 18 that inverts the signal B, which has been at a low level, is input to the MOS.
MOS to which signal C, which is at a higher level, is input
) Since the transistor 16d is also turned on, the signal B is held at a low level by the unit circuit 16 during the tl- period when φ is at a low level. When the signal B is at a low level, the MOS transistor 11b to which the signal B is input is turned on. At this time, the MO to which the J input signal is input
S) The transistor lla is in the on state, and the MOS to which φ is input.) The transistor 11a is also in the on state, so the signal A remains at a high level.

If the J input signal is set to a low level and the K input signal is set to a high level in this way, the signal B becomes low level with a delay of one bit of φ, and is held at this level 33- thereafter.

As described above, the conventional circuit shown in FIG. 1 operates as a J- flip-flop circuit.

Incidentally, a conventional one-phase static type J- having the above-mentioned configuration is also being considered in which a reset function and a set function are added to the 7-lip float circuit. That is, as shown in FIG. 3, this means that the unit circuit 11.
Two P-channel MO8 transistors 12 are connected to the P-channel MO8 transistor 11h that inputs φ at 12.
e, 12f are connected in series, and this P-channel MOS) transistor 12f and unit circuit 11.1 are connected in series.
A P-channel MO8) transistor 12gf is inserted in parallel between the common output terminal of the circuit 11. are inserted in parallel, and the P-channel Mos transistor 13 of the unit circuit 13
P channel MO8) 9 y raster 13e is inserted in series between a and VDD, and P channel MO8) run raster 1 is inserted between the output end of unit circuit 13 and vDD.
By inserting the entire St column, the MOS in this unit circuit 13 is
) N-channel MOS between the run transistor 13d and GND
Transistor lsgkm - An N-channel MO is connected between this MOS transistor 13g and the output terminal of the unit circuit 13.
S) Run sister 13h is inserted in parallel, MO8) Run sister 12f is inserted in parallel.

A set signal sETk, which becomes high level when set, is supplied to each r-cell of 12h.
An inverted (complementary) signal of the set signal by the inverter 21 is supplied to each dart of 3g, and the above MO8) run sister 13
A reset signal RESET which becomes high level upon reset is supplied to each gate of MO8) Runsistor 12e, and an inverted (complementary) signal of the reset signal by the inverter 22 is supplied to the dart of MO8) Runsistor 12e.
The signal C is applied to the dirt of 2g, and the above MOS transistor 1
The Fi1 phase pulse signal φ is supplied to each of the darts of 21 and 21, and between the MOS transistors that constitute each unit circuit 11 to 14) and the MOS transistor that constitutes each unit circuit 15 and 16)! The ratio of the Im values is set to a large value, and when the set signal 5IET and the reset signal RESET are both at high level, the set is given priority.

[Problems with background technology]

However, the conventional single-phase static J-type flip-flop circuit with reset and set functions as described above still has the problems of a large number of elements, a complicated configuration, and a large turn area. ing. In particular, as mentioned above, only so-called one-sided priority systems have been developed that give priority to set or reset (not shown), and TTL systems that give priority to both sides have appeared (
) Run sister transistor logic)
Another major problem is that it is not compatible with flip-flop circuits.

[Purpose of the invention]

This invention was made in consideration of the above circumstances, and has a simple configuration with a small number of elements, has both set and reset priority functions, and is an extremely good one-phase static type J- that is the motherboard of TTL and converters. The purpose is to provide a fast-track circuit.

[Summary of the invention]

That is, the present invention provides the first potential supply end and the first output end of one channel. 2nd, 3rd. Fourth I
GFIIET is inserted in series and the second and third I GFE
The 5th. A sixth IGFKT is inserted in series and the first IGFKT is inserted in series. A seventh IGFET of one channel is inserted between the connection point of the second IGFET and the first output terminal, and a seventh IGFET of the other channel is inserted between the first output terminal and the second potential supply terminal. 8゜9th. A tenth IGFET is inserted in series and the first IGFET is inserted in series.
and the output end of the ninth. between the connection point of the 10th IGFET and the 11th IGFET of the other channel. A twelfth IGFET is inserted in series, and a thirteenth 37-IGFET of the other channel is inserted between the first output terminal and the second potential supply terminal to form a first unit, and 1
The 14th. 15th. A 16th IGFET is inserted in series, and a 17th IGFET of one channel is inserted between the first potential supply end and the second output end, and the second output end and the second potential supply end are connected to each other. the 18th and 19th ends of the other channel. A 20th IGFET is inserted in series between the second output terminal and the 19th IGFET. The 21st IGFET ff of the other channel is connected between the connection point of the 20th IGFET
22.i of one channel is inserted between the first potential supply end and the third output end to form a second unit. Second
3 IGFETs k are inserted in series, and a 24th IGFET 'i of the other channel is inserted between the third output terminal and the second potential supply terminal to form a third unit; ．． The J input signal is supplied to the dart of the eighth IGFET, the input signal is supplied to the dart of the sixth and eleventh IGFETs via an inverter, and the input signal is supplied to the dart of the sixth and eleventh IGFET, and the input signal is supplied to the dart of the sixth and eleventh IGFET. 1st
The output signal 3 of the first unit is connected to the dart of IGFET 8.
No. 8- is supplied, and the above No. 3. 12th. The output signal of the second unit is supplied to the dart of the 23rd IGFET, the output signal of the third unit is supplied to the fifth, ninth, and fifteenth IGFETs, and the output signal of the third unit is supplied to the fifth, ninth, and fifteenth IGFETs. 1. 13th I
GFET Dart and the 17th and 20th IGFETs
The set signals are supplied to the darts of the seventh dart in an inverse relation to each other. The tenth I GFET dart and the fourteenth.
A reset signal is supplied to the dart of the 21st IGFET in an inverted relationship with respect to the M2. No. 19. A dynamic section in which a one-phase Norse signal is supplied to the dart of the 222M24 IGFET, and 25th and 26th IGF's of one channel are connected between the first potential supply terminal and the fourth output terminal. E
T i is inserted in series, and the 27th. 28th
A fourth unit is constructed by inserting IGF'E'I' in series, and one Tejanel's 29th. a 30th IGFET is inserted in series, and a 31st IGF'ET of the other channel is inserted between the fifth output terminal and the second potential supply terminal to constitute a fifth unit; The 32nd potential of the other channel is connected between the third output end of the third unit and the second potential supply end.
into the IGFET' of the 25th. No. 30. Third
The output signal of the third unit is supplied to the dart of the I GFET of the third unit. 12th. 23rd. 26th. Second
7. All the output signals of the fifth unit are supplied to the field of the 32nd IGFET, the output signals of the second unit are supplied to the field of the 32nd IGFET, and the output signal of the second unit is supplied to the field of the 32nd IGFET.
The output signal of the fourth unit is supplied to the dart of the 18th IGFKT, and the 28th. a static section configured by supplying the one-phase Norse signal to the dart of a twenty-ninth IGFET; the output signal of the second unit is one of the output signals; 7. 10th
This is characterized in that the output signal is ANDed with the above-mentioned set signal supplied to the dart of the rGFET to obtain the other output signal.

Further, in the present invention, a first terminal of one Tejanel is provided between the first potential supply end and the first output end. 2nd゜3rd. 4th IGF
ET is inserted into the inner row, and the second. The fifth IGFET of one channel is connected between the connection point of the third IGFET and the first output terminal. 6th
The IGF'ET' of the first . Second IGF
A seventh IGFET of one channel is inserted between the connection point of the ET and the first output terminal, and an eighth IGFET of the other channel is inserted between the first output terminal and the second potential supply terminal. 9. A tenth IGFET is inserted in series between the first output terminal and the ninth IGFET. The connection point of the 10th I GFET and the 11th I GFET of the other channel. A twelfth IGFET is inserted in series, and a thirteenth IGFET of the other channel is inserted between the first output terminal and the second potential supply terminal to form a first unit. , one-channel 14th, 15th, and 16th rGFETs are inserted in series between the first potential supply terminal and the second output terminal, and the first potential supply terminal and the second output terminal 17th I GFE of one channel during
T and the second output end and the second one
18th 41-19th of the other channel between the i-position supply end and the other channel. A 20th IGFET is inserted in series between the second output terminal and the 19th IGFET. Insert the 21st IGFET e of the other channel between the connection point of the 20th IGFET and
The 22nd. 23rd IGFET
e in series, and the third output terminal and the second
the 24th IGFE of the other channel between the potential supply end of
T is inserted to form a third unit, and the fourth. The J input signal is supplied to the dart of the 8th IGFET via an inverter, the input signal is supplied to the dart of the 61st and 11th IGFET, and the input signal is supplied to the dart of the 16th IGFET. The output signal of the first unit is supplied to the dart of the eighteenth IGFET, and the third. 12th. 23rd I GFET dart
supplying the output signal of the unit body of the fifth unit. 9th. 15th
Before the IGFET dirt! i[2 supplies the output signal of the third unit; Reset signals are supplied to the darts of the thirteenth IGFET and the darts of the seventeenth and 20th IGFETs in an inverse relationship to each other; 104th
2- IGFET L0D Dart and the 14th. The set signals are supplied to the darts of the 21st I GFET in an inverse relationship to each other, and the 2nd. No. 19. 22nd. 24th IGFE
A dynamic section that supplies a one-phase pulse signal to the dart of T, and a 25° to 26th IGFET'! of one channel between the first potential supply end and the fourth output end. t
iW column is inserted and the fourth output terminal and the second
and the potential supply end of the other channel. A 28th IGFET 'i is inserted in series to form a fourth unit,
29. of one channel between the ii2 first potential supply end and the fifth output end. The 30th IGFET 'k is inserted in a row, and the 31st IGFET of the other channel is inserted between the fifth output terminal and the second potential supply terminal to constitute the fifth unit; The 32nd IGF'ET'i of the other channel is inserted between the third output end of the third unit and the second potential supply end, and the 25th. Third
0, IX 31 (D IGFET (Dl'-
) d) supplying the output signal of the unit N3;
゜m12. 23rd. 26th. 27th. 32nd IGIT
The output signal of the fifth unit is supplied to the dart of the 32nd IGFET, and the output signal of the second unit is supplied to the dart of the 16th and 18th IGFET. The output signal of the 28th unit is supplied to the 28th unit.
．． a static part configured by supplying the one-phase pulse signal mentioned above to the dart of a twenty-ninth IGFET; the output signal of the second unit is one of the output signals; ．． This is characterized in that the logic 8# of the reset signal supplied to the dart of the thirteenth IGFET is taken as the other output signal.

Furthermore, the present invention provides the first potential supply terminal and the first output terminal of one channel between the first potential supply terminal and the first output terminal. 2nd degree 31st m4 IG
FET is inserted in series and the second. The fifth IGFET of one channel is connected between the connection point of the third IGFET and the first output terminal. A sixth I GFET is inserted in series. Second IGF
A seventh IGFET of one channel is inserted between the connection point of the ET and the first output terminal, and an eighth IGFET of the 4111 channel is inserted between the first output terminal and the second potential supply terminal.゜No. 9. A 10th IGFET is inserted in the inner row, and the first output terminal and the front C 9th IGFET are inserted. between the connection point of the 10th IGFET and the 11th IGFET of the other channel. A twelfth IGFET is inserted in series, and a thirteenth IGFET of the other channel is inserted between the first output terminal and the second potential supply terminal to form a first unit, and the first 14. of one channel between the potential supply end and the second output end. 15th. 16th IG
FETs are inserted in series, and a 17th IGFET' of one channel is inserted between the first potential supply terminal and the second output terminal.
ii, and the 18th and 19th channels of the other channel are inserted between the second output terminal and the second potential supply terminal. Second
0 IGFET is inserted in series to connect the second output terminal and the M
19. A 21st IGFET of the other channel is inserted between the connection point of the 20th IGFET to form a second unit, and one of the IGFETs is connected between the first potential supply end and the third output end. Channel 22. A 23rd IGFET 'e is inserted in series, and a 24th IGFET 'i of a 4jJ channel is inserted between the third output terminal, the second potential supply terminal and 45- to form a third unit. And the above 3. 9th IGF
The J input signal is supplied to the dart of ET, and the fifth and twelfth
An input signal is supplied to the 15th I GFET dart through an inverter. The output signal of the first unit is supplied to the dart of the nineteenth I GFET, and the fourth.
11th. The output signal of the second unit is supplied to the dart of the twenty-second IGFET, and the sixth. 8th. 16th IG
The output signal of the third unit is supplied to the dart of the 13th IGFET and the set signals are supplied to the dart of the 13th IGFET and the 17th and 20th (D IGFETs (71'-)) in a mutually inverted relationship. and the said No. 7. No. 10
IGFET dart and the 14th. 21st IGF
r-) of the ETs in an inverse relationship to each other, and the 2nd I, 18th . 23rd. A dynamic part is formed by supplying a 1-phase 4 pulse signal to the dart of the 24th IGFET, and 25th and 26th IGFET's of one channel are connected between the first potential supply terminal and the fourth output terminal. e is inserted in series, and the 27th. A 28th rGFET is inserted in series 7 to form a fourth temperature field, and a 29th rGFET of one channel is inserted between the first potential supply end and the fifth output end. 30th I
GFETs are inserted in series, and a 31st IGFET of the other channel is inserted between the fifth output terminal and the second potential supply terminal to form a fifth unit, and the third
The 32nd IGFKTi of the other channel is inserted between the third output terminal of the unit body and the second potential supply terminal, and the third supplying the output signal of the unit body 4. 11th.
22nd. 25th. 28th. The output signal of the fifth unit is supplied to the dart of the 32nd IGFET, the output signal of the second unit is supplied to the dart of the 32nd IGFET, and the output signal of the second unit is supplied to the dart of the 32nd IGFET. The output signal of the fourth unit is supplied to the dart of the 19th TGFET, and the 27th . Third
A static section formed by supplying all of the 1-phase pulse signals to the dart of the 7th IGFET is specifically biased, the output signal of the 2nd unit is set as one output signal, and this one output signal and the 7th. The present invention is characterized in that the logical product of the reset signal and the reset signal supplied to the IGFET of Mlo is used as the other output signal.

[Embodiments of the invention]

The present invention will be described in detail below with reference to the drawings. m4
Figure d is a circuit configuration diagram of the first embodiment of the one-phase static type J- frizzo flop circuit according to the present invention, and this circuit is roughly divided into two parts: a dynamic loop and a static loop. . Furthermore, among these, the dynamic loop is 1.4%2, 3rd
The static loop is composed of the units 3J, 3j, and JJ, and the static loop is the fourth unit. Each fifth unit 34.3
5 and N channel MO8) transistor 36.

In the first unit 31, four P-channel MO8s are connected between the positive potential VDD supply point and the base $% GND supply point.
) transistors 31m, 31b.

31c, 31d and three N-channel MO8)
The transistors 31e, 31f, i1g are inserted in series in this order, and the P-channel MO8) transistor,
9 l b, 31 e connection point and N channel MO8
) Between the connection points of transistors 31f, , 91g, two P-channel MO8) transistors 31h.

311 and two N-channel MO8) transistors 31j
, 31k in series in this order, and the P channel M
O8) A P-channel MO8) transistor 31 and an N-channel MO8) transistor 31 m'i are inserted in series in this order between the connection point of the transistors 31g and 31b and GND, and a P-channel MOS transistor, 91d, ,
The respective connection points of the transistors 31e, , 91t and the N-channel MO8) transistors 31e, , 11j, 31m are commonly connected, and the common connection point is used as an output end.

Furthermore, in the second unit 32, three P-channel MOS transistors 32*, 32 are provided between vDD and GND.
b, 32a and three N-channel MO8 transistors 3
2rl, 32e, 32ff49 - Insert in series in this order and also connect DD and N channel MO
8) P channel MO8) transistor 32g'l and N channel MO8) transistor, 92h''i are inserted in series in this order between the connection point of transistors 32e and 32f, and the above P channel MO8) transistor, 92e
, 32 g and N-channel MO8) transistor 32 (
1 and 32h are commonly connected, and the common connection point is used as an output end.

Further, in the third unit 33, two P-channel MO8) transistors 93 a are connected between vDD and GND.
, 33b and one N-channel Mos transistor 33af are inserted in series in this order to form a P-channel MO8) transistor 33b and an N-channel MO8) transistor 33.
The connection point with is the output end.

In addition, in the fourth unit 34, two P-channel MO8) transistors 34h and 941 are provided between vDD and GND.
b D and two N-channel MO8) transistors 34Q,
34df are inserted in series in this order, and the connection point between the P-channel MOS transistor 34b and the N-channel 50-MOS transistor 34o is used as an output terminal.

Roughly speaking, in the fifth unit 35, two P-channel M0S transistors 13.5 a are connected between DD and GND.
, , 95 b and one N-channel MO8) transistor, 95 c 'i insert this l1lin K m column,
The connection point between the P-channel MO8) transistor 9sb and the N-channel MO8) lannostar 35c is used as the output terminal.

In addition, the N-channel MO8) Lanzoster 36 is inserted between the output end of the third unit 33 and GND.

Then, the J input signal is the P channel MOS transistor, ? 1 d and N channel MO8) transistor 31
K input signal is supplied to each r-) of inverter 3
7 to each gate of the P-channel MOS transistor 311 and the N-channel MO8 transistor 31j. Further, the signal A at the output end of the first unit 31 is supplied to each of the P-channel MO8) transistors 32G and the N-channel MO8) transistors 32d. Furthermore, the signal B at the output terminal of the second unit 32 is applied to the P-channel MOS transistor 31c and the N-channel MO8) transistor s1.
transistor 33b.

, wo4b and N-channel MO8) transistor 34c.

36 darts each. Furthermore, the signal C at the output end of the third unit 33 is the N-channel MO8')
Transistor 31fsP channel MO8 transistor 31
h, 32b, 34a, 35b and N channel MOS transistor 35c.

Furthermore, the signal at the output end of the fourth unit 34 is supplied to each of the P-channel MO8) transistors 32c and the N-channel MO8) transistors 32d. Further, the signal at the /Jj power end of the fifth unit 35 is transmitted to the P channel MO8) run raster 31c, the N channel MO
8) %P channel MO8) Transistor 33b to transistor 31.

34b and N-channel MO8) are supplied to each dart of transistors 34e36.

Here, the set signal 〒 is applied to the P channel MO8) transistor 31a and the N channel M via the inverter 38.
O8) Supplied to each gate of the transistor 31m. Further, the set signal SET through the inverter 38 is applied to the P-channel MO8 transistor 32g and the N-channel MO8 transistor 32g through another inverter 39.
f is supplied to each gate. Furthermore, the reset signal RE
SET or the above P channel MO via the inverter 40
8) Supplied to each gate of the transistor 32a and the N-channel MOS transistor J2h. Additionally, the reset signal RESET via the inverter 40 is transmitted via another inverter 41 to the P-channel MO8) transistor 91 and the N-channel MO8) transistor 31.
It is supplied to each dart of g and also to one input terminal of the NAND circuit 42. The signal at the output end of this NAND circuit 42 becomes one output signal of the flip-flop circuit to the one-phase static type J-53 to be described here through inverters 43 and 44 all in series.

However, the signals at the output terminals of the second unit 33 and the fifth unit 35 are supplied to the other input terminal of the NAND circuit 42, and the inverter 4.5.46f shield array , it becomes the other output signal Q of the one-phase static type J- flip-flop circuit described here.

Furthermore, the P channel MO8) run raster 31b, N
channel MO8) transistor 32, P channel MO8
) transistor 33m, N channel MO8) transistor,
9.9c, 34d and P channel MO8) A one-phase pulse signal φ is supplied to each dart of transistor ssa.

Next, the operation of the circuit configured as described above will be explained using the timing chart shown in FIG. In this case, first, the operation of the dynamic loop with the static loop omitted will be described (in the timing chart shown in FIG. 5, the portion indicated by the dotted line is the dynamic holding period). However, at this time, SET SET and 54- (RESET) (S RESET i-) are both connected to the low level GND.
The set signal image and reset signal oil level in Figure 4 are both at high level V. It is assumed that the level is 0. For this reason, the above MO8) transistor 31
a, 32a, 31g, 92f are all on, and MOS transistors 31L, 32g are turned on.
+, 'j 1 m, and 32 h are all off.

Then, at timings 1 to 1, both the ~J input signal and the input coefficient are set to high level. Then, J
Since both the input signal and the input signal are at the low level, M
OS) transistors 31e and 31i turn on,
Since the MOS transistors 31 d and 31 j are turned off, the dynamic roof of the circuit shown in FIG. 4 can be equivalently considered as the circuit shown in FIG. 6. At this time, φ is at a low level. .Furthermore, at this time @
Assuming that the signal B' (j is low level, the M0S transistor 3.9b is turned on, and the MOS transistor 3.9 b is turned on, and the MOS
Since the transistor 33a is also turned on, one signal C becomes high level. Also, M to which this high-level letter C is input
OS) Since the transistor 31f turns on, the signal A becomes low level.

When φ flips to high level at timing tl, M
The OS transistor 33a turns on and the signal C is inverted to low level. When the signal C is inverted to a low level, the MOS transistor 31f is turned off, and the MOS transistor 31b to which the high level φ is input is also turned off, so the output terminal of the first unit 31 is cut off from both vDD and GND. However, the signal A at the output terminal is not dynamically maintained.
will be maintained at the same low level. Further, the MOS transistor 32c to which this low level signal A is input is turned on, and the MOS transistor 32b to which the low level signal C is input is also turned on, so that the signal B is inverted to a high level.

When φ is reversed to low level at timing 11, MO
Since the transistor 33b is also turned off, the output terminal of the third unit 33 is connected to vDD and G.
Although it is cut off from both ND, the coefficient C at its output terminal is kept at the low level due to dynamic maintenance.

MOS to which this low level signal C is input) transistor 3 J h is turned on, and MOS to which low level φ is input
S) Since the transistor 31b is also turned on, the signal AH is inverted to high level. Furthermore, the MOS transistor 32c to which this high-level coefficient A is input is turned off, and the MOS transistor 32e to which the low-level φ is input is also turned off, so that the output terminal of the second unit 32 is connected between vDD and GND. Although it is cut off from both, the signal BFi at its output terminal is kept dynamically at a high level.

At 1.0 timing, φ is reversed to high level, MO
Since the S transistor 33a is turned on, the coefficient C remains at a low level. M to which this low level signal C is input
OS) The transistor 311 is turned off, and the acid level φ is input.MOS) The transistor 31b is also turned off, so
The output end of the first unit 31 is cut off from both vDD and GND, but the signal A at the output end is held at the high level at the dynamic hold=57-. In addition, this high level signal A is input to a MOS transistor 32.
When d is turned on, the MOS transistor 92e to which high-level φ is input is also turned on, so that the signal B is inverted to a low level.

When φ is inverted to a low level at timing t4, the MOS transistor 33h is turned on and the low level signal B is input.) The transistor 33b is also turned on, so the coefficient C is reversed to high level. Then, the MOS to which the high level signal C is input ()
Since the transistor 31f is turned on, the signal AH is inverted to low level. In addition, the MOS transistor 32rl to which this low level signal A is input is turned off, and the MOS transistor 32b to which the high level signal C is input is also turned off, so that the output terminal of the second unit 32 is connected to vDD. Although it is cut off from both GND, the signal B at its output terminal is kept dynamically at the low level it has been.

At timing t6, when φ is inverted to a high level, the MOS transistor 33a is turned on, and the signal C is inverted to a low level. Then, the MOS transistor 31f to which this low level signal C is input is turned off, and the MOS transistor 31f to which the high level signal C is input is turned off.
Since the output terminal of the first unit 31 is also turned off, the output terminal of the first unit 31 is cut off from both DD and GND, but the coefficient A of the output terminal is kept at a low level until it is dynamically maintained. Ru. Too bad, this low level signal A dE large input MO
S) Since the transistor 32e is turned on and the MOS transistor 32b to which the low level signal C is input is also turned on,
The signal Bu is inverted to high level.

In this state, we have returned to the first timing tl, and if we consider the period from tl to t6\) as one cycle, then
After this, the same cycle is repeated every time φ is reversed.

In this way, when both the J input signal and the input coefficient are set to a high level, the signal becomes a 2-frequency divided signal of the B signal and the output signal Q multiplied by φ. In other words, the above circuit operates as a binary counter.

Next, the operation when the J input signal is set to high level and the K input signal is set to low level will be described. In this case, the MOS) transistors pJIe, 31j shown in FIG. 4 are turned on, and the MOS) transistors 91d, , 91
1 is turned off, the dynamic loop of the circuit shown in FIG. 4 can be isometrically considered as the circuit shown in FIG. 7.

When φ becomes high level at the timing of jll,
M OS ) Since the transistor 33a turns on, the coefficient C
It becomes a low level. Then, the MOS transistor J1f to which this low-level coefficient C is input is turned off, so the output terminal of the first unit 91 is cut off from both vDD and GND. The signal is not dynamically held and is held at the high level at 1 (see FIG. 5). Also, the MO to which this high level signal A is input is
S transistor? 2 d is on, and the MOS transistor 32e to which high level φ is input is also turned on, so
The signal Bu becomes low level.

When φ is inverted to low level at the timing of tv, the MOS transistor 93a to which the low level φ is input is turned on, and the MOS transistor 33b to which the low level signal B is input is also turned on, so that the coefficient It is inverted to C high level. Then, the MO to which the device level signal C is input
S) Since the Lanzoster 31f is turned on, the signal A is inverted to a low level. Furthermore, the MOS transistor 32b to which the high level signal C is input is turned off, and the MOS transistor 32e to which the low level φ is input is also turned off.
The output terminal of the second unit 32 is cut off from both vDD and GND, but the signal B at the output terminal is not dynamically maintained and is maintained at the low level as before.

At timing t8, when φ turns to high level, the MOS transistor 33c turns on, so
The signal C is inverted to low level.

Then, this low-level double angle C is input to the MOS.
Transistor, 92 b f): MOS) transistor 3 that is turned on and receives the signal A that was currently at a low level
Since 2a is also on, signal Bd is inverted to high level. When the signal B is inverted to a high level, the Mos transistor 31k is turned on, so that the signal A remains at a low level.

62- When φ is inverted to a low level at the timing of t9, the MOS transistor 33b is turned off and the signal B, which has been at a high level until now, is input.
Since the OS transistor 33a is also turned off, the output terminal of the third unit 33 is cut off from both vDD and GND, but the signal C at the output terminal is not maintained dynamically, but is maintained at the low level as before. Ru. Then, the MOS transistor 32b to which the low level signal C is input turns on.
MOS to which signal A, which has been at a low level until now, is input
Since the transistor 32c is also turned on, the signal B remains at a high level. Also, MO to which high level signal B is input
S) Since the transistor 31k is turned on, the signal A remains at a low level.

When φ is reversed to high level at the timing of tlo,
Since the transistor 33C (MOS) is turned on, the signal C remains at a low level. Then, this low level signal C
MOS to which transistor 32b is turned on and signal A, which has been at a low level until now, is input to MOS)
Since the transistor 32e is also turned on, the signal B remains at a high level.

Since the MOS transistor 31k to which this high-level signal B is input is turned on, the signal A remains at a low level.

In this state, it returns to the timing t8, and from then on, every time φ is reversed, the timing t91. The state of tlo will be repeated. In this way, if the J input signal is set to high level and the input signal is set to low level, signal B and output signal Q will become high level with a delay of 1 bit of φ, and this level will be maintained from then on. Ru.

Next, we will explain the operation when both the J input signal and the input signal are set to a low level while the signals A, B, and C are at low, high, and low levels, respectively. In this case, the MOS transistors 31d and 31j shown in FIG. 4 are turned on,
Since the MOS) transistors 31e and 311 are turned off, the dynamic circuit of the circuit shown in FIG. 4 can be considered as the circuit shown in FIG. 8 with equal constraints.

First, at the timing of *111, when φ becomes high level, the MOS) transistor 93c turns on, so
Signal C remains at a low level. Also, a MOS to which the signal A, which has been at a low level until now, is input.
) Since the transistor 32b is also turned on, the signal B remains at a high level.

Then, the MOS to which this high level signal B is input is
Since the transistor 31k is turned on, the signal A remains at a low level.

When φ becomes a low level at the timing of tlm, the signal B that has been at a high level until now is input to the MOS.) Run raster 33b is turned off and a low level φ is input to the MOS.
Since the transistor 33a is also turned off, the third unit 33
The output terminal of is cut off from both vDD and GND, but the signal C at the output terminal is not dynamically maintained and is kept at the previous low level. Then, the MOS transistor 32b to which the low-level signal C is input is turned on, and the MOS transistor 32a to which the signal A, which had been at a low level, is input is also turned on, so the signal B remains at the high level. Become. Further, since the MOS transistor 31k to which this high-level signal B is input is turned on, the signal A remains at a low level.

When φ flips to high level at the timing of tlm, M
OS) Since transistor 33e turns on.

Signal C remains at a low level. In addition, the MOS transistor 3) into which the signal A, which has been at a low level until now, is input.
2a is turned on and low level signal C is input to the MOS
) Since the transistor 32b is also turned on, the signal B remains at a high level. Then, the MOS transistor 31k to which this high-level signal B is input is turned on, so that the signal A remains at a low level.

In this state, if we return to the timing tlo,
After this, every time φ is reversed, the timing jl! r jl
The state 1 is often repeated repeatedly. In this way, by setting both the %J input signal and the 66 input signal to a low level, the signal B, that is, the 66-output signal Q, will continue to maintain its previous state.

Next, the operation when the J input signal is set to a low level and the K input signal is set to a high level will be described.

In this case, the MOS transistor 31d shown in FIG.

, 911 turn on, MOS) transistors 3je, 31
Since j is turned off, the dynamic roots of the circuit shown in FIG. 4 can be considered as the circuit shown in FIG. 9 with equal constraints.

First, at timing t14, when φ becomes high level,
MOS) Since the run source 33c turns on, the signal C
is at a low level. Also, M to which a high level φ is input
Since the transistor 31b turns off (OS), the output terminal of the first unit 3 is cut off from both VDD and GND, but the signal A at the output terminal becomes dynamically maintained, and the current state (see Figure 5) is maintained. ) held at a low level. Furthermore, the transistor 32a is turned on, and the MOS transistor 32a to which this low level signal A is input is turned on, and the MOS transistor 32a to which the low level signal C is input is
Since the OS transistor 32b is also turned on, the signal B becomes high level.

When φ is reversed to low level at the timing of tI5,
MOS) transistor,? , 9c are turned off, and the MOS transistor 33b to which the signal B, which has been at a high level until now, is input is also turned off, so the output terminal of the third unit 33 is cut off from both VDD and GND. The signal C at the output terminal is not dynamically maintained and is maintained at the low level that it has been.

Then, the MOS to which this low level signal C is input ()
The transistor 31h is turned on, and the MOS transistor 31b to which low-level φ is input is also turned on, so that the signal A is inverted to a high level. Still, the MOS transistor 32c to which this high-level signal A is input is turned off, and the MOS transistor 32e to which the low-level signal φ is input is also turned off, so the output terminal of the second unit 32 is connected to vDD and GN.
However, the signal B at its output terminal is kept at the high level it has been in since it is not dynamically maintained.

When φ is reversed to high level at the timing of tts,
Since the transistor 33c (MOS) is turned on, the signal C remains at a low level. Also, since the MOS transistor 31b to which high-level φ is input is turned off, the output terminal of the first unit 3 is cut off from both vDD and GND, but the signal A at the output terminal remains dynamic. Tonanashi will be maintained at the high level up until now. Further, a MOS transistor 92 to which this high level signal A is input is
d is turned on, and the MOS transistor 32e to which high-level φ is input is also turned on, so that the signal B is inverted to a low level.

When φ is inverted to low level at timing 111, signal B, which was at low level until now, is input to the MOS.
The transistor 33b is turned on, and the MOS transistor 33a to which low-level φ is input is also turned on, so that the signal C is inverted to a high level.

Then, the MOS resistor 32b to which the high-level signal C is input turns off, and the MO transistor 32b to which the low-level signal φ is input turns off.
S) Since the transistor 32o is also turned off, the output terminal of the second unit 32 is cut off from both VDD and GND, but the signal B at the output terminal is not maintained dynamically and remains as low as before. held at the level. Further, the MOS transistor 31a to which this low level signal B is input is turned on.

MOS to which low level φ is input) t resistor 31
Since signal b is also turned on, signal A remains at high level.

When φ is reversed to high level at timing t18,
Since the MOS) transistor 33c is turned on, the signal C is inverted to a low level. Furthermore, since the MOS transistor 31b to which high-level φ is input is turned off, the output terminal of the first unit 31 is cut off from both vDD and GND, but the signal A at the output terminal is kept dynamic. C,
It will be maintained at the same high level as before. Further, a MOS transistor 92 to which this high level signal A is input is
d is turned on, and the MOS transistor 32o to which high-level φ is input is also turned on, so that the signal B remains at a low level.

In this state, the timing t1g is returned to the timing t1g.
*The state of tl8 will be repeated. In this way, if the J input signal is set to a low level and the K input signal is set to a high level, the signals B and b output signal Q will be at a low level with a delay of 1 bit of φ, and from then on, this level will be maintained. Retained.

As described above, the dynamic roots of the circuit shown in FIG. 4 result in a fritsuno-frotsuno circuit operation in J-.

Here, in the above explanation of the dynamic roots, when the output end of each unit body 31, 32, 33 is cut off from both VDD and GND, the signals A, B, and C at the output end are assumed to be dynamically maintained as shown in FIG. Although it has been explained that the previous state is maintained as indicated by the dotted line, this dynamically held state is statically held by the action of the static loop described below.

Therefore, the static route will be explained below. First, at the timing t1, the output terminal of the first unit 3 is cut off from both vDD and GND, but at this time, the MOS transistor 34c to which the high level signal B is input is turned on, MOS to which high level φ is input)
Since the transistor 34d is also turned on, the output signal of the fourth unit 34 is at a low level, and the signal A is held at a low level.

At timing t2, the second and third unit bodies 32, 3
．． Although the output terminals of 9 are cut off from both DD and GND, the signal B is at a high level at the timing of stl, so the MOS) transistor 36 is turned on and the signal C is held at a low level, and this low level signal C
MOS to which transistor 35b is turned on and low level φ is input to transistor 35
Since 1L is also turned on, the output signal of the fifth unit 35 remains at a high level, and the signal B is held at a high level. That is, at this timing t2, the signal B is
, C.

At timing t3, the output terminal of the first unit 3 becomes VD.
Although cut off from both D and GND, the low level signal C
MOS to which transistor 34m is turned on and low level signal B is input) transistor 34
Since the signal A is also turned on, the output signal of the fourth unit 34 is not at a high level, and the signal A is kept at a high level.

At timing t4, the output end of the second unit 32 becomes vD.
Although cut off from both D and GND, the high level signal C
Since the MOS transistor 35c to which is input is turned on, the output signal of the fifth unit 35 is at a low level, and the signal B is held at a low level.

At timing t5, the output terminal of the first unit 3 becomes vD.
A high level signal B that is blocked from both D and GND
The MOS transistor 34c to which φ is input is turned on, and the MOS transistor 34d to which high-level φ is input is also turned on, so the output signal of the fourth unit 34 is at a low level, and the signal A is kept at a low level. be done.

73- At the timing of t6, the output terminal of the first unit 3 becomes vD.
Although cut off from both D and GND, the low level signal C
MOS to which transistor 34& is inputted and low level signal B is inputted to transistor 34
Since the signal A is also turned on, the output signal of the fourth unit 34 is not at a high level, and the signal A is kept at a high level.

At timing t7, the output end of the second unit 32 reaches vD.
Although cut off from both D and GND, the high level signal C
Since the MOS transistor 35a to which is input is turned on, the output terminal of the fifth unit 35 becomes a low level, and the signal B is held at a low level.

At timing t9, the output end of the third unit 33 becomes vD.
A high level signal B that is blocked from both D and GND
The signal C is held at a low level because the MOS transistor 36 to which it is input is turned on.

At the timing of tti, the output end of the first unit 31 becomes v
MOS) transistor, 9 which is cut off from both DD and GND but receives high level signal B
4 MOS where c is turned on and high level φ is input)
Since the transistor 34d is also turned on, the output signal of the fourth unit 34 is kept at a low level, and the signal A is kept at a low level.

At the timing of tlg, the output terminal of the third unit 33 becomes V
Since the MOS transistor 36, which is cut off from both DD and GND but receives a high-level signal B, is turned on, the signal C is held at a low level.

At the timing of tlg, the output end of the first unit 3 becomes v
MOS (MOS) which is cut off from both DD and GND but receives high level signal B) Runnostar 34c is turned on,
MOS to which high level φ is input) transistor 34d
is also turned on, so the output signal of the fourth unit 34 is at a low level, and the signal A is held at a low level.

At timing t14, the output end of the first unit 31 reaches V
MOS transistor 94 which is cut off from both DD and GND but receives a high level signal B; MOS transistor 94 c is turned on and receives a high level φ;
Since d is also turned on, the output signal of the fourth unit 34 is at a low level, and the signal A is held at a low level.

At the timing of tts, the second and third unit bodies 32,
,? The output terminals of 3 are each cut off from both VDD and GND, but since signal B is at a high level at timing t14, MOS) Lanzostar 36 is turned on,
The signal C is held at a low level, and the MOS transistor 35b to which this low-level signal C is input is turned on, and the MOS transistor 35a to which the low-level φ is input is also turned on, so that the fifth unit When the output signal of the body 35 is at a high level, the signal B is held at a high level.

That is, at the timing of tllll, the signals B and C are held due to the positive feedback effect by the MOS transistor 36 and the fifth unit 35, similar to the timing of t2.

At the timing of tlg, the output end of the first unit 31 becomes v
A MOS that is cut off from both DD and GND but receives a low-level signal C.) A MOS transistor 94a is turned on and a low-level signal B is input.) Since the transistor 34b is also turned on, the fourth The output signal of the unit 34 is not at a high level, and the signal A is held at a high level.

At the timing of tty, the output end of the second unit 32 becomes v
The transistor 35a is turned on, so the output signal of the fifth unit 35 becomes low level.
Signal B is held low.

At the timing of tts, the output terminal of the first unit 3 becomes V
MOS transistor 34a is cut off from both DD and GND, but low-level signal C is input, and transistor 34a is turned on.
MOS to which low level signal B is input) transistor 3
4b is turned on, the output signal of the fourth unit 34 is at a high level.

Signal A is held high.

In this way, signals A and B shown by dotted lines in FIG.

The dynamic holding state of C is made into a static holding state by the action of the static tire 77-.

Next, set signal SET and reset signal RESETK
explain about. First, if the reset signal RESET is low level and the set signal SET is high level, then
In the figure, a case will be explained in which the reset signal RESET is at a high level and the set signal SET is at a low level. In this case, since the MOS transistor 32g is turned on, the signal B becomes a high level, and the output signal Q is eventually set to a high level and both are set to a low level.

Next, when the reset signal RESET is at a high level and the set signal SET is at a low level, in the case of a reset pulse, both MOS transistors 32f and 32h are turned on, so the signal B becomes a low level and the output is eventually output. The signal Q is set to a low level, and the signal Q is set to a high level.

Furthermore, when the reset signal RESET and the set signal SET are both at high level, and when the reset signal 78- signal RESET and set signal SET are both at low level, the MOS transistor 32g is turned on and the signal B becomes high level. As a result, both output signals Q and Q are set to high level. Here, the operations explained above are summarized as shown in the following table.

Therefore, according to the configuration as in the first embodiment,
When the reset signal RESET and set signal SET are both high level, the output signals Q and Q are both high level.
A 7-lip-frog circuit can be provided for a so-called reset, reset, and set dual priority type J-. Furthermore, compared to the conventional circuit shown in FIG. 3, the number of elements is smaller and the configuration is simpler.

FIG. 10 is a circuit diagram of a second embodiment of the present invention, and FIG. 11 is a timing chart showing its operation. In this second example.

Each P-channel MOS transistor in the first embodiment is replaced with an N-channel MOS transistor, and conversely, the N-channel MOS transistor is replaced with a P-channel MO8) transistor, and the power supply connections are also changed accordingly. This is a reverse version, and the numbers "1" are prefixed to the parts corresponding to those in FIG. 4. However, in this case, P channel MO8) transistor 1
31g and N channel MOS) transistor 131t) Set signal SET via K inverter 138
and supplies a set signal SET via an inverter 139 to each dart of the N-channel MOS) transistor 132a and the P-channel MO8) transistor 132h,
A reset signal RESET is supplied via the inverter 140 to each dart of the P-channel MO8) transistor 132f and the N-channel MOS transistor 132g.
O8) Inverter 14 for each dirt of 131m transistor
1 through the P-channel MO8) transistor 131e and the N-channel MOS
) The J input signal is supplied to each dart of the transistor 131d via the inverter 187, and
Input signals are directly supplied to each of the 11 darts.

As shown in FIG. 11, the operation is such that the phase of the signal B is different from that of the first embodiment circuit, so that the output signal Q of the signal B is synchronized with the falling edge of φ. φ18
It is shifted by 0° (half bit).

FIG. 4 is a circuit diagram 81 of a third embodiment of the present invention. This third embodiment circuit consists of the series-connected MOS transistors 31c, 31d and J 1 e t J 1 f and 31h, 311 and 31j, 31k and 32b of the first embodiment circuit shown in FIG. , 3
2a and 32d, 32m and 33h, 33b and 3
4a.

The positions of 34b and 34a, 34d and 35m, and 35b are exchanged with each other, and it goes without saying that even with such a configuration, the same operation as in the first embodiment can be performed.

It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the gist thereof.

〔Effect of the invention〕

Therefore, as detailed above, according to the present invention, the number of elements is small and the configuration is simple.

It is possible to provide a free-lag floating circuit for an extremely good one-phase static type J- that is equipped with a reset priority function and is compatible with TTL.

82-

[Brief explanation of the drawing]

Figures 1 and 2 are circuit configuration diagrams showing a free-lag floating circuit in a conventional one-phase static type J-, and a timing diagram to explain its operation, and Figure 3 is set to the conventional circuit shown in Figure 1. FIGS. 4 and 5 are circuit configuration diagrams showing a state in which a priority function is provided, and FIG. 4 and FIG. 6 to 9 are timing diagrams for explaining the J input signal and the equivalent circuit configuration diagram of the embodiment circuit shown in FIG. FIG. 12 is a circuit configuration diagram showing a second embodiment of the present invention and a timing diagram for explaining its operation, and FIG. 12 is a circuit configuration diagram showing a third embodiment of the invention. 11-16...Unit circuit, 17.18...Inverter, 19...N-channel MO8 transistor. 20-22... Inverter, 3... First unit, 32... Second unit, 33... Third unit,
34...Fourth unit body, 35...Fifth unit body, 3
6...N channel MO8) transistor, 37~4 no.
...Inverter, 42...NAND circuit, 43-46.
...Inverter. Applicant's agent Patent attorney Takehiko Suzue -IIQ- ((f) U Figure 6 f] Figure 7 Figure 8 Figure 9

Claims (3)

[Claims] (1) Between the first potential supply end and the first output end, the first. Second. Third. A fourth IGFET is inserted in series and the second IGFET is inserted in series. The fifth IGFET of one channel is connected between the connection point of the third IGFET and the first output terminal. 6th I GFE
A seventh IGF of one channel is inserted between the connection point of the first and second IGFETs and the first output terminal.
ET e of the other channel between the first output terminal and the second potential supply terminal. 9th. A tenth IGFET 'Ik is inserted in series between the first output terminal and the connection point of the ninety-first tenth IGFET 'Ik of the other channel. A twelfth IGFET e is inserted in series between the first output terminal and the second potential supply terminal to form a first unit by inserting it into a thirteenth rGFET' of the 41-way channel; The 14th, 15th and 15th channels of one channel are connected between the first potential supply end and the second output end. 16th IGF
A 17th IGFET 'e of one channel is inserted in series between the first potential supply terminal and the second output terminal.
18. of the other channel between the second output terminal and the second potential supply terminal. No. 19. A 20th I GFET is inserted in series to connect the second output terminal and the first
9. A 21st IGFET 'e of the other channel is inserted between the connection point of the 20th IGFET to form a second unit, and between the first potential supply end and the third output end. and one channel of Mg2. A 23rd IGFET is inserted in series, and a 24th IGFET of the other channel is inserted between the third output terminal and the second potential supply terminal to form a third unit, and the fourth ．． A J-scar signal is supplied to the dart of the eighth IGFET, and the sixth IGFET is supplied with a J-scar signal. 11th IGF
An input signal is supplied to the dirt of the ET through the 16th. The output signal of the first unit is supplied to the dart of the eighteenth I GFET, and the third, twelfth .
The output signal of the 20th unit is supplied to the dart of the 23rd fGFET, and the 5th. 9th. 15th I GFET
The output signal of the third unit is supplied to the dart of the first unit. dart of the thirteenth IGFET and the seventeenth IGFET. The set signals are supplied to the darts of the 20th I GFET in an inverse relationship to each other. The dart of the tenth IGFET and the fourteenth IGFET. A reset signal is supplied to the dart of the 21st I GFET in an inverse relation to each other, and
．． 22nd. A dynamic section configured by supplying a one-phase i4 pulse signal to the dart of the 24th I GFET, and a 25th I GFET of one channel between the first potential supply end and the fourth output end.
．． A 26th IGFET is inserted in series and the 4th IGFET is inserted in series.
The 27th and 28th IGFETs of the other channel are inserted in series between the output terminal of M1 and the second potential supply terminal to form a fourth unit, and the potential supply terminal of M1 and the fifth output 29. of one channel between the ends. A fifth unit is formed by inserting a third O IGFET in series and a thirty-first IGFET of the other channel between the fifth output terminal and the second potential supply terminal; A 32nd IGFET of the other channel is inserted between the third output terminal of the third unit and the second potential supply terminal, and the second
5. The output signal of the third unit is supplied to the dart of the IGFET of the 30° button 31. 12th. 23rd
゜No. 26. 27th. The output signal of the fifth unit is supplied to the dart of the 32nd IGFET, and the 32nd IGFET
The output signal f of the second unit is supplied to the dart of the ET, and the 16th. The output signal of the fourth unit is supplied to the dart of the 18th I GFET, and the 28th. and a static part configured by supplying the first phase/Gurus master to the dart of the 29th IGFE'r, the output signal of the second unit being one output signal, and the one output signal and the above 7. 1. A one-phase static type J-flip-frozen circuit, characterized in that the output signal is ANDed with the reset signal supplied to the dart of a tenth IGFET and used as the other output signal. (2) Between the first potential supply end and the first output end, the first. Second. Third. A fourth IGFET is inserted in series and the second IGFET is inserted in series. The fifth IGFET of one channel is connected between the connection point of the third IGFET and the first output terminal. 6th IGFET
A seventh IGFET of one channel is inserted in series between the connection point of the first and second IGFETs and the first output terminal.
T'! and the eighth. of the other channel between the first output terminal and the second potential supply terminal. 9th. 10th
IGFETs are inserted in series between the first output terminal and the ninth output terminal.
, the connection point of the 10th I GFET and the 11th GFET of the other channel. A twelfth IGFET is inserted in series, and a thirteenth IGFET 'e of the other channel is inserted between the first output terminal and the second potential supply terminal to constitute a first unit; The 14th and 15th channels of one channel are connected between the potential supply terminal of the channel and the second output terminal of the channel. A 16th IGFET is inserted in series, and a 17th IGFET 'i of one channel is inserted between the first potential supply end and the second output end, and the second output end and the second potential 18 of the other channel between the supply end and the supply end. No. 19. 20th 5-IGFET 'fl: inserted in series and the 21st IGFET 'ii of the other channel inserted between the second output terminal and the connection point of the 19th and 20th IGFETs to form a second unit 22. of one channel between the first potential supply end and the third output end. 23rd IGFET
'i series insertion and the third output end and the second
the 24th IGFE of the other channel between the potential supply end of
T'i is inserted to form a third unit, a J input signal is supplied to the dart of the 41st and 8th IGFET via an inverter, and an input signal is supplied to the dart of the 61st and 11th IGFET. and the 16th. 18th IGFE
The output signal of the first unit body is supplied to the darts of the third, twelfth . The output signal of the second unit is supplied to the dart of the twenty-third IGFET, and the fifth. 9th, 1st
All the output signals of the third unit are supplied to the dart of IGFET No. 5, and The dart of the 13th I GFET and the 17th. A reset signal is supplied to the dart of the 20th IGFET in an inverted relationship with respect to the 7th IGFET. 10th I
6-G of GFET and the 14th. A set signal is supplied to the dart of the 21st IGFET in an inverted relationship with respect to the second, 19th, .
22nd. A dynamic section that supplies a 1-phase/1,000-pulse signal to the dart of the 24th IGFET is connected to the 25th IGFET of one channel between the first potential supply end and the fourth output end. A 26th IGFET is inserted in series, and 27th and 28th IGFETs of the other channel are inserted in series between the fourth output terminal and the second potential supply terminal to form a fourth unit. 29. of one channel between the first potential supply terminal and the fifth output terminal. A 30th IGFET is inserted in series, and a 31st IGFET of the other channel is inserted between the fifth output terminal and the second potential supply terminal.
f: insert to form a fifth unit, insert a 32nd IGFET of the other channel between the third output end of the third unit and the second potential supply end, and 25th. 30° An output signal of the third unit is supplied to the dart of the 31st IGFET, and the third unit. 12th. 23rd degree 2nd
6. 27th. The output signal of the fifth unit is supplied to the dart of the 32nd IGFET, the output signal of the second unit is supplied to the dart of the 32nd rGFET, and the output signal of the second unit is supplied to the dart of the 32nd rGFET. The output signal of the fourth unit is supplied to the dart of the 18th IGFET, and the 28th. 29th IGFET
a static section configured by supplying the one-phase pulse signal to the dirt of the second unit, the output signal of the second unit being one output signal, and this one output signal and the first output signal. 1st
1. A one-phase static type J-Frizzo-Flotsuno circuit, characterized in that the other output signal is obtained by performing a logical product with the reset signal supplied to the dart of IGFET No. 3. (3) Between the first potential supply end and the first output end, the first. 21st 3rd. A fourth IGFET is inserted in series and the second IGFET is inserted in series. The fifth IGFET of one channel is connected between the connection point of the third IGFET and the first output terminal. 6th rGFET
'ff: A seventh IGFET 'e of one channel is inserted between the connection point of the first IGFET and the first output terminal, and the first output terminal and the second IGFET are inserted in series. 8. of the other channel between the potential supply end and the potential supply end. 9th.
A tenth IGFET is inserted in series between the first output terminal and the W connection point of the ninth and tenth IGFETs of the other channel. A twelfth IGFET is inserted in full series, and a thirteenth rGFET 'i of the other channel is inserted between the first output terminal and the second potential supply terminal to form a first unit, and the first The 14th and 15th channels of one channel are connected between the potential supply terminal of the channel and the second output terminal of the channel. 16th IGFET
are inserted in series, and a 17th IGFET of one channel is inserted between the first potential supply terminal and the second output terminal, and between the second output terminal and the second potential supply terminal. 18 of the other channel. No. 19. 20th IGF
ET' in series with the second output terminal and the nineteenth,
A 21st IGFET i of the other channel is inserted between the connection point of the 20th IGFET to form a second unit;
Between the first potential supply end and the third output end, there is a 22nd. A 23rd IGFET 'e ti string is inserted between one end of the third output 9 and the second potential supply end of the other channel.
4 IGFETs are inserted to form a third unit; The J input signal is supplied to the dart of the ninth IGFET, and the fifth. An input signal is supplied to the dart of the 12th I GFET via an inverter, and the input signal is supplied to the dart of the 15th I GFET. 19th
The output signal of the first unit is supplied to the dart of the I GFET of the fourth, eleventh, . The output signal of the second unit is supplied to the dart of the twenty-second IGFET, and the sixth
．． The output signal of the third unit is supplied to the darts of the eighth and sixteenth IGFETs; 13th IGFET
The dirt and the 17th. The set signals are supplied to the darts of the 20th IGFET in an inverse relationship to each other, and the 7th IGFET. 1017th) IGFET (711''-) and the darts of the 14th and 21st IGFETs are supplied with reset signals in an inverse relationship to each other, and one phase is supplied to the darts of the second, 18th, 23rd and 24th IGFETs. A dynamic section supplying a pulse signal, and 25th and 26th IGs of one channel are connected between the first potential supply terminal and the fourth output terminal.
FET10- are inserted in full series and the 27th and 28th I of the other channel are inserted between the fourth output terminal and the second potential supply terminal.
GFET' in series to form a fourth unit, and the 29th. 30th IGFET'! f is inserted in series, and a 31st IGFET 'ii of the other channel is inserted between the fifth output terminal and the second potential supply terminal to form a fifth unit, and the third unit A 32nd IGFET of the other channel is inserted between the third output terminal of the 26th . 29th 3rd
The output signal of the third unit is supplied to the dart of the fourth IGFET. 11th. 22nd゜25th. 28th
．． The output signal of the fifth unit is supplied to the dart of the 32nd IGFET, the output signal of the second unit is supplied to the dart of the 32nd IGFET, and the output signal of the second unit is supplied to the dart of the 32nd IGFET. 1st
The output signal of the fourth unit is supplied to the dart of the 27th IGFET. a static section configured by supplying the one-phase pulse signal to the dart of a 30th I GFET; the output signal of the second unit is used as one output signal; 7th. 10th I
1. A one-phase static type J- frizzo-frozzo circuit, characterized in that the other output signal is obtained by performing an AND with the reset signal supplied to the dart of a GFET.