JPS60127761A - Manufacture of mos transistor - Google Patents
Manufacture of mos transistorInfo
- Publication number
- JPS60127761A JPS60127761A JP23668383A JP23668383A JPS60127761A JP S60127761 A JPS60127761 A JP S60127761A JP 23668383 A JP23668383 A JP 23668383A JP 23668383 A JP23668383 A JP 23668383A JP S60127761 A JPS60127761 A JP S60127761A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- thin film
- gate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体集積回路（以下ＬＳＩという）特に高
密度ＬＳＩに用いる微細素子の製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing fine elements used in semiconductor integrated circuits (hereinafter referred to as LSIs), particularly high-density LSIs.
従来例の構成とその問題点
ＭｏＳ）ランジヌタの微細化に伴ないドレインの電界が
強くなる為Ｌ Ｄ Ｄ （ｌｉｇｈｔｔｙＤｏｐｅｄＤ
ｒａｉｎ−ｓｏｕｒｃｅ ）やＤ Ｄ （Ｄｏｕｂ４ｅ
ＤｉｉｆｆｕｓｅｄＤｒａｉｎ ）構造を使用せざる
を得なくなっている。Conventional configuration and its problems
rain-source ) and D D (Doub4e
DiffusedDrain) structure.
従来このＬＤＤ構造を形成する為の１例を第１図に沿っ
て説明する。An example of conventionally forming this LDD structure will be explained with reference to FIG.
第１図乙において１はＰ型のシリコン基板、２はゲート
酸化膜、３は多結晶シリコンのゲート電極、４は低濃度
部のソースドレインの為のｎ型イオンビーム、６がソー
ス及びドレインである。５は酸化膜分離である。ｂの工
程では７の高温堆積酸化脂形成する。この膜を異方性ド
ライエツチングによシエッチングして、Ｃ工程８のザイ
ドゥオー／Ｖを形成する。その後９のｎ型不純物イオン
注入によＩ）１○のソースドレインをＬＤＤ構造とする
。In FIG. be. 5 is oxide film separation. In step b, high temperature deposited oxidized fat 7 is formed. This film is etched by anisotropic dry etching to form Zyduo/V in step C8. Thereafter, by implanting n-type impurity ions in step 9, I) the source and drain in step 1 are made into an LDD structure.
しかしながら上記の例では、高温堆積酸化膜が一般的に
堆積レ−１・が遅いことと、第１図Ｃ工程とするドライ
エツチング時に、終点を均一性よく制御することが難し
く、ソースドレイン表面に結晶欠陥が生じやすくなる等
の問題点を有している。However, in the above example, the high-temperature deposited oxide film generally has a slow deposition rate, and it is difficult to control the end point with good uniformity during dry etching as shown in step C in Figure 1. It has problems such as crystal defects are likely to occur.
さらには、サイドウオールの幅を均一性良くパターンを
出すことにも問題があり、高密度ＬＳＩをつくる」−で
困難であった。Furthermore, there was also a problem in creating a pattern with good uniformity in the width of the sidewalls, making it difficult to create high-density LSIs.
ところで、本発明者等はゲート電極を選択酸化すること
によシゲート電極の端部に均一性良くテーパを形成でき
ることを見出し、その結果、１回のイオン注入でＬＤＤ
構造のＭＯＳＩ・ランシスタを形成できることを見出し
、その結果高密度ＬＳＩに利用できることを見出した。By the way, the present inventors have discovered that by selectively oxidizing the gate electrode, it is possible to form a taper with good uniformity at the end of the gate electrode, and as a result, it is possible to form an LDD with a single ion implantation.
It was discovered that it was possible to form a MOSI/Lancy transistor structure, and as a result, it was found that it could be used for high-density LSI.
発明の目的
本発明は、このような従来の問題に鑑み、ＬＤＤ構造の
ＭＯＳ）ランジスタを制御性良く形成する方法のＬＳＩ
の製造方法を提供することを目的とする。Purpose of the Invention In view of such conventional problems, the present invention provides an LSI of a method for forming an LDD structure MOS transistor with good controllability.
The purpose is to provide a manufacturing method for.
発明の構成
本発明は、シリコン基板に分画領域を形成した後に、ゲ
ート酸化膜、ゲート電極を形成し、その上に窒化膜を形
成し、この窒化膜にグー１〜パターンを形成する。その
後選択酸化によりグー１〜電極以外の部分の電極材料の
一部を酸化し、エツチングする。この後、窒化膜をマス
クとして異方性のエツチングを行ない、テーパ状のエツ
ジをもつゲート電極を形成する。そして窒化膜除去後ソ
ースドレインを形成する不純物イオンをイオン注入する
ことにより制御性良（ＬＤＤ構造を形成できるものであ
る。なおゲート電極には、多結晶シリコンや金属シリサ
イドが適当である。Structure of the Invention In the present invention, after forming a divided region on a silicon substrate, a gate oxide film and a gate electrode are formed, a nitride film is formed thereon, and patterns 1 to 1 are formed on this nitride film. Thereafter, a portion of the electrode material other than the electrode 1 is oxidized and etched by selective oxidation. Thereafter, anisotropic etching is performed using the nitride film as a mask to form a gate electrode with a tapered edge. After removing the nitride film, impurity ions for forming the source and drain are implanted to form a LDD structure with good controllability. Polycrystalline silicon or metal silicide is suitable for the gate electrode.
実施例の説明
第２図は本発明の第１の実施例におけるＬＤＤ構造のＭ
Ｏ８ＬＳＩの製造工程を示す。説明を容易にする為、従
来例と共通の構成要素の番号は、第１図と同じにしであ
る。以下第２図の工程図に沿って説明を行なう。DESCRIPTION OF EMBODIMENTS FIG. 2 shows M of the LDD structure in the first embodiment of the present invention.
The manufacturing process of O8LSI is shown. For ease of explanation, the components common to the conventional example are numbered the same as in FIG. The explanation will be given below along the process diagram shown in FIG.
工程ａは、Ｐ型（１００）シリコン基板に選択酸化によ
ｐｅｏｏ ｎｍの酸化膜形成を行なう。In step a, a peoo nm oxide film is formed on a P-type (100) silicon substrate by selective oxidation.
その上に２０ｎｍのゲート酸化膜２をｗｅｔ酸化によシ
形成を行なった。その上からゲート電極となるタングス
テンシリサイド薄膜１１を２０ ＯｎＩｎ全面に堆積を
行なった。その上を１○ｏｎｍ酸化しＳｉｎ、、 １２
を形成し１１００ｎ の窒化膜１３を堆積し、写真食刻
法によシこの薄膜をゲート上に残した。このときのゲー
ト長は１．６μｍで形成した。A 20 nm gate oxide film 2 was formed thereon by wet oxidation. A tungsten silicide thin film 11, which would become a gate electrode, was deposited over the entire surface of the 20 OnIn film. Oxidize 10onm on top of it to give Sin, 12
A nitride film 13 of 1100 nm was deposited, and this thin film was left on the gate by photolithography. The gate length at this time was 1.6 μm.
次にｂ工程では、３○ｏｎｍの選択酸化を穐こし酸化膜
１４を形成した。この酸化膜を弗酸を含む湿式エツチン
グで除去したのち、窒化膜をマスクとして異方性エツチ
ングによシ残留した薄膜シリサイドをエツチングし、Ｃ
工程に示す形状を形成しテーパをもったゲート電極１５
を形成した。Next, in step b, selective oxidation of 30 onm was performed to form an oxide film 14. After this oxide film was removed by wet etching containing hydrofluoric acid, the remaining thin film silicide was etched by anisotropic etching using the nitride film as a mask.
Gate electrode 15 formed into the shape shown in the process and having a taper
was formed.
ここで形成されたテーパのゲート電極は、ｄ工程におけ
るイオン注入時に、ソースドレインのゲート電極近くの
ソースドレインの濃度がゆるやかに低下し浅くなる効果
をつくる。The tapered gate electrode formed here creates the effect that the concentration of the source/drain near the gate electrode gradually decreases and becomes shallower during ion implantation in step d.
ｄ工程において窒化膜を除去後Ａ８イオンを６ＱｋｅＶ
の加速エネルギーで４Ｘ１０ ｎ、、Ｉ””イオン注入
し、９５０℃３０分の熱処理を施こすことによｐＬＤＤ
構造のドレインをもつＭＯＳＩ・ランシヌタを形成した
。After removing the nitride film in step d, A8 ions are heated to 6QkeV.
By implanting 4×10 n, I'' ions with an acceleration energy of
A MOSI lancinuta with a drain structure was formed.
以上のように本実施例によれば、ゲート電極１１の利質
をタングステンシリサイドとしだが、ポリシリコンやそ
の他の金属シリサイド例えばモリブデンシリサイド等に
ついても酸化雰囲気中でＳｉＯ２となるので、タングス
テンシリサイドと同様に用いることが可能である。As described above, according to this embodiment, the main material of the gate electrode 11 is tungsten silicide, but since polysilicon and other metal silicides such as molybdenum silicide also become SiO2 in an oxidizing atmosphere, the same It is possible to use
発明の効果
本発明により作成したＭＯ５ＬＳＩは、ＬＤＤの端部の
濃度勾配の均一性が高い。そのバラツキはチャンネル長
のバラツキになる為、素子のシキイ電圧（以下ｖｔ と
記す）のバラツキが、ＬＤＤの均一性となってあられれ
る。従来法のサイドウオール法によシ作成したものは１
枚の３インチウエバｒｌＪｆ Ｖｔ、が約Ｏ，ＳＶにオ
イテ、σが０．０３６Ｖであったのに対して本発明法に
より作成したチャンネ）Ｖ艮１．２μｍの微細ＭＯ５素
子は、σが０．０２２ Ｖと、改善され再現性均一性の
いずれも高い高密度Ｉ、ＳＩを実現できるものである。Effects of the Invention The MO5LSI produced according to the present invention has a highly uniform concentration gradient at the end of the LDD. Since this variation becomes a variation in channel length, the variation in the threshold voltage (hereinafter referred to as vt) of the element becomes the uniformity of the LDD. The one created using the conventional sidewall method is 1.
While a 3-inch wafer rlJfVt, had a value of approximately O.SV and σ of 0.036V, the fine MO5 element with a channel) V of 1.2 μm prepared by the method of the present invention had a σ of 0.036V. 022 V, high density I and SI with improved reproducibility and uniformity can be realized.
第１図ａ −ｃは従来のサイドウオール形成法によシ作
成するＬＤＤＭＯ，Ｓｌ・ランジヌクの製造工程断面図
、第２図ａ〜ｄは本発明の実施例のＭＯＳＬＳＩの製造
工程断面図である。
１・・・・・シリコン基板、２・・・・・・デー１−酸
化膜、１１・・・・・ゲート電極薄膜、１３・・・・・
・耐酸化膜（窒化膜） 、１６・・・・・・イオンビー
ム、１７・・・・・・Ｉ、ＤＤ構造ソース１ルイン。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名菓
１ 図
協 ２ 図
３Figures 1a to 1c are cross-sectional views of the manufacturing process of LDDMO, Sl/Lanjinuk, produced by the conventional sidewall forming method, and Figures 2a to d are sectional views of the manufacturing process of MOSLSI according to the embodiment of the present invention. . 1... Silicon substrate, 2... Day 1-oxide film, 11... Gate electrode thin film, 13...
- Oxidation-resistant film (nitride film), 16...Ion beam, 17...I, DD structure source 1 Ruin. Name of agent: Patent attorney Toshio Nakao and one other name
1 Zukyo 2 Diagram 3
Claims (4)
ゲート絶縁膜上にゲート電極薄膜を形成する工程、ｉＩ
ｉ：ｌ酸化性薄膜を選択的に形成する工程、前記ゲート
電極薄膜を所望の厚さにまで酸化する工程、前工程で形
成された酸化膜を除去する工程。 前記耐酸化性薄膜直下部分を除く前記ゲート電極薄膜全
エツチングする工程、上部よシソーヌおよびドレインを
形成するべくイオンの打ち込みを行なう工程゛を少なく
とも含むことを特徴とするＭｏＳ ｌ・ランジスタの製
造方法。(1) Step of forming a gate insulating film on the semiconductor substrate Step of forming a gate electrode thin film on the gate insulating film, iI
A step of selectively forming an i:l oxidizing thin film, a step of oxidizing the gate electrode thin film to a desired thickness, and a step of removing the oxide film formed in the previous step. A method for manufacturing a MoS l transistor, comprising at least the steps of: etching the entire gate electrode thin film except for the portion immediately below the oxidation-resistant thin film; and implanting ions from the top to form a sissonne and a drain.
とする特許請求の範囲第１項に記載のＭｏＳ−トランジ
スタの製造方法。(2) A method for manufacturing a MoS-transistor according to claim 1, characterized in that the oxidation-resistant thin film is a silicon nitride film.
とを特徴とする特許請求の範囲第１項に記載のＭＯ８Ｉ
−ランジスタの製造方法。(3) MO8I according to claim 1, characterized in that the gate electrode thin film is a metal silicide thin film.
- A method of manufacturing a transistor.
を特徴とする特許請求の範囲第１項に記載のＭｏＳ）ラ
ンジヌタの製造方法。(4) A method for manufacturing a MoS (MoS) lunge as set forth in claim 1, characterized in that the gate electrode material is a polycrystalline silicon thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23668383A JPS60127761A (en) | 1983-12-15 | 1983-12-15 | Manufacture of mos transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23668383A JPS60127761A (en) | 1983-12-15 | 1983-12-15 | Manufacture of mos transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60127761A true JPS60127761A (en) | 1985-07-08 |
Family
ID=17004226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23668383A Pending JPS60127761A (en) | 1983-12-15 | 1983-12-15 | Manufacture of mos transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60127761A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6232650A (en) * | 1985-08-05 | 1987-02-12 | Mitsubishi Electric Corp | Manufacture of semiconductor |
| US6001714A (en) * | 1996-09-26 | 1999-12-14 | Kabushiki Kaisha Toshiba | Method and apparatus for manufacturing polysilicon thin film transistor |
| KR100320789B1 (en) * | 1993-01-18 | 2002-01-18 | 야마자끼 순페이 | A semiconductor device |
| US6551913B1 (en) | 1998-06-30 | 2003-04-22 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating a gate electrode of a semiconductor device |
| US6624473B1 (en) * | 1999-03-10 | 2003-09-23 | Matsushita Electric Industrial Co., Ltd. | Thin-film transistor, panel, and methods for producing them |
| US6884664B2 (en) | 2000-10-26 | 2005-04-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US6909114B1 (en) * | 1998-11-17 | 2005-06-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having LDD regions |
| US6949767B2 (en) | 1998-11-25 | 2005-09-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US6979603B2 (en) | 2001-02-28 | 2005-12-27 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US7259427B2 (en) | 1998-11-09 | 2007-08-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
-
1983
- 1983-12-15 JP JP23668383A patent/JPS60127761A/en active Pending
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6232650A (en) * | 1985-08-05 | 1987-02-12 | Mitsubishi Electric Corp | Manufacture of semiconductor |
| US6984551B2 (en) | 1993-01-18 | 2006-01-10 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device and method of fabricating the same |
| KR100320789B1 (en) * | 1993-01-18 | 2002-01-18 | 야마자끼 순페이 | A semiconductor device |
| US6417543B1 (en) | 1993-01-18 | 2002-07-09 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device with sloped gate, source, and drain regions |
| US7351624B2 (en) | 1993-01-18 | 2008-04-01 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device and method of fabricating the same |
| US6001714A (en) * | 1996-09-26 | 1999-12-14 | Kabushiki Kaisha Toshiba | Method and apparatus for manufacturing polysilicon thin film transistor |
| US6551913B1 (en) | 1998-06-30 | 2003-04-22 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating a gate electrode of a semiconductor device |
| US7279711B1 (en) | 1998-11-09 | 2007-10-09 | Semiconductor Energy Laboratory Co., Ltd. | Ferroelectric liquid crystal and goggle type display devices |
| US7259427B2 (en) | 1998-11-09 | 2007-08-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US9627460B2 (en) | 1998-11-17 | 2017-04-18 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a semiconductor device |
| US7172928B2 (en) | 1998-11-17 | 2007-02-06 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a semiconductor device by doping impurity element into a semiconductor layer through a gate electrode |
| US6909114B1 (en) * | 1998-11-17 | 2005-06-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having LDD regions |
| US8957422B2 (en) | 1998-11-17 | 2015-02-17 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a semiconductor device |
| US7564059B2 (en) | 1998-11-25 | 2009-07-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with tapered gates |
| US6949767B2 (en) | 1998-11-25 | 2005-09-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US6624473B1 (en) * | 1999-03-10 | 2003-09-23 | Matsushita Electric Industrial Co., Ltd. | Thin-film transistor, panel, and methods for producing them |
| US6812490B2 (en) | 1999-03-10 | 2004-11-02 | Matsushita Electric Industrial Co., Ltd. | Thin-film transistor, panel, and methods for producing them |
| US7183144B2 (en) | 2000-10-26 | 2007-02-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US6884664B2 (en) | 2000-10-26 | 2005-04-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US7531839B2 (en) | 2001-02-28 | 2009-05-12 | Semiconductor Energy Laboratory Co., Ltd. | Display device having driver TFTs and pixel TFTs formed on the same substrate |
| US6979603B2 (en) | 2001-02-28 | 2005-12-27 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US8017951B2 (en) | 2001-02-28 | 2011-09-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including a conductive film having a tapered shape |
| US8242508B2 (en) | 2001-02-28 | 2012-08-14 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
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