JPS60120463A - Multiprocessor system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a multiprocessor system that includes a parent processor and a child processor and has improved reliability.

Prior Art and Problems Various (1) configurations are already known for multiprocessor systems, such as a configuration in which distributed processing is performed using all microprocessors with the same configuration, or a configuration in which a parent processor is determined. There are configurations in which child processors are managed and processes are executed by dividing functions among them. Also known is a configuration in which the parent processor has higher functionality than the child processors, complex processing is performed by the parent processor, and other processing is distributed among the child processors.

Such multiprocessor systems have common devices such as common memory and common input/output devices that can be accessed by each processor, and these common devices have failure detection functions such as parity check functions. When a failure is detected, there are two methods: one to notify the processor accessing the common device, and the other to notify the parent processor.

In the former method, when a child processor with a low fault handling capability receives a fault detection signal from the common device, the child processor performs processing using the low fault handling capability and does not notify the parent processor with a high fault handling capability (2 ) It is necessary to In this case, if the child processor accesses the faulty location again before the fault processing in the parent processor is completed, it is generally not possible to notify the parent processor that has already notified the fault occurrence. Therefore, since it is not possible for the child processor to access the faulty location again, there is a drawback that the system may go down due to program runaway or the like.

The latter method has the advantage that the parent processor can immediately recognize the occurrence of a fault in the common device, but if the child processor continues to operate as it is, it will access the fault again and send the fault detection signal again. In this case, the failure analysis process in the parent processor will be interrupted, and in the worst case, the program will run out of control and the system will go down.

OBJECTS OF THE INVENTION The present invention provides a multiprocessor system having a child processor and a parent processor with a higher fault handling capability than the child processor, in which: The process is executed, while the preprocessor function is stopped to prevent the program from running out of control due to a failure on the child processor.
The purpose is to improve the reliability of the system.

Structure of the Invention The present invention provides a multiprocessor system having a child processor, a parent processor having a higher failure detection function than a core child processor, and a common device such as a common memory accessed by the child processor and the parent processor. A fault handling unit is provided that stops the child processor in response to a fault occurrence signal such as a parity error of a common device, notifies the parent processor of the fault occurrence, and restarts the child processor after the fault countermeasure processing of the parent processor is completed. All failure handling is performed by the parent processor to prevent program runaway due to the child processor's poor failure handling capabilities. Examples will be described in detail below.

Embodiment (4) of the invention FIG. 1 is a block diagram of an embodiment of the invention, in which 1 is a parent processor (MCPU), 2 is a local memory of the parent processor 1, 3 is a common memory (MEM), and 4 is a Child processor (SCPU), 5 is local memory of child processor 4, 6 is common peripheral device such as input device (Ilo), 7
is a failure handling unit, 8 is a local bus of parent processor 1, and 9 is a local bus of parent processor 1.
is a common bus, lO is a common memory failure detection signal line, 11
12 is a fault detection signal line for the common peripheral device 6; 12 is a fault detection signal line for the local memory 5; 13 is a control signal line for the child processor 4; and 14 is a signal line for the parent processor 1. Parent processor 1 has a failure handling function that is child processor 4.
It is of higher quality and has, for example, a function to detect illegal commands.

Further, the common memory 4 and the common peripheral device 6 are connected to the parent processor 1.
The local memory 2 is accessed only by the parent processor 1, and the local memory 5 is accessed only by the child processor 4. In addition, the fault processing unit 7 receives the fault detection signal and notifies the parent processor 1 of the occurrence of the fault (5) and stops the operation of the child processor 4, so that when the fault is recovered by the fault processing in the parent processor 1, It has a configuration that performs control to restart the operation of the child processor 4.

When the parent processor 1 or the child processor 4 accesses the common memory 3 or the common peripheral device 6, if a fault is detected due to a parity error or the like, the fault detection signal line 10.1
A fault detection signal is applied to the fault processing section 7 via the fault processing section 1.

When a failure due to a parity error or the like is detected when the father/child processor 4 accesses the local memory 5, a failure detection signal is applied to the failure processing unit 7 via the failure detection signal line 12. This fault processing unit 7 has a fault detection signal line 10.
, 11. When a fault detection signal is received through one or more of the signal lines 11 and 12, the function of the child processor 4 is stopped via the control signal line 13, and at the same time, the function of the child processor 4 is stopped via the control signal line 13.
This notifies the parent processor 1 of the occurrence of a failure.

The parent processor 1 executes the fault processing program (6) by interrupting the fault occurrence notification via the signal line 14, and performs fault location search, fault recovery processing, etc. When the fault recovery processing is completed, the fault processing program (6) The failure processing unit 7 is notified of the completion of failure recovery processing. The failure processing unit 7 thereby restarts the child processor 4 via the control signal line 13.

Further, if a failure occurs again while the parent processor 1 is executing the failure handling program, for example, if the parent processor 1 accesses the common memory 3 and a failure detection signal due to a parity error etc. is applied to the failure processing unit 7, The parent processor 1 is notified of the occurrence of a failure through the signal line 14, but in this case, it is determined that the failure is occurring during the execution of the failure handling program, so it is determined that it is impossible to continue executing the failure handling program, and the parent processor 1 will also stop the operation and send out an alarm.

FIG. 2 is a block diagram of the main parts of the fault processing section 7, in which fault detection signal lines 10, 11 . ! The receiving circuit 21 connected to the processor 2 and the receiving circuit 21 stop the operation of the child processor 4 by receiving a failure detection signal, and restart the operation of the child processor 4 by the notification of failure recovery from the parent processor 1. It includes a control signal sending circuit 22 and a circuit 23 that notifies the parent processor 1 of the occurrence of a failure by receiving a failure detection signal. For example, when the control signal sent to the control signal line 13 is "1°", the child processor main/tsusa 4 is in the operating state, and when it is "O", the control signal is in the stopped state.
．． In case of Hagi state, the control signal sending circuit 22 is configured with a → flip-flop, and it is normally set and sends a control signal of "1" to the control signal vA13, and when the receiving circuit 21 receives a fault detection signal, it is reset. “0” by
A control signal is sent to the control signal line 13 to stop the child processor 4, and when the failure processing of the parent processor 1 is completed and the failure is recovered, a control signal from the parent processor 1 is sent to the control signal line 13 via the signal line 14. When set by a signal, a control signal of "1" is sent to the control signal line 13, and the child processor 4 resumes operation. Also, the receiving circuit 21
When the fault detection signal is received by the processor 1, the parent processor 1 is notified of the fault occurrence via the circuit 23.

FIG. 3 shows a flowchart (8) of the embodiment of the present invention, in which the failure processing unit 7 uses the common memory 3. The presence or absence of a failure detection signal from the common peripheral device 6, etc. is monitored, and if a failure occurs, the child processor is stopped, the parent processor is notified of the failure occurrence, and the parent processor executes the failure handling program upon notification of the failure occurrence to recover from the failure. This restarts the child processor.

Although the above-described embodiment shows a case in which there is only one child processor 4, the present invention can also be applied to a multiprocessor system consisting of a parent processor 1 and a plurality of child processors.

Of course, the present invention can also be applied to a system in which a plurality of common peripheral devices 6 are provided.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention provides a multiprocessor having a parent processor 1 having a higher failure detection function than a child processor 4, and a common device such as a common memory 3 that is accessed by the child processor 4 and the parent processor 1. In the system, when a fault is detected, the fault processing unit 7 stops the operation of the child processor with a low fault handling function (9), and causes the parent processor with a high fault handling function to perform the fault handling. Because of this, a child processor with a low fault handling function is separated from the system, and program runaway due to the child processor accessing the faulty part again can be prevented. Therefore, there is an advantage that the reliability of the system can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a main part of a failure processing section, and FIG. 3 is a flowchart of an embodiment of the present invention. 1 is the parent processor (MCPU), 2 is the parent processor 1
3 is a common memory (MEM), 4 is a child processor (SCPU), 5 is a local memory of the child processor 4, 6 is a common peripheral device such as an input device (Ilo), 7 is a failure 8 is a local bus of the parent processor 1; 9 is a common bus; 10 is a failure detection signal line of the common memory; 11 is a failure detection signal line of the common peripheral device 6;
12 is a failure detection signal line for the local memory (10) 5; 13 is a control signal line for the child processor 4; and 14 is a signal line for the parent processor 1. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Shoji Aitani Representative Patent Attorney Hiroshi Watanabe - (11) Figure 1

Claims (1)

[Claims] In a multiprocessor system that includes a child processor, a parent processor that has a higher failure detection function than the child processor, and a common device such as a common memory that is accessed by the child processor and the parent processor, parity errors, etc. of the common device may occur. The present invention is characterized by further comprising a fault processing unit that stops the child processor in response to a fault occurrence signal, notifies the parent processor of the fault occurrence, and restarts the child processor after the fault countermeasure processing of the parent processor is completed. multiprocessor system.