JPH01319834A - microcomputer - Google Patents

Abstract

PURPOSE:To minimize the recovery processing time by detecting the abnormality and run-away of a program executed by a central processing unit with the overflowing of a counting means and using a watch dog timer capable of selecting the object function to reset based on the overflowing. CONSTITUTION:When the recovery from a failure is preferentially re-started from the initial setting of a system as a whole, the selecting condition of a function module and the resetting mode of the function module are given to a watch dog timer 7 so that the object to reset based on the overflowing of a counting means 18 is all the function modules including a central processing unit 1. The watch dog timer 7 to set such a selecting condition, when the overflowing of the counting means 18 is detected, resets the whole of a data processing LSI chip, outputs a resetting signal for an external peripheral circuit in accordance with the necessity, and based on this, the central processing unit 1 starts the resetting exception processing and restarts the initial setting of the system. Thus, the recovery processing time can be minimized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing system equipped with a watchdog timer for detecting system abnormality based on an abnormal loop or runaway of a program executed by a central processing unit. relates to a reset process therein, and relates to a technique that is effective when applied to, for example, a single-chip microcomputer with a built-in watchdog timer.

[Prior art]

In data processing systems that include data processing LSIs (Large Scale Integrated Circuits) such as single-chip microcomputers, it is necessary to detect failures as soon as they occur in order to prevent situations such as system stoppages or runaways. ,
It is necessary to keep the spread to a minimum. Conventionally, as means for detecting abnormalities in the system and returning the system to a normal state, methods have been adopted, such as using a watchdog timer or executing a reset command.

When using a watchdog timer, under normal conditions, the watchdog timer resets a counter at regular intervals via a software program, and an overflow of the counter may cause an abnormal loop or runaway of the program. However, in a conventional logic LSI incorporating such a watchdog timer, a detection signal of the occurrence of a failure by the watchdog timer is given to the central processing unit as a predetermined interrupt signal for exception processing.

In some devices, a failure detection signal from a watchdog timer is used as a signal to initiate a reset operation for the entire chip, similar to a reset operation via an external reset terminal.

Also, those that use a reset command to return to normal state,
Executing this instruction activates the reset operation of the entire chip.

An example of a document describing the watchdog timer is "R Microcomputer Handbook" P2S5, published by Ohm Publishing on December 25, 1985. In addition, an example of a document describing a microcomputer using a reset instruction is "Bessatsu Transistor Techniques 5PECIAL N" published by CQ Publishing on March 1, 1985.
There are o2JP2 to P152.

[Problem to be solved by the invention]

The present inventor has studied conventional techniques that utilize a watchdog timer or execute a reset command to detect abnormality in the system and return the system to a normal state.

When using a reset command to return to a normal state, when the operating program of the system goes out of control, the microcomputer (or microprocessor) must be caused to execute the reset command via some external means. . By the way, the bus release state or wait state of the microcomputer may become deadlocked due to some external failure factor. However, in such a deadlock state, the central processing unit is unable to execute any instructions, not just the reset command, so if the bus release state or external wait state enters a deadlock state, it is simply a reset. Instructions cannot return the deadlock state to normal. In order to deal with such a deadlock state, a new circuit must be added outside the microcomputer to cut off the wait request signal and the pass right request signal so that the reset command can be executed.

If the overflow signal of the watchdog timer is simply given to the central processing unit as a predetermined exception handling interrupt signal, the central processing unit is required to execute its interrupt handling routine, so this technique is similar to the technique using the reset instruction described above. It is not possible to easily restore a bus release state or an external wait state that has entered a deadlock to a normal state.

Furthermore, if the overflow signal of the watchdog timer is used as a signal to start a reset operation of the entire chip in the same way as a reset operation via an external reset pin, the above-mentioned problem of recovery from a deadlock state can be solved. overcome, but because the entire system is reset even in cases where deadlock is the only failure factor.

A new problem arises in that recovery processing for restarting the system takes time.

Moreover, resetting the entire microcomputer chip using such a method takes priority over all states of the microcomputer chip, including its instruction execution state and bus cycle, and is performed asynchronously, regardless of these, so there is no need to interrupt the bus cycle. There is also a risk that the contents of memory may be randomly destroyed. For example, when a memory write operation is performed by outputting an address signal from an input/output port, if the entire chip is reset, the write control signal is negated in response and the port is in a high output impedance state. be made into A predetermined propagation delay occurs before the change in the write control signal that is negated at this time is completely transmitted to the external memory, and during this time, the input/output port is If the output of an uncertain address is taken into memory, there is a risk that data will be destroyed at multiple unspecified addresses.

In this way, individual conventional technologies that use a watchdog timer or execute a reset command to detect system abnormality and process a return to a normal state cannot easily recover from a deadlock. Even if it is possible to recover from a deadlock, there is a risk that memory contents may be randomly destroyed due to bus cycle interruption, and furthermore, recovery processing may take time. For this reason, it is not possible to optimize all of the recovery processes from failures that are variously required in various systems using individual conventional technologies, and there is a need to waste time on recovery processes from failures that are required for the system. , unless a special circuit is provided externally, individual requirements for recovery processing cannot be satisfied.

An object of the present invention is to minimize the processing time for various recovery processes required by various systems in a data processing device that uses a watchdog timer to perform recovery processes from failures, and to individually perform external recovery processes. The objective is to provide a technology that can minimize and optimize the amount of hardware that must be added to the system.

Another object of the present invention is to provide a data processing device that can easily recover from a deadlock and can prevent memory contents from being randomly destroyed at that time.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a data processing device such as a single-chip microcomputer in which a central processing unit and other functional modules are formed on one semiconductor substrate, an abnormal loop or runaway of a program executed by the central processing unit is detected by an overflow of a counting means. However, a watchdog timer is used in which a target functional module to be reset can be programmably selected based on the overflow.

In addition, in a data processing device such as a single-chip microcomputer in which a central processing unit and other functional modules are formed on a single semiconductor substrate, an abnormal loop or runaway of a program executed by the central processing unit can be detected due to an overflow of a counting means. and a reset mode in which a predetermined functional module including a central processing unit is the target to be reset based on the overflow detected by the CPU, and a reset mode in which the target is a predetermined functional module not including the central processing unit. It employs a watchdog timer whose reset mode can be selected programmably.

At this time, it is preferable to programmably select a functional module to be reset in a reset mode in which a predetermined functional module that does not include the central processing unit is a reset target module.

Furthermore, in a reset mode in which a predetermined functional module that does not include a central processing unit is set as a reset target module, the interrupt controller is excluded from programmably selectable reset target modules, and in a reset operation of a functional module that can be selectively reset, In order to perform efficient recovery processing, it is desirable that the watchdog timer instructs the central processing unit to perform predetermined exception processing via the interrupt controller.

In the reset mode in which a predetermined functional module that does not include the central processing unit is the module to be reset, an input/output port that can output an address signal that changes to a high output impedance state in response to being reset is used. , it is desirable to exclude it from the selectable reset target modules in order to prevent undesired data destruction of the memory at the time of reset.

In the reset mode in which a predetermined functional module including the central processing unit is reset, a reset signal can also be output to the outside.

[For production]

According to the above-mentioned means, the reset operation by the watchdog timer performed based on the overflow of the counting means depends on the reset mode selectable in the watchdog timer and the selection state of the programmably selectable reset function module. Its contents are determined. The type of reset operation to be selected is determined depending on what is given top priority as recovery processing from a system failure.

System hardware or software failures, such as central processing unit deadlock caused by undesired locking of external wait or bus requests, as well as other failures such as those caused by power supply noise or surges. If the priority is to restart from the initial settings of the entire system in order to recover from any failure, the target to be reset based on the overflow of the counting means should be reset to all systems including the central processing unit. The selection state and reset mode of the functional module are given to the watchdog timer as if it were a functional module.When the watchdog timer to which such a selection state is set detects an overflow in the counting means, the single-chip micro Resets the entire data processing LSI chip, such as a computer, and outputs a reset signal for external peripheral circuits as necessary.Based on this, the central processing unit starts reset exception handling and restarts the initial settings of the system. do.

If you want to give top priority to recovering the central processing unit from a deadlock state caused by an external wait request or bus right request, you can exclude the central processing unit from resetting based on the overflow of the counting means and set the target to the bus arbiter or wait. As with the controller, the watchdog timer is given a selection state of the functional module and a corresponding reset mode. The watchdog timer to which such a selection state is set resets the bus arbiter and wait controller based on the overflow of the counting means, and thereby the central processing unit acquires the bus right and also controls the current bus cycle. Exit the deadlock by terminating without interruption. The central processing unit that has broken out of the deadlock state executes interrupt exception handling directly or indirectly instructed by the watchdog timer, and
Perform recovery processing.

In particular, when a deadlock state based on a wait request is released, terminating the bus cycle without interrupting the bus cycle prevents the data in the internal memory from being undesirably rewritten or destroyed. Furthermore, at this time, excluding output ports and input/output ports that can output address signals that are put into a high output impedance state by reset from the reset target module means that the address signal will be output at the set timing based on the overflow of the watchdog timer. It maintains a port or an input/output port in an address signal output mode, and works to prevent data in the external memory from being undesirably destroyed during a transition period until the external memory is disabled. Furthermore, the fact that the watchdog timer instructs its own interrupt exception handling serves to eliminate the need to analyze the cause of the failure, thereby omitting the step for analyzing the cause.

In this way, the selectivity of the reset operation by the watchdog timer minimizes the processing time for the various recovery processes required for various systems, and also minimizes the amount of hardware that must be individually added externally. It also works to facilitate recovery from deadlock, and to prevent the memory contents from being randomly destroyed at that time.

〔Example〕

FIG. 1 shows a block diagram of a single-chip microcomputer that is an embodiment of the present invention. The single-chip microcomputer shown in the figure is manufactured using a single chip such as a silicon substrate using known semiconductor integrated circuit manufacturing technology.
formed on individual semiconductor substrates.

The single-chip microcomputer shown in FIG. 1 includes, but is not limited to, a central processing unit (CPU) 1 and an interrupt controller 4 coupled to the central processing unit 1 via an internal data bus 2 and an internal address bus 3, respectively. ,
Path arbiter 5, wait controller 6, watchdog timer 7, free running timer 8, serial communication interface controller 9, RA
M (random access memory) 10, ROM (read only memory) 11, first port 12, and second port
A port 13 and further a system control circuit 14 are included.

The first port 12 is a set of input-only ports and output-only ports that are not put into a high output impedance state even when reset, and the second port 13 receives an address signal that is put into a high output impedance state when reset. It is used as an input/output port that can output.

The interrupt controller 4 is supplied with a non-maskable interrupt signal NMI and maskable interrupt signals IRQI, IRQ2 supplied from the outside via the first port 12, and also receives a watchdog timer 7, a free running timer 8, and internal interrupt signal RQ3. output from the serial communication interface controller 9, respectively. IRQ4. IRQ5 is given. The interrupt controller 4 provides the central processing unit 1 with a vector and an interrupt signal IRQ6 according to the type of interrupt signal supplied thereto according to the interrupt priority order. When the interrupt signal IRQ6 is asserted, the central processing unit 1 branches to interrupt exception processing corresponding to the vector applied at that time.

The path arbiter 5 samples the bus right request compensation signal BREQ supplied from the outside and arbitrates the bus right with an external path master module (not shown).

When the wait controller 6 detects that the main wait request signal WAIT supplied from the outside is asserted, it remains in a predetermined state until the wait request signal WAIT is negated in one machine cycle of the single-chip microcomputer. Controls the insertion of weights.

The system control circuit 14 has logic for receiving a reset signal RES, a standby signal 5TBY, and a mode signal MDo-MD2 from the outside to control the operating mode or internal state of the single-chip microcomputer.

This system control circuit 14 has a logic for resetting all functional modules included in the single-chip microcomputer in response to assertion of a reset signal RES supplied from the outside to a low level, and a logic for overflow of a watchdog timer door. It also has logic that asserts a reset signal to the outside based on the signal.

FIG. 2 shows an example of the above reset logic that the system control circuit 14 has.

According to FIG. 2, the input/output terminal 15 of the reset signal RES
is pulled up externally, and inside the system control circuit 14, an input buffer 16 having a hysteresis characteristic for receiving a reset signal RES supplied from the outside is coupled to its input/output terminal 15. , open drain structure discharge MO8
A FET 17 is interposed between the circuit and the ground terminal Vsg.

The output signal of the input buffer 16 is the internal reset signal φre.
s, to all functional modules included in the single-chip microcomputer. A reset signal φres1 output from the watchdog timer 7 is supplied to the gate electrode of the discharge MO3FET 17. This reset signal φres1 is a signal that is selectively asserted based on an overflow of a counter included in the watchdog timer 7, the details of which will be explained later.

Due to external action or discharge MOSF
When the reset signal RES is asserted to a low level due to the ON operation of the ET17, the internal reset signal φres outputted from the input buffer 16 is asserted to a high level, thereby all functions included in the single-chip microcomputer are activated. The module is reset, and in response to this, the central processing unit 1 executes exception processing to perform the recovery processing necessary for restarting the system.

FIG. 3 shows an example of the watchdog timer 7.

In the normal state, the watchdog timer 7 of this embodiment resets the counter 18 at regular intervals via a software program, etc., and detects an abnormal loop or runaway of the program due to an overflow of the counter 18. The control register 2o is used to instruct a predetermined reset operation, and includes a control register 2o for programmably selecting a target functional module to be reset based on, for example, an overflow.

This control register 20 includes, but is not limited to, a reset enable bit RESE for selecting an overall reset, a reset enable bit RESE for selecting a reset of the bus arbiter 5, and a reset enable bit RESE for selecting a reset of the wait controller 6. Bit RESE, Reset enable bit R for selecting reset of free-running timer 8.
E S E4. a reset enable bit RESE for selecting reset of the serial communication interface controller 9; a reset enable bit RESE for selecting reset of the first port 12;
A setting area for a reset enable bit RESE for selecting reset of the second port 13 is provided. Each reset enable bit RESE
The setting bit "1" in RESE means selection of reset operation.

The overflow signal of the counter 18 sets an overflow flag 21 consisting of a flip-flop. The output of the overflow flag 21 in the set state is logic rI
It is considered to be J.

Although not particularly limited, the logic gate 22 individually ANDs the output of the overflow flag 21 with each of the reset enable bits RESE1 to RESE, and when the result is logic "1", The reset signals φres□, ..., φres,
Assert. The reset signal φres is used to reset the entire system by turning on the discharge MO8FET 17 at its high level, the reset signal φreS2 resets the path arbiter 5 at its high level, and similarly, the reset signal φres is used at its high level. The reset signal φres4 activates the free running timer 8 with its high level, the reset signal φresS activates the serial communication interface controller 9 with its high level, and the reset signal φreSG activates the first port 12 with its high level. , the reset signal φr
eS resets the second boat 13 due to its high level.

When the bus arbiter 5 or the wait controller 6 is reset, even if the bus arbiter 5 or the wait request signal WAIT supplied thereto is in the asserted state, the asserted state of the signal is masked, and as a result, the central processing The bus right is returned to the device 1, and insertion of wait cycles or wait states by the central processing unit 1 is stopped.

The output of the overflow flag 21 is supplied to the interrupt controller 4 as the interrupt signal IRQ3. This interrupt signal IRQ3 is a dedicated interrupt signal for instructing the central processing unit 1 to perform exception processing for recovery from a failure factor detected by an overflow of the watchdog timer 7. Note that the set state of the overflow flag 21 is reset based on exception processing executed by the central processing unit 1.

The content of the reset operation performed by the watchdog timer 7 based on the overflow of the counter 18 is determined according to the selection state of a programmably selectable reset target function module in the watchdog timer 7.

The type of reset operation to be selected is determined depending on what is given top priority as recovery processing from a system failure.

Various system hardware and software failures,
For example, when a deadlock occurs in the central processing unit 1 due to an undesired locking of a wait request or a bus request from the outside, or other failures such as those caused by power supply noise or surges, However, if priority is given to restarting the initial settings of the entire system to recover from the failure, all functional modules including the central processing unit 1 are to be reset based on the overflow of the counter 18. In the control register 20, only the reset enable bit RESE1 is set to "1".

On the other hand, if you want to give top priority to recovering the central processing unit 1 from a deadlock state caused by an external wait request or bus request, exclude the central processing unit 1 from being reset based on the overflow of the counter 18. The reset enable bits RESE2 and RESE in the control register 20 are set to "1" so that the bus arbiter 5 and wait controller 6 can be configured to perform the same operation.

The timing chart in FIG. 4 shows a case where the reset mode is selected, which prioritizes recovery from any failure detected by the overflow of the counter 18 by restarting the initial settings of the entire system. An example of the operation is shown below. The reset mode is selected by setting only the reset enable bit RESE□ to "1" in the control register 20.

In FIG. 4, the overflow factor of the counter 18 is as follows:
Let us take as an example a case where the wait request signal WAIT is undesirably fixed at a low level (asserted level) and the central processing unit 1 becomes deadlocked.

A wait state TW is inserted from time t after the T2 state of the system clock, and when the number of insertions exceeds the maximum limit, the counter 18 overflows at time t2 due to the deadlock state of the central processing unit 1.

In the explanation based on FIG. 4, since only the reset enable bit RESE1 is set to "1" in the control register 20, only the reset signal φres1 is asserted in synchronization with the overflow of the counter 18, and this is gated. Discharge M received by the electrode
O8FETI7 turns on. The discharge MO8FET 17, which is turned on, receives the reset signal φres.
. is asserted at time t, thereby all the functional modules inside the single-chip microcomputer that receive the reset signal φreso are reset, and the discharge MOSFET 17 also outputs the reset signal to the outside via the input/output terminal 15. Assert RES. When the wait controller 6 is reset by the reset signal φres0, the wait request from the wait controller 6 to the central processing unit 1 is negated at time t, and insertion of the wait state TW is stopped.

At this time, since the central processing unit 1 is also reset at a timing synchronized with the negation of the reset signal φres0, the address signal is changed in synchronization with this and the write signal WT or read signal RD is also negated, resulting in a reset. The bus cycle is interrupted and terminated.

At a timing after this bus cycle ends, the central processing unit 1 executes reset exception handling and restarts the initialization of the system.

In this way, the wait request signal W given from the outside
Central processing unit with AIT fixed at low level 1. The deadlock will be resolved and the system will return to normal.

Although not particularly limited, in this embodiment, the second port 13 is also reset at the same time as the functional module including the central processing unit 1 is reset. The second port, which is an input/output port that can output an address signal, performs a reset operation using an externally applied reset signal RES during power-on reset, etc.
Even in the overall reset operation based on the overflow of the counter 18, its input/output terminals are controlled to a high output impedance state asynchronously with the system clock. During the transient period until the second port 13 is brought into a high output impedance state, an uncertain address output is given to the outside. If such an uncertain address output is taken into the external memory before the negated state of the write signal WT due to the interruption of the bus cycle is transmitted to the external memory (not shown), data will be lost at multiple unspecified addresses. There is a risk of destruction. Therefore, as a matter of course, the return processing in the reset mode is designed to take into account the possibility of such data destruction.

FIG. 5 is a timing chart showing an example of the operation when a reset mode is selected in which recovery from deadlock of the central processing unit 1 caused by the bus request signal BREQ or the wait request signal WAIT is selected. The reset mode is selected by setting only the reset enable bits RESE2 and RESE to "1" in the control register 20, respectively.

In FIG. 5, the overflow factor of the counter 18 is as follows:
Corresponding to FIG. 4, let us take as an example a case where the wait request signal WAIT is undesirably fixed at a low level (asserted level) and the central processing unit 1 becomes deadlocked.

A wait state TW is inserted from time t1 after the T2 state of the system clock, and when the number of insertions exceeds the maximum limit, the counter 18 overflows at time t2 due to the deadlock state of the central processing unit 1.

In the explanation based on FIG. 5, the control register 20 includes reset enable bits RESE2 and R.
Since only ESE is set to "1", only the reset signals φres2 and φres3 are asserted at time t in synchronization with the overflow of the counter 18, and as a result, the bus arbiter 5 and the wait controller 6
is put into a reset state. When the bus arbiter 5 is reset, the bus right is returned to the central processing unit 1 even if an external bus master module occupies the bus right. Furthermore, when the wait controller 6 is reset, the wait request from the wait controller 6 to the central processing unit 1 is negated at time t4, and insertion of the wait state TW is stopped. This allows the central processing unit 1 to fix the wait request signal WAIT given from the outside to a low level.
deadlock is resolved.

At this time, the central processing unit 1 has not been reset, so
Since the bus cycle is maintained until the final T3 state, the address signal is not changed until the bus cycle ends at time t5, and the write signal WT and read signal RD are also not changed until the T33 state is reached. continues to be asserted. That is, even if the bus arbiter 5 and wait controller 6 are reset, the current bus cycle is completed without being interrupted.

Further, the second port 13, which serves as an input/output port capable of outputting an address signal, is also not reset until at least the bus cycle ends at time t5.

Therefore, in the bus cycle when the bus arbiter 5 and the wait controller 6 are reset, the risk of erroneous writing or data destruction at multiple unspecified addresses in the memory is prevented.

Furthermore, when the counter 18 overflows at time t2 and the overflow flag 21 is set, the interrupt signal IRQ3 output from the watchdog timer 7 is asserted at time t21.

Central processing unit with deadlock resolved as described above! i! 1 ends the bus cycle at time t, accepts the interrupt processing based on the interrupt signal IRQ3, starts reset exception processing based on the overflow of the watchdog timer 7, and returns the system to the normal state. .

The exception handling at this time is the interrupt signal IRQ3 asserted due to the overflow of the watchdog timer 7.
, the central processing unit @1 can branch to a predetermined exception process without analyzing the cause of the failure at that time.

In this way, when such a reset mode is set in the watchdog timer 7, if the cause of the failure is a deadlock in the central processing unit 1 due to the bus request redemption signal BREQ or the wait request signal WAIT, the watchdog timer Reset signal φ1”eSzt output from timer 7
φres is the bus arbiter 5 and wait controller 6
is reset by hardware to eliminate the deadlock of the central processing unit 1, and the central processing unit 1, which has been made operational by this, performs a predetermined operation based on the interrupt signal IREQ3 output from the watchdog timer 7. The program branches to reset exception handling and performs reset processing for the external function module, etc. that is the cause of the deadlock.

Therefore, it is possible to recover from a deadlock with minimal processing, and since the central processing unit 1 and the second port 13 are not reset at that time, it is possible to prevent the memory contents from being randomly destroyed.

Note that if a reset mode is set in which the bus arbiter 5 and wait controller 6 are reset based on the overflow of the watchdog timer 7, the cause of the failure may be the bus right request redemption signal BREQ or the wait request signal WAI.
If the central processing unit 1 is not deadlocked due to T, for example, if the hardware is damaged due to a surge, the specific cause of the failure remains even after the processing is finished, but in this case, the number of resets etc. is counted. This may lead to countermeasures such as giving an external warning that it is impossible to return to the normal state.

According to the above embodiment, the following effects are obtained.

(1) The single-chip microcomputer of this embodiment resets the entire system or resets exclusively to eliminate deadlock, depending on the settings of the control register 20.

A reset operation based on an overflow of the watchdog timer 7 can be selectively set. This results in 1
In a single-chip microcomputer or a system that includes one, the top priority is given to recovery from any failure by restarting the initial settings of the entire system. In addition, it is possible to make a selection such as giving top priority to recovering the central processing unit 1 from a deadlock state caused by an external wait request or a bus right request.
When making this selection, it is only necessary to change the setting contents of the control register 20, and there is no need to add any special external hardware.

(2) When selecting a reset mode that gives top priority to recovering the central processing unit 1 from a deadlock state caused by an external wait request or bus right request, the central processing unit 1 is not reset; Since a branch to the reset exception processing to be executed by the central processing unit 1 is given by the interrupt signal IRQ3 output from the watchdog timer 7, the central processing unit 1 is capable of determining the cause of the failure, which is necessary for resetting the entire system. is unnecessary, and only the exception handling for the return processing, which is given the highest priority, needs to be executed. Therefore, in response to a failure that requires the system to be restored with the highest priority, it is possible to reduce the processing time by minimizing the recovery processing using exception handling to restart the system. Become.

(3) From the effects (1) and (2) above, it is possible to minimize the processing time for various recovery processes required on various systems, and to minimize the amount of hardware that must be individually added externally. can be optimized.

(4) When selecting a reset mode that gives top priority to recovering the central processing unit 1 from a deadlock state caused by an external wait request or bus right request, the central processing unit 1 is not targeted for reset. The bus cycle is maintained until the end, and since the second port 13, which is changed to a high output impedance state by being reset, is not subject to reset, the address signal output operation to the outside is not performed until the bus cycle is completed. This prevents data in the external memory from being undesirably destroyed or erroneously written during the transition period until the external memory is disabled when executing reset mode for the purpose of eliminating deadlock. This can prevent the possibility of such occurrence. In this regard, the same holds true for internal memories such as RAM10, since bus cycles are not interrupted.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

In the above embodiment, the case where the reset mode based on the overflow of the watchdog timer 7 is selected is the system-wide reset mode or the reset mode exclusively aimed at eliminating deadlock, but the central processing unit 1 and the interrupt controller 4 are In the latter reset mode in which the reset target is not set, other functional modules such as the free running timer 8 and the serial communication interface controller 9 may be included as the reset target.

In addition, in the above embodiment, a control register 2o is provided which can select and set whether or not to reset each functional module in one-to-one correspondence with various functional modules. A mode in which it is possible to select between a reset mode in which the entire system is reset and a reset signal RES is asserted externally, and a reset mode in which the bus arbiter 5 and the wait controller 6 are reset to eliminate deadlock. A register may also be provided. In addition, the reset operation selection method of resetting the entire internal function module based on the overflow of the watchdog timer and asserting the reset signal RES externally is based on the configuration in which the reset enable bit RESE□ is provided in the control register 2o of the above embodiment. Not limited.

Reset enable bits may be provided in a one-to-one correspondence with all functional modules, and a logic circuit may detect that all functional modules are set to logic "1" to select the relevant operation mode.

Nonvolatile storage means such as EPROM may be used as the control register 20 and mode register.

When the functions of the control register 20 and logic gate 22 are included in the system control circuit 14, such a circuit configuration can be regarded as an element constituting a watchdog timer.

Furthermore, the functional modules included in the single-chip microcomputer are not limited to the above embodiments and can be modified as appropriate.

The above explanation has mainly been about the case where the invention made by the present inventor is applied to a single-chip microcomputer, which is the field of application that formed the background of the invention.
The present invention is not limited thereto.

The present invention can be applied to data processing devices in general that have a processing function for monitoring abnormal loops or runaway programs and recovering from the failure when detected.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, the content of the reset operation by the watchdog timer is determined according to the reset mode that can be selected in the watchdog timer and the selection state of the programmably selectable reset target function module, so it is detected by an overflow of the watchdog timer. If the top priority is to restart the entire system from its initial settings in response to any failure that occurs, the target to be reset based on the overflow of the watchdog timer should be set to all systems, including the central processing unit. It is sufficient to set the selection state and reset mode of the functional module in the watchdog timer, such as setting the functional module as the functional module. If you want to give the highest priority, select a functional module such as a bus arbiter or wait controller to exclude the central processing unit from being reset based on the overflow of the watchdog timer, or select a corresponding reset mode. You can set it as a watchdog timer. Thereby, such various reset operations can be selected and set as necessary without adding any special external hardware.

When selecting a reset operation that gives top priority to recovering the central processing unit from a deadlock state caused by an external wait request or bus right request, the central processing unit is not reset; By providing a branch to the reset exception processing to be executed using the interrupt signal output from the watchdog timer 7, the central processing unit does not need to perform processing to determine the cause of a failure, which is required when resetting the entire system. It is sufficient to execute only the exception handling for the return processing given the highest priority.

Therefore, in response to a failure for which recovery is to be given top priority in the system, recovery processing by exception handling for restarting the system can be suppressed to the necessary minimum, and the processing time can be shortened.

Therefore, as a result of the above-mentioned effects, it is possible to optimize the recovery processing required in various systems by minimizing the processing time and minimizing the amount of hardware that must be individually added to the outside.

In addition, when selecting a reset mode that gives top priority to recovering the central processing unit from a deadlock state caused by an external wait request or bus request, the bus cycle at that time is is maintained until the end, and since ports that can output address signals that change to a high output impedance state when reset are not subject to reset, address signal output operations to the outside are not performed until the bus cycle is completed. This prevents data in the external memory from being undesirably corrupted during the transition period until the external memory is disabled when performing a reset operation where top priority is to resolve a deadlock. It is possible to prevent the possibility of erroneous writing, and since the bus cycle is not interrupted, it is possible to prevent undesired data from being written to the internal memory or data destruction.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a single-chip microcomputer that is an embodiment of the present invention, Figure 2 is a circuit diagram showing an example of reset logic included in a system control circuit, and Figure 3 is an example of a watchdog timer. Block Diagram. Figure 4 shows the operation when the reset mode is selected, which gives top priority to restarting the initial settings of the entire system in response to any fault detected by the overflow of the watchdog timer. A timing chart showing an example. FIG. 5 is a timing chart showing an example of the operation when a reset mode is selected to give top priority to recovery from a deadlock of the central processing unit due to a bus request or a wait request. 1...Central processing unit, 2...Internal data bus, 3.
...Internal address bus, 4...Interrupt controller,
5... Bus arbiter, 6... Wait controller, 7... Watchdog timer, 8... Free running timer, 9... Serial communication interface controller, 1o... RAM, 11...
ROM, 12... 1st port, 13... 2nd port, 14... System control circuit, 18... Counter, 20... Control register, RE S E
s~RE SE t...Reset enable bit, 21...Overflow flag, 22...Logic game h, BREQ...Bus request signal, WAIT...
Wait request signal, RES...reset signal, φre
s, ~φres, . . . reset signal, IRQ3. IR
Q6...Interrupt signal.

Claims (1)

[Scope of Claims] 1. A watchdog timer that detects an abnormal loop or runaway in a program executed by a central processing unit by an overflow of a counting means, and is capable of programmably selecting a target functional module to be reset based on the overflow. A data processing device comprising: 2. A predetermined target including a central processing unit and other peripheral function modules that detects an abnormal loop or runaway of a program executed by the central processing unit by an overflow of a counting means, and resets based on the overflow. A reset mode in which the target is a functional module that does not include a central processing unit, and a reset mode in which the target is a predetermined functional module that does not include a central processing unit, and a watchdog timer that allows the reset mode to be selected programmably. A data processing device characterized by: 3. In a reset mode in which a predetermined functional module that does not include a central processing unit is a module to be reset, the functional module to be reset is programmably selectable. 2. The data processing device according to item 2. 4. In a reset mode in which a predetermined functional module that does not include a central processing unit is set as a reset target module, the interrupt controller is excluded from programmably selectable reset target modules, and in a reset operation of a functional module that can be selectively reset. 4. The data processing device according to claim 3, wherein the watchdog timer is configured to instruct the central processing unit to perform predetermined exception processing via an interrupt controller. 5. In a reset mode where a predetermined functional module that does not include a central processing unit is the module to be reset, ports capable of outputting an address that changes to a high output impedance state by being reset are excluded from the modules to be reset that can be selected. 3. A data processing device according to claim 2, characterized in that the data processing device comprises: 6. The data set forth in claim 2, wherein the reset signal is also output to the outside in a reset mode in which a predetermined functional module including a central processing unit is a module to be reset. Processing equipment.