JPS60111509A - operational amplifier - Google Patents

Abstract

PURPOSE:To improve the through-rate by feeding back a node voltage at a differential stage to a bias voltage generating circuit in a differential operational amplifier. CONSTITUTION:A bias control circuit 1 consisting of the parallel connection with a P-channel MOS transistor (TR) M10 and an N-channel MOSTRM11 is inserted to the titled amplifier. The TRM10 goes to a low resistance when a node voltage V3 is lowred. On the other hand, the TRM11 becomes a low resistance when the voltage V3 is increased. Thus, the circuit 1 acts like a variable resistor becoming a low resistance when the voltage V3 is higher or lower than the operating point. As a result, the bias voltage V6 is low with V1 V2 and high when the difference between the potentials V1 and V2 is large, the current to the TRM5 is increased so as to increase the through-rate. Even if a large load is given to an output V0, since only the load with the own capacitor is given to an output V3, the response of the bias voltage is fast.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a differential input operational amplifier configured with CMOS devices, and particularly relates to an operational amplifier suitable for obtaining high gain and high speed operating characteristics. .

[Background of the invention]

The most basic configuration of a CMOS operational amplifier is, for example, I
EEEJournHl of 5olid -3tat
eCircuits Vol, 8C-17, A6. D
ember 1982 (referred to as document ■) P, 971
This is shown in Fig. 4. Figure 1 shows the Fi of the above-mentioned document.
g, 4 is shown with PMO8 and NMOS replaced. In 0MO8, the electrical characteristics of PMO8 and NMOS are almost symmetrical, so even if this is done, they are functionally equivalent. The differential stage of the operational amplifier is composed of M1 to M5. The AC characteristics of the differential stage can be analyzed using a circuit such as the one shown in FIG. In the figure, the symbol gM is the drain current amplification factor due to the gate-source voltage, and r is the differential resistance at saturation. In FIG. 1, Ml and M2. M3 and M4 are transistors of the same size υ, and the potential V in the linear operating region
Since t and V2 and the potentials (3) and (4) can be considered to be approximately equal, in FIG. Under these conditions, the solution (and the gain G are as follows).

N.

■1 V2=gM"(rz//'4) (1) Also, 4 g y = (2(,T)βI)2 r=(λ■)". Here, (W/L) is the size of the MOS transistor, β is the channel conductance, λ is the channel length variation effect coefficient, and ■ is the drain current.

Substituting these values yields the following equation.

Here, β=βN in I-ko/2+gM2.

W/L = (W/L'), λ-λN1 at r2
It is assumed that λ=λP at r4.

On the other hand, the slew rate S is defined as a voltage value that changes per unit time, and is expressed by the following equation.

■ S = -(3) CL Here, CL is the load capacity, and Δ is the current related to charging and discharging the load. When considering the slew rate for voltage (4) in FIG. 1, it is sufficient to set I=Io/2. Also, load capacity CL
As M2. If we consider only the self-capacitance of M4 and ignore the loads such as M6, OL will be as follows.

CL: CJLJ・(Wt+W4) (4) CJ is the diffusion layer capacitance per unit area, LJ is the width of the diffusion layer, w, , W,
are respectively M2. This is the channel width of M4. By substituting these, we get Generally, W2>W4, and equation (5) where W4=O gives the upper limit of the slew rate.

If the slew rate S at this time is written as Sm, then the work force is O. 8m=-)8'(6) 2 CJL, r Wz becomes.

In equation (2), (w/L)z = Wz/L
By solving for W2 and substituting it into equation (6), the relationship between slew rate and gain can be obtained.

In equation (7), length of the diffusion layer LJ1 capacitance per unit area of the diffusion layer CJ% channel length modulation effect coefficients λP and λ
The N1 channel conductance βN is a constant determined by the process. Further, the minimum dimension of the channel length is determined depending on the process. Therefore, the maximum value of the slew rate is 8 m''F(8), but if you try to obtain gain, the slew rate will drop significantly.

For this reason, for example, in an integrator having a reset circuit as shown in FIG. 3, the reset time is approximately proportional to the reciprocal of the slew rate, so the reset time must be long. Further, in the case of a voltage of 7 lower as shown in FIG. 4, the output cannot move faster than the slew rate, resulting in the disadvantage that it cannot follow changes in the input.

A similar problem is found in P978 of the above-mentioned document (■).

18 or l5SCC83'l
This phenomenon also occurs in a folded cascode amplifier as shown in pkgure 2 of 'ochical Paper FAM17.5 (referred to as Document ■) P 314. The cascode amplifier 7'' is characterized in that it can obtain a high gain without lowering the slew rate compared to the basic amplifier shown in FIG. However, in this case as well, the result is that the slew rate is approximately proportional to the reciprocal of the gain.

Electronics Letlers 3rdF is a countermeasure to improve the slew rate for such problems.
el)ruary 1983. Vo 1.19, No
, 3 (referred to as reference document) PO2. This circuit is applied to a balanced differential stage, and monitors the two outputs of the differential stage, and when a difference occurs in the input voltage and one of the two outputs decreases, it increases the bias voltage and increases the current. work. As a result, the gain decreases, but the slew rate can be improved.

However, this circuit cannot be applied to a differential stage with unbalanced output. Further, there were drawbacks such as a large circuit scale and a slow response if the output load of the differential stage was large.

[Purpose of the invention]

An object of the present invention is to provide an operational amplifier with an improved slew rate. By inserting transistors connected in parallel and applying one of the differential stage outputs to each gate, especially the output that is not connected to the next stage, a difference is created in the input voltage and the output of the differential stage is The present invention provides an operational amplifier equipped with a circuit that operates to change a bias voltage in a direction that increases the current in a differential stage when the field deviates from the operating point, thereby improving the slew rate.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. Fifth
The figure shows an example in which the bias circuit according to the present invention is applied to the differential stage portion of the conventional circuit shown in FIG. Normally, a bias circuit has M8 and Mo connected directly, or each is stacked in multiple stages.

Here, bias control circuit 1 is constructed by parallel connection of PMO8) transistor MIO and NMO8) transistor Mll.
is inserted. PMO8) The resistor MIG becomes low in resistance when the voltage v3 becomes low. On the other hand, the voltage of NMO8) transistor MIX is ■.

The higher the value, the lower the resistance. Therefore, the bias control circuit 1 has a voltage v3 higher than the operating point voltage of 1. Alternatively, it works as a variable resistor that lowers the resistance as it becomes lower. As a result, the bias voltage V6 is low when V 1 and y2, and v
The larger the difference between l and V2, the higher it becomes, increasing the current in M5 and improving the slew rate. Furthermore, even if a large load is applied to the output Vo, the output (3) is only loaded by its own capacitance, so the response of the bias voltage is quick.

Figure 6 shows the bias voltage Va for the differential stage output voltage ■3.
, Vy and the current I flowing through the MoS transistor M5
This figure shows the changes in .

In this example, the operating point voltage of the differential stage output (3) is around -0.5V, and as it deviates from this, the bias voltage V6 increases, and it can be seen that the current I flowing through M5 increases. The gate voltage (Vp) that minimizes the bias voltage
) and the ratio of the minimum value (Ip) and maximum value (IM) of the current can be changed depending on the circuit configuration and size design of each transistor. In the example shown in this figure, IM/IP=3.4
It can be seen that the slew rate can be improved by 3.4 times. Figure 7 shows a second embodiment in which the bias circuit of the present invention is applied to the differential stage of a folded cascode amplifier. A circuit example of the differential stage of a folded cascode amplifier is given in the document ■P, 978 F.
ig, 18.

FIG. 7 uses a differential stage similar to the one in which the relationship between PMO8 and NMO8 in the literature figure is reversed.

That is, the difference is that in Document (2), the gate and drain of M5 are connected, whereas in FIG. 7, the gate and drain of MIO on the opposite side, rather than the corresponding transistor Mll, are connected. Even in this case, the operating point voltage and gain remain the same. However, when trying to apply feedback to the bias control circuit with the voltage V6 corresponding to the output Vo in order to improve the slew rate, in the circuit of Document (2), the influence of the load on the output V6 is M5. It comes around through M6. For this reason, there is a drawback that the response until the bias is changed is slow. On the other hand, if the arrangement is as shown in FIG. 7, the effect of the load on the output Vo will not affect the output (6), so the above problem will not occur.

The bias circuit (MBI to MB5) in Figure 7 is PMO8)
Ransistor M3. Bias voltage V that determines the current of M4
A bias voltage VB3 that determines the current of the transistor M5 (Bl, NMOS) and a bias voltage VB2 that determines the operating point voltage of the voltages Vs and V4 are generated. In order to increase the slew rate, it is necessary to use only the current of M5 (M
3. The current in M4 also needs to be increased. Therefore, at this time, the bias voltage VBI must be high and VBI must be low. This is automatically achieved by inserting the bias control circuit 1 between MB2 and MB5 as shown.

FIG. 8 shows an example of the characteristics of the bias circuit in FIG. 7. The input voltage v6 to the bias circuit is plotted on the horizontal axis, and the output bias voltage Vnr + VB21 VBS is plotted on the vertical axis. Also, the current flowing through M5 at this time is shown at the same time. In this example, the operating point voltage Vp is around -1.5V,
The ratio IM/IP of the minimum current value IP and maximum current value IM is 3.8
It is. That is, compared to normal operation, when the operating point is off, the slew rate can operate at a maximum of 3.8 times.

Figure 9 shows M2O, M21 and M22 in the differential stage of Figure 7.
~ Source follower composed of M24, M2S, M26
This is a circuit example of an operational amplifier configured by combining an output stage composed of MB6 to MB9 and a second bias circuit composed of MB6 to MB9. The output V7 of the differential stage is the output of the next stage M2O, M
24 and the output V of the amplifier output stage.
Feedback is applied from o through resistor R1 and capacitor C. Due to the presence of this return path, the load on yy becomes considerably large.

Therefore, it is important to separate the signal V6 to the bias control circuit 1 from the influence of v7, and instead of coupling between the gate and source of Mll, it must be coupled on the MIO side as shown in the figure. . Note that C and R are added for phase compensation.

〔Effect of the invention〕

As described above, according to the present invention, when the difference between two input voltages is large, the current in the differential stage can be increased by changing the bias voltage, so that the slew rate can be significantly improved. For this reason, in conventional operational amplifiers, the gain and slew rate have a contradictory relationship, and the gain must be kept low to ensure a certain slew rate.However, by applying the present invention, it is possible to achieve a high gain. This makes it possible to obtain a high-performance operational amplifier by simultaneously obtaining a high slew rate and a high slew rate.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional CMO8 operational amplifier, and Figure 1 is its small signal equivalent circuit. "Connection diagram and output waveform" is a circuit diagram in which the bias control circuit of the present invention is applied to the differential stage of a conventional amplifier, No. 6.
The times are the output characteristics of the bias circuit of FakekeM, the name q is the circuit diagram applied to the cascode amplifier, the υ mouth is the output characteristics of the bias circuit of Taku7cho, and the control (2) is the output characteristics of the high performance operational amplifier of the present invention. It is a circuit diagram. 1...Bias voltage control circuit. 1st day 3rd day
,! 5th item 711 Vth b mouth V3CV) 7th close + \l 8th day VbCV) 9th page 1st page continuation [Phase] Inventor Ogawa - Ka @ Inventor Hagiwara. Hitachi Microcomputer Engineering Co., Ltd. 1-28 Higashikoigakubo, Kokubunji City Hitachi, Ltd. Central Research Laboratory

Claims (1)

[Claims] 1. A differential operational amplifier configured with CMOS devices, characterized in that the voltage at one node of the differential stage is fed back to the bias voltage generation circuit to control the bias voltage. operational amplifier. 2. The bias voltage generation circuit includes a circuit configured to connect a PMO 8 and an NMO 8 in parallel, and apply one node voltage of the differential stage to each gate in common. The operational amplifier according to item 1. 3. The differential stage is a folded cascode amplifier, and is a node that obtains an output signal from the first output node of the cascode circuit to the next stage, and feeds back to the bias voltage generation circuit from the second output node. 1. The ρ operational amplifier according to item 1 above, wherein the ρ operational amplifier obtains a voltage. 4. The cascode circuit includes two MOS transistors whose gate and drain are coupled on the second output node side.
The MOS transistor is stacked in two stages, and the gate on the first output node side is coupled to the corresponding gate of the MOS transistor on the first output node side. 4. The operational amplifier according to item 3 above.