JPS60110142A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60110142A JPS60110142A JP21826983A JP21826983A JPS60110142A JP S60110142 A JPS60110142 A JP S60110142A JP 21826983 A JP21826983 A JP 21826983A JP 21826983 A JP21826983 A JP 21826983A JP S60110142 A JPS60110142 A JP S60110142A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- insulating film
- forming
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 19
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 5
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims 2
- 230000008018 melting Effects 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 14
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 7
- 239000000377 silicon dioxide Substances 0.000 abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- 239000011229 interlayer Substances 0.000 abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の製造方法、特にMO8型集積回
路の多層配線技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular to a multilayer wiring technology for MO8 type integrated circuits.
従来例のj114成とその問題点
第1図は、アルミニウム二層配線構造を有する半導体装
置の上層アルミニウム電極層蒸着直前まで完了した工程
における従来例を示す要部の拡大断面図である。簡略化
するため第1層アルミニウム電極層形成工程から示して
いる。図中1は半導体基板、2は表面絶縁膜、3はアル
ミニウムまだはアルミニウム合金などからなる第1層金
属膜、そして4ば絶縁膜で、第2層目の金属配線(図示
せず)との層間絶縁膜となるものである。従来、第1層
金属膜3を形成した後、常圧あるいは減圧CVD法によ
るリン添加S i O2膜、もしくはプラズマCVD法
による窒化硅素膜を第2層金属膜との層間絶縁膜4とし
て形成する方法により形成されていた。この方法では、
第1層金属膜3の段差部における絶縁WX4の現状は、
第1図のaに示すように、オーバーハングのきつい形状
となる。このような断面形状の絶縁膜4では、図中すに
おいて、膜質が低下し応力変化によって容易にクラック
が発生し、絶縁耐圧が確保できない問題があった。また
、図中aおよびbにおいて相互配線に用いるアルミニウ
ムが段切れを起こし易すという問題があった。J114 formation of the conventional example and its problems FIG. 1 is an enlarged sectional view of the main part of the conventional example showing the process completed immediately before the deposition of the upper aluminum electrode layer of a semiconductor device having a two-layer aluminum wiring structure. For the sake of simplicity, the process of forming the first aluminum electrode layer is shown first. In the figure, 1 is a semiconductor substrate, 2 is a surface insulating film, 3 is a first layer metal film made of aluminum or aluminum alloy, and 4 is an insulating film, which is connected to a second layer metal wiring (not shown). This serves as an interlayer insulating film. Conventionally, after forming the first layer metal film 3, a phosphorus-doped SiO2 film by normal pressure or low pressure CVD method or a silicon nitride film by plasma CVD method is formed as the interlayer insulating film 4 with the second layer metal film. It was formed by a method. in this way,
The current status of the insulation WX4 at the stepped portion of the first layer metal film 3 is as follows:
As shown in a of FIG. 1, the shape has a severe overhang. In the insulating film 4 having such a cross-sectional shape, as shown in the figure, there is a problem in that the film quality deteriorates and cracks easily occur due to changes in stress, making it impossible to ensure dielectric strength. In addition, there is a problem in that the aluminum used for mutual wiring in a and b in the figure tends to cause breakage.
発明の目的
本発明は、上記の問題点を解決するためになさルたもの
で、層間絶縁膜にオーパーツ・ング部が形成されること
を防ぎ、このオーパーツ・ング部が存在した時に生じる
応力不均衡に基くアルミニウム等の金属膜配線の局部的
な応力腐食を排除して、金属配、腺の段切れを防止し信
頼性を高めることのできる半導体装置の製造方法を提供
するものである。Purpose of the Invention The present invention has been made to solve the above-mentioned problems, and is intended to prevent the formation of an overparts ring in an interlayer insulating film, and to prevent the formation of an overparts ring in the interlayer insulating film, and to prevent the formation of an overparts ring in the interlayer insulating film. The present invention provides a method for manufacturing a semiconductor device that can eliminate localized stress corrosion of metal film wiring such as aluminum due to stress imbalance, prevent breakage of metal wiring and glands, and improve reliability. .
発明の構成
本発明は、要約するに、半導体基板上に直接もしくは絶
縁膜を介して電極層を形成したのち、前記電極層より横
方向の工・ンラング速度が小さし第2層を形成し、つい
で所定のレジスしくターンをマスクに、前記電極層およ
び第2層にエツチング処理を櫂こし、エツチング断面形
状を丁字形になし、しかる後に低温形成可能な絶縁膜を
形成した後、前記絶縁膜全面に等方性エツチング処理を
施こす工程をそなえた半導体装置の製造方法であり、こ
れによればその後形成される蒸着絶縁膜にできる段差部
をなめらかな膜表面となし、多層配線構造が好都合に実
現される。Structure of the Invention The present invention can be summarized by forming an electrode layer directly or via an insulating film on a semiconductor substrate, and then forming a second layer having a lower lateral processing speed than the electrode layer, Next, using a predetermined resist pattern as a mask, etching is performed on the electrode layer and the second layer so that the cross-sectional shape of the etching becomes a T-shape. After that, an insulating film that can be formed at a low temperature is formed, and then the entire surface of the insulating film is etched. This is a method for manufacturing semiconductor devices that includes a process of isotropic etching. According to this method, the stepped portions of the subsequently formed vapor-deposited insulating film are made into smooth film surfaces, making it convenient for multilayer wiring structures. Realized.
実、怖−1の説明
本発明の詳細を実施例をもって説明する。第2図は、本
発明の一実施例にかかる方法により製造された半導体装
置の要部を示す断面図で、第1図と同一番号は同一部分
を示すが、二酸化硅素膜6および絶縁膜6を有するとこ
ろが第1図構造と異なる。Actually, Explanation of Fear-1 The details of the present invention will be explained with reference to examples. FIG. 2 is a cross-sectional view showing essential parts of a semiconductor device manufactured by a method according to an embodiment of the present invention, in which the same numbers as in FIG. 1 indicate the same parts. It differs from the structure in Figure 1 in that it has the following.
以下、本発明の実施例を順を追って説明する。Hereinafter, embodiments of the present invention will be described in order.
第3図は電極配線層として、アルミニウム膜3を約1μ
m形成した後、CVD法により、第21−として、二酸
化硅素膜5を3000人の厚みに形成し、所定のレジス
トパターン7を形成した段階の1新面図である。その後
、レジスト7をマスクI、lこフレオン系ガスを用いた
反応性イオンエツチングにより、二酸化硅素膜5を異方
性エツチングした後、アルミニ1クム膜3に塩素系ガス
プラズマを用い、エツチング処理する。この時アルミニ
ウム膜3は、二酸化硅素膜5の下部へ0.3μm程度の
アンダーカットを生じさせる。このように形成された丁
字形の断面形状を有するパターン上部、プラズマCVD
法により窒化硅素膜6を形成した段階の断面図を第4図
に示す。この後、前記半導体基板全面に、フレオン系ガ
スを用いプラズマエツチング処理を施こし、電極層3の
側壁部分にのみ窒化硅素膜6を残し、段差部分の平坦化
を行った段階の断面図を、第5図に示す。この結果、こ
の後形成される絶縁膜の全表面はならだかになり、オー
バーハングのない良好な絶縁膜が得られる。その後の上
部北極配線に用いるアルミニウム膜3は段切れもなく非
常に信頼性の高い形成かり能であり7、半導体装置の信
頼性が飛躍的に向上する。なお、第2層として、本実施
例では二酸化硅素膜6を用いたが、これは、電極層3よ
り横方向工、ノラング速度の低い材料であれば、他の材
料でもよく、また導電性材料であってもかまわない。Figure 3 shows an aluminum film 3 of approximately 1 μm as an electrode wiring layer.
This is a new view of a stage in which a silicon dioxide film 5 is formed to a thickness of 3000 mm as a 21-th film by the CVD method, and a predetermined resist pattern 7 is formed. Thereafter, the silicon dioxide film 5 is anisotropically etched by reactive ion etching using Freon-based gas using mask I for the resist 7, and then the aluminum 1-layer film 3 is etched using chlorine-based gas plasma. . At this time, the aluminum film 3 causes an undercut of about 0.3 μm below the silicon dioxide film 5. The upper part of the pattern having a T-shaped cross section formed in this way, plasma CVD
FIG. 4 shows a cross-sectional view of the silicon nitride film 6 formed by the method. After that, the entire surface of the semiconductor substrate is subjected to plasma etching using Freon gas, leaving the silicon nitride film 6 only on the side wall portions of the electrode layer 3, and the cross-sectional view at the stage where the stepped portions are flattened is shown below. It is shown in FIG. As a result, the entire surface of the insulating film to be formed thereafter becomes sloped, and a good insulating film without overhang can be obtained. The aluminum film 3 subsequently used for the upper north pole wiring can be formed very reliably without any gaps 7, and the reliability of the semiconductor device is dramatically improved. Although the silicon dioxide film 6 was used as the second layer in this embodiment, it may be made of any other material as long as it has a lower lateral processing speed than the electrode layer 3, or it may be made of a conductive material. It doesn't matter.
発明の効果
以上、本発明によれば、多層金属配線構造を持つLSI
あるいは超LSIの素子構造の製造方法として特に好適
であり、工業的価値が高い。As described above, according to the present invention, an LSI having a multilayer metal wiring structure
Alternatively, it is particularly suitable as a method for manufacturing a VLSI element structure, and has high industrial value.
第1図は、従来の半導体装置の要部断面構造図、第2図
は、本発明にかかる半導体装置の要部断面構造図、第3
図〜第5図は、本発明の工程断面図である。
1・・・・・・半導体基板、2・・・・・・表面絶縁膜
、3・・・・・金属膜、4・・・・・・絶縁膜、5・・
・・・二酸化硅素膜、6・・・・・プラズマ窒化硅素膜
、7・・・・・・ホトレジスト。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図
第 2 図
fJa図
第4図FIG. 1 is a cross-sectional structural diagram of main parts of a conventional semiconductor device, FIG. 2 is a cross-sectional structural diagram of main parts of a semiconductor device according to the present invention, and FIG.
Figures 5 to 5 are cross-sectional views of the process of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Surface insulating film, 3... Metal film, 4... Insulating film, 5...
... silicon dioxide film, 6 ... plasma silicon nitride film, 7 ... photoresist. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure fJa Figure 4
Claims (3)
横方向のエツチング速度が、前記電極層より小さい第2
層を形成し、ついで所定のレジストパターンをマスクに
、前記′電極層および第2層に順次、エツチング処理を
施こしてパターン形成シ、ついで、両層パターン上をお
おって、低温形成可能な絶縁膜を形成した後前記絶縁膜
に等方的エツチング処理を施こす工程をそなえた半導体
装置の製造方l去。(1) After forming a predetermined electrode layer on the semiconductor substrate,
a second layer whose etching rate in the lateral direction is lower than that of the electrode layer;
Then, using a predetermined resist pattern as a mask, the 'electrode layer and the second layer are sequentially etched to form a pattern, and then both layer patterns are covered with an insulating layer that can be formed at a low temperature. A method for manufacturing a semiconductor device comprising the step of subjecting the insulating film to an isotropic etching process after forming the film.
金属、高融点金属シリサイドもしくはアルミニウム、ア
ルミニウム合金からなる特許請求の範囲第1項に記載の
半導体装置の製造方法。(2) '1'jl: The method of manufacturing a semiconductor device according to claim 1, wherein the pole layer is made of polycrystalline silicon, a high melting point metal, a high melting point metal silicide, aluminum, or an aluminum alloy.
プラズマCVD法で形成される特許請求の範囲第1項に
記載の半導体装−の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film that can be formed at low temperature is formed by a low pressure CVD method or a plasma CVD method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21826983A JPS60110142A (en) | 1983-11-18 | 1983-11-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21826983A JPS60110142A (en) | 1983-11-18 | 1983-11-18 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60110142A true JPS60110142A (en) | 1985-06-15 |
Family
ID=16717219
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21826983A Pending JPS60110142A (en) | 1983-11-18 | 1983-11-18 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60110142A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0251232A (en) * | 1988-06-29 | 1990-02-21 | Philips Gloeilampenfab:Nv | Manufacture of semiconductor device |
JPH0520649U (en) * | 1991-08-30 | 1993-03-19 | アラコ株式会社 | Variable shape sheet |
-
1983
- 1983-11-18 JP JP21826983A patent/JPS60110142A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0251232A (en) * | 1988-06-29 | 1990-02-21 | Philips Gloeilampenfab:Nv | Manufacture of semiconductor device |
JPH0520649U (en) * | 1991-08-30 | 1993-03-19 | アラコ株式会社 | Variable shape sheet |
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