JPH04340749A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of an insufficient withstand voltage of a shirt-circuiting trouble caused by residual dross left in a cave after patterning upper wiring by preventing the formation of the cave in an interlayer insulating film between wiring. CONSTITUTION:An interlayer insulating film composed of silicon oxide films 4 and 5 is formed by depositing the film 5 after depositing the film 4 on the surface of a silicon oxide film 2 on which wiring 3 and 3a are formed and etching back the film 4.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having multilayer wiring.

0002

2. Description of the Related Art With the recent increase in the degree of integration of semiconductor devices, semiconductor devices in which interconnections formed on a semiconductor substrate are structured in multiple layers of two or more have been put into practical use. The interlayer insulating film used in this multilayer wiring is generally formed by the CVD method.

FIGS. 2A to 2D are cross-sectional views of a semiconductor chip shown in order of steps to explain a conventional method of manufacturing a semiconductor device.

First, as shown in FIG. 2(a), a lower layer wiring 3 is formed on a silicon oxide film 2 provided on a silicon substrate 1.
, 3a.

Next, as shown in FIG. 2(b), a silicon oxide film 6 is deposited by the CVD method to form an interlayer insulating film. Here, if the distance between the wirings 3 and 3a is narrow, a cavity 7 is created between the silicon oxide film 6.

Next, as shown in FIG. 2C, a portion of the upper surface of the silicon oxide film 6 is etched back to smooth the upper surface using a reactive ion etching method.

Next, as shown in FIG. 2D, a metal layer is deposited on the silicon oxide film 6 and selectively etched to form upper layer interconnections 8 and 8a.

[0008] Here, a residue 9 of the metal layer may be generated within the cavity 7.

[0009]

[Problems to be Solved by the Invention] In the above-mentioned conventional semiconductor device manufacturing method, as the spacing between lower layer interconnects becomes narrower, cavities are formed in the interlayer insulating film between adjacent interconnects, which reduces the electrical withstand voltage between the interconnects. In addition, during the etching process when forming the upper layer wiring, metal layer residue is generated in the cavity, causing a short circuit between the upper layer wiring and reducing the reliability of the semiconductor device. .

0010

[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes the steps of providing a plurality of adjacent wirings on an insulating film provided on a semiconductor substrate, and forming a surface including the wirings with a distance between the wirings. forming a first interlayer insulating film having a thickness of less than 1/2; etching back the first interlayer insulating film to leave the first interlayer insulating film only on the sidewalls of the wiring; The method includes the step of forming a thick second interlayer insulating film on the surface including the wirings to fill the gaps between the wirings.

[0011]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

First, as shown in FIG. 1(a), an aluminum layer is deposited and patterned on a silicon oxide film 2 provided on a silicon substrate 1, and the lower layer wiring is formed with a film thickness of 1 μm and a wiring interval of 1 μm. Form 3, 3a.

Next, as shown in FIG. 1(b), a silicon oxide film 4 is deposited to a thickness of 0.4 μm by plasma CVD.

Next, as shown in FIG. 1(c), CF4
The silicon oxide film 4 is etched back by reactive ion etching using gas, leaving the silicon oxide film 4 only on the side walls of the wirings 3 and 3a.

Next, as shown in FIG. 1(d), a silicon oxide film 5 is deposited to a thickness of 0.5 μm by the CVD method to form an interlayer insulating film composed of the silicon oxide films 4 and 5.

Here, since the taper is formed at the shoulder by etching back the silicon oxide film 4, the interlayer insulating film can be formed without creating a cavity between the wirings 3 and 3a when depositing the silicon oxide film 5. can be formed.

Note that the thickness of the silicon oxide film 4 must be kept to less than 1/2 of the wiring spacing so as not to create cavities.

Furthermore, tungsten may be used instead of aluminum as the lower layer wiring material, and CHF3 gas is used as the etching gas for reactive ion etching used for etch back in this case. Further, materials such as molybdenum, polysilicon, polycide, etc. may be used for the lower layer wiring.

[0020]

Effects of the Invention As explained above, the present invention forms a first interlayer insulating film on adjacent interconnects, and then etch-backs the first interlayer insulating film, leaving the first interlayer insulating film only on the side walls of the interconnects. A taper is provided at the upper end of the interlayer insulating film. Next, by providing a thick second interlayer insulating film, it is possible to prevent cavities from forming in the interlayer insulating film between wirings, thereby preventing short circuits in the breakdown voltage or upper layer wiring, and improving the reliability of the semiconductor device. has.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

1 Silicon substrate 2, 4, 5, 6 Silicon oxide film 3, 3a, 8,
8a Wiring 7 Cavity 9 Residue

Claims (1)

[Claims] 1. A step of providing a plurality of adjacent wirings on an insulating film provided on a semiconductor substrate, and a first interlayer insulating film having a thickness of less than 1/2 of the wiring spacing on a surface including the wirings. a step of etching back the first interlayer insulating film to leave the first interlayer insulating film only on the sidewalls of the wiring, and forming a thick second interlayer insulating film on the surface including the wiring. 1. A method of manufacturing a semiconductor device, comprising the step of forming and filling gaps between interconnections.