JPS60105056A - digital control device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a digital control device including a processor and a backup memory.

[Prior art]

FIG. 1 is a block diagram showing a conventional example, in which a processor 1 is located at the center, a main memory 2, an input/output circuit 3, and a backup memory 4 are arranged around the periphery, and these are connected by a bus bar 5. The processor 1 executes instructions stored in the main memory 2, performs control operations while accessing predetermined data in the main memory 2, and exchanges data with the outside via the input/output circuit 3. .

In addition, as a countermeasure in the event that an abnormality occurs due to a runaway of the processor 1, the contents of the main memory 2 become irregular, and the 1 basic database is destroyed, the database in the main memory 2 is periodically transferred to the memory 4. Shioshi, Processor 1
When an abnormality is detected by self-diagnosis or a separate monitoring circuit, and the initial state is set before restarting the operation, the contents of the memory 4 are stored in the main memory 2, and the operation is resumed based on this. It becomes.

However, in the past, if a failure such as a disconnection or short circuit occurs in the circuit between the bus 5 and the memory 4, it becomes impossible to restart the operation, and the contents of the memory 4 become irregular and the database This has the disadvantage that it requires a lot of effort and time to recover from a failure.

[Summary of the invention]

The present invention has an object of fundamentally solving the conventional drawbacks, and in the above-mentioned digital control device, a bidirectional buffer circuit is inserted between the processor and the backup memory, and the processor or the buffer Backup memory is removable from the main body including the circuit,
Moreover, even if a main unit side KJ4 error occurs, the backup memory retains the stored contents, thereby providing an extremely effective digital control device.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to FIG. 2 and subsequent figures showing embodiments.

FIG. 2 is a block diagram of the entire configuration. A bidirectional buffer circuit 21 is connected to one end of the bus 5, forming a main body 22 that is integrated with the processor 1 to the buffer circuit 21. The connected backup unit 23 is detachable from the main body 22 through a connector 24.

In addition, the backup unit 23 houses a backup memory, and the backup memory is stored in the backup unit 23 and
The database is transferred in the same manner as described above.

FIG. 3 is a diagram showing the parts where a failure occurs in the bus bar 5 to the backup unit 23, and shows the case where a failure occurs in each of the following parts.

■=buffer circuit 21 side of bus 5, ■: bus 5 side of buffer circuit 21, ■=main circuit of buffer circuit 21, ■: connector 24 side of buffer circuit 21, [F]: buffer circuit 21 and connector 24 [F]: Circuit between the connector 24 and the memory for bank-up, @: Inside the memory for backup, If the phenomena and countermeasures corresponding to each failure part are shown in this, the following is shown. As shown in the table.

Therefore, even if an abnormality occurs on the main body 22 side, as long as the backup memory maintains the stored contents normally, in the case of 0 to [F], the control operation will be resumed as soon as the main body 22 is replaced. While it is subsequently restarted, [F]
In the case of ■, there is no problem with the operation of the main body 22, so
Replacing the backup unit 23 immediately restores the normal state υ, and in either case, troubleshooting becomes simple and easy.

FIG. 4 is a block diagram of the bank up unit 23, which includes a bank up memory 3.1 having a plurality of data areas DEA and DEB, and a selection circuit 32. A selection signal for repeatedly and sequentially selecting the data areas DEA and DEB is applied to the data areas DEA and DEB individually and sequentially through a part 5a of the bus 5. On the other hand, it sends out an enable signal to set the data access state.

Therefore, in the data area DEA1DEH, the databases given via the part 5b of the bus 5 are repeatedly stored individually and sequentially, but for a predetermined prohibited time after one of them becomes accessed. The configuration of the selection circuit 32 is determined such that the other is in an access prohibited state.

5 is a block diagram of the selection circuit 32, and FIG. 6 is a block diagram of the selection circuit 32.
It is a timing chart showing the waveforms of each part in the figure, and the code showing the selection signal from the bus 5a is the decoder 4.
1 and are generated individually and sequentially as selection signals (a) and (b), which are sent to the data area DEAXDEB as enable signals (c) and (d) via AND gates 42 and 43. Enable signal (1
(d) is also applied to pulse generators 44, 45 such as monostable multi-bibreaks, and each is driven by the trailing edge of enable signals (c) and (d), and the inhibition time T,
Inhibition pulses (e) and (f) having a pulse width of □ are generated.

The inhibit pulses (,), (f) are inverted via inverters 46, 47, and the enable signals (d),
(C), so during the inhibit time TINH, the AND gates 43 and 42 on the other side are in the off state, and either one of the enable signals is sent out. Prohibited time T I
During the HH time, the other enable signal cannot be sent.

Therefore, during the prohibition time TtNn after the data area DEA enters the access state, the data area DEB becomes the access prohibition state, and when the data area DEB enters the access state, the data area DEA becomes the access prohibition state. .

Note that the inhibition time TINII is a fixed time T that is set for the self-diagnosis cycle of the processor 1 and for monitoring the monitoring circuit.
WDT, and the time interval between selection signals (a) and (b) is T8.
If it is EL, TagL)TtNn)Twnt ・・・・・・・・・・・・
・・・・・・・・・・・・ As defined in the relationship in (1).

Then, as shown in FIG. 6(g), the occurrence of an abnormal state on the main body 22 side is indicated by a chain line, and the detection of this by a certain period of time TwnT is indicated by an X mark.
Even if the contents of either of B are destroyed due to the occurrence of an abnormal condition, the contents of the data area listed in (g) will not be saved as normal because access is prohibited at this time. Ru.

That is, in the abnormal states of ■ to ■, the data area DEA
is in the access state and the contents of the data area D8 are invalid, whereas the data area D8 is in the non-access state and the access prohibited state.
The contents of EH are maintained as normal, and in the abnormal state of ■,
Both data areas are in a non-accessed state, and both data areas DEA and DEri hold regular contents.

In addition, in the abnormal states of ■ to ■, the relationship is opposite to that described above, and even if the contents of data area DEH become irregular, the contents of data area DgA are maintained as regular, and ■
In the abnormal state of , the result is the same as that of ① above.

Therefore, even if an abnormality such as a runaway occurs in the processor 1 at any point and data with incorrect content is transferred to the backup unit 23, the data areas DEA and DE
At least one of B stores the regular database immediately before the abnormality occurs, and when restarting the control operation in response to the detection of the abnormal state, the data areas DEA and D
If the check pits, etc. in the EB are checked and the contents are determined to be legal, and the contents are used, there will be no problem in continuing the control operation.

Table 1 Each time T8ELXTINII, TWDT is (
1) It is desirable to make them as close to each other as possible while maintaining the relationship shown in equation 1).
, (d).

FIG. 7 is a flowchart showing the operating status of the processor 1.1 Backup memory addition? If the judgment in step 51 is No, the process immediately moves to control calculation 52, but if YES in step 51, the database is transferred from one backup memory to the main memory 53, and then the process moves to step 52. , 1 Self-diagnosis'' Next to 54, is the backup memory normal? 〃Judging from 55, this is N.

If so, send an alarm 56, and if YES, transfer the data to the backup memory 57, then return to step 52, and repeat the above steps.

Therefore, the main body 22 side or the backup unit 2
Even if a failure occurs on any of the three sides, recovery from the failure is easy and quick, and in particular, there is no need to reconfigure the database, which greatly reduces the effort required to recover from the failure.

However, as the buffer circuit 21, a simple buffer amplifier or gate circuit connected bidirectionally is used.
Depending on the conditions, a latch circuit or the like may be added, or a socket, a planted pin, etc. may be used in place of the connector 24, and the structure of the bank up unit 23 may be selected accordingly. .

Furthermore, if the number of data areas DEA and DEB is increased and the configuration shown in FIG. 5 is determined accordingly, data storage becomes more reliable, and in FIG. A counter or the like that counts pulses may be used, and the same effect can be obtained by replacing the AND gates 42 and 43 with NAND gates, inhibit gates, etc.
As long as it exhibits the same function, in addition to the configurations shown in FIGS. 4 and 5, the configuration can be arbitrarily selected and numerous modifications can be made.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, failure recovery is easy and quick9, and in particular, there is no need to reconfigure the database, which greatly reduces the effort involved in failure recovery.
Remarkable effects can be obtained as a digital control device for various uses.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional example, Fig. 2 and subsequent figures show embodiments of the present invention, Fig. 2 is a block diagram of the entire configuration, Fig. 3 is a block diagram of main parts showing the failure occurrence part, Fig. 4 5 is a block diagram of the backup unit, FIG. 5 is a block diagram of the selection circuit, FIG. 6 is a timing chart showing waveforms of each part in FIG. 5, and FIG. 7 is a flow chart showing the operating status of the processor. 1...Processor, 2...Main memory, 5...
-Bus bar, 21-- life buffer circuit, 22-- main body, 23-- back amplifier unit, 24-- connector, 31-- memory, 32-- selection circuit. Patent applicant: Yamani-Newel Co., Ltd. Agent: Masaki Yamakawa (and 1 other person) Figures 1 to 4 LL1 OO Figure 6 Figure 7

Claims (1)

[Claims] In a digital control device having a processor and a memory for bank-up, a bidirectional buffer circuit inserted between the processor and the memory for backup, and a main body including the processor or the buffer circuit detachably provided. A digital control device comprising: the bank-up memory that retains stored contents even if an abnormality occurs on the main body side.