JPS5839321A - Storage device - Google Patents

Abstract

PURPOSE:To prevent a runaway and malfunction of a computer by providing a voltage detecting circuit which detects an abnormal voltage of a battery, and sending a parity error signal to a computer side on detecting the abnormal voltage and then stopping the execution of the computer. CONSTITUTION:When an electronic computer system is not powered up by a power source VCC, a voltage required to retain data in a memory element 7 is applied from a battery 10 through a power source circuit 11. If the battery 10 has a fault such as a voltage drop, the computer system is powered up and reset a prescribed time later by a reset signal 14. At this time, a status signal 13 showing that the voltage level signal 15 of the battery 10 is lower than a voltage drop reference signal is held by a latch circuit 17, deciding on the state of a latch signal 16. On the basis of the signal 16, a parity error logical circuit 19 sends parity error data to a data bus 1 through a bus driver 5 in response to the reading of the computer. Consequently, the computer side stops execution.

Description

Detailed Description of the Invention (j) Description of the Technical Field The present invention relates to a storage device C2 having a battery backup memory used in a computer system, with particular consideration given to protection in the event of abnormal battery voltage and battery maintenance during operation. related to storage devices.

(b) Description of Prior Art As a collapsible storage device used in computer systems, data retention during power outage 6: Battery backup memory using a battery has recently been used.

Figure 1 is a block diagram showing the configuration of a conventional general battery backup memory. 01#'i data bus, 2i1 address bus, and control signal + 3 Fi
Thl+ control circuit type circuit 4 A control signal for operating the bus driver 5, 6 a control signal and an address signal for the memory element 7,
8 is the data signal of the memory element 7, 9 is the power supply of the memory element 7 for battery backup, IO#'i batch')
l 11 is the power supply circuit.

12 is a voltage detection circuit for detecting voltage abnormality of the battery 10; 13 is a detection signal thereof;

161 FIG. 5 = In the control circuit 4. The bus driver 5.degree. memory element 7 operates under the management of the address bus and control signals 2, similar to a general computer. The power supply circuit 11 also supplies power Vcc to the computer system.
It switches between the battery 10 and the battery 10, and is switched to the battery side in the event of a power outage.

In this conventional battery backup memory, if there is an abnormality in the battery 101 and the computer system operates in a state where the contents of the memory element 7 are lost, it is dangerous, so a voltage detection circuit 12 is provided to check the battery voltage. The computer system is prevented from operating in a ridge manner by reading the detection signal 13 as input data and checking the data using computer system software.0However, with this conventional method, existing core memory and wire memory etc., there is a drawback that an input point for reading the detection signal 13 described above and software for processing the read data must be added.

(c) Purpose of the invention The purpose of the present invention has been made in view of the above-mentioned drawbacks,
As a means of preventing v4wj operation due to battery voltage abnormality, we provide a battery backup memory storage device that does not require reading a voltage abnormality detection signal as input data and does not require special software for voltage detection. There is a particular thing.

(Structure of the Invention FIG. 2 shows an embodiment of the independent backup memory according to the present invention. Parts such as - are the same as in FIG. 1, and the explanation thereof will be omitted.

In the same figure (2, RI8'r'14 is the system reset signal output when the computer system is powered on,
LmvL15ti battery lO voltage level signal,
5Ts13e'' is a status signal obtained by converting the voltage level signal 15 determined by the voltage detection circuit 12 into a logic signal, L
On day 16, status signal 5T813 is reset signal R1
The latch signal held in the latch circuit 17 by 1i8'l'14, puts is the parity-error logic circuit 19
is the output control signal of

FIG. 3 is a timing chart illustrating the invention in detail in FIG. 2. In the same figure, rmf indicates the reference voltage of the voltage drop determined by the voltage detection circuit 12 〇 (θ) Effect of the invention 82 In Figure + 2, when the computer system is not operating, that is, when the computer system power supply V
When cc is not supplied, C2 is applied from the battery 10 through the power supply circuit ti to store the data in the memory element 7 (2).
When the power supply Vcc of the computer system is supplied, the power supply circuit 11 automatically switches the power supply to the power supply Vcc side of the computer system. This is the same as in the case shown in FIG. 1 C:.

If an abnormality such as voltage drop occurs in the battery 10,
At the time of power outage ζ2, the data content of the memory element 7 is no longer guaranteed. If such an abnormality exists, the power of the computer system is turned on at time tl, and when the system reset signal RE8T14 is released at time 1B, the voltage level signal LgvLis of the battery 10 will reach the voltage drop standard shown in FIG. The latch circuit 17 holds the status signal 5T813 indicating that the signal is below the signal rgj, and the latch signal 1
, 816 is determined. Next C2, latch No. 16 L8
16 outputs a parity error output control signal PI318 of the parity error logic circuit 19, and a data read request from the computer (in contrast, from the control circuit 4,
Only the data that causes a certain parity error is transferred to the data bus 1 of the computer and system through the bus driver 5.
0 As a result, the computer side detects a parity error and stops execution, resulting in a runaway situation.

There is no risk of malfunction.

Also, in the above state, at time χ8, batch January 0 is extracted and at time s4, oil is removed. Even if C1 and two normal batteries] O are inserted, the two-touch signal L816 does not deteriorate, so two people cannot operate C.

Therefore, the computer will not read the contents of the memory element 7 and start execution while the contents of the memory element 7 are uncertain.Also, even if the battery lO is normal, if the battery is replaced due to periodic maintenance. C2 operates on the reverse logic described above and allows battery 10 to be replaced while the computer system is running while preserving the contents of memory element 7.

(r) Detailed Description of the Invention C2 The battery backup memory according to the present invention l2 has a protection circuit against battery voltage abnormalities and does not require special software for voltage detection. It can be used in the same way as existing core memory, wire memory, etc.

In addition, since battery replacement can be easily performed while the data in the memory element is preserved, it is possible to provide a storage device that is easy to maintain.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional battery backup memory, FIG. 2 is a block diagram showing a battery backup memory according to an embodiment C of the present invention, and FIG. 3 is a block diagram showing a battery backup memory according to an embodiment of the present invention. This is a timing chart. 1... Data bus 2... Address bus and control signal 3... Control signal 4... Control circuit 5... Bus driver 6... Control signal and address signal 7...
Memory cable 8...Data signal 9...Power supply 10.
... Battery 11 ... Power supply circuit 12 ... Voltage detection circuit 13 ... Voltage detection status signal 14 ... Reset signal 15 ... Battery voltage level signal 16
... Latch signal 17 ... Latch circuit 18 ... Parity error control signal 19 ... Parity 2-logic circuit (7317) Agent Patent attorney Nori Chika
Yu (and 1 other person) Figure 2/7 3rd Fl! J

Claims (2)

[Claims] (1) In a storage device that uses a battery to retain data during a power outage, a voltage detection circuit is installed to detect voltage abnormalities in the battery, and the detection signal of the voltage detection circuit is replaced and retained at the timing when the power is turned on. A storage device equipped with a holding circuit. (2) In a storage device that uses a battery 42 to retain data during a power outage, a voltage detection circuit is provided to detect an abnormal voltage of the battery, and when the voltage detection circuit detects an abnormal voltage of the battery, A storage device equipped with a parity error logic circuit that generates a parity error for a system data read request.