JPS5994866A - Semiconductor device having schottky junction - Google Patents
Semiconductor device having schottky junctionInfo
- Publication number
- JPS5994866A JPS5994866A JP57205722A JP20572282A JPS5994866A JP S5994866 A JPS5994866 A JP S5994866A JP 57205722 A JP57205722 A JP 57205722A JP 20572282 A JP20572282 A JP 20572282A JP S5994866 A JPS5994866 A JP S5994866A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- aluminum
- gate electrode
- schottky junction
- migration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
- H10D30/6738—Schottky barrier electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/675—Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 本発明はショットキ接合を有する半導体装置に関する。[Detailed description of the invention] The present invention relates to a semiconductor device having a Schottky junction.
最近の通信システムの発展に伴って、これに使用される
半導体装置はより高い周波数で、より高速に動作するこ
とが要求されている。これらの要求に基すいて化合物半
導体装置が開発されてきた。With the recent development of communication systems, semiconductor devices used therein are required to operate at higher frequencies and at higher speeds. Compound semiconductor devices have been developed based on these requirements.
その代表的なものが砒化ガリウム(以下QaAsと記す
)を用いた電界効果トランジスタ(以下QaA8・FE
Tと記す)である。化合物半導体を用いた半導体装置、
特にQaAsを用いた半導体装置では主にショットキ接
合が用いられており、これらの装置において、良質なシ
ョットキ接合を得ることが最も重要なこととなっている
。A typical example is a field effect transistor (hereinafter referred to as QaA8・FE) using gallium arsenide (hereinafter referred to as QaAs).
(denoted as T). Semiconductor devices using compound semiconductors,
Particularly in semiconductor devices using QaAs, Schottky junctions are mainly used, and in these devices, it is most important to obtain a high quality Schottky junction.
従来、化合物半導体に対するショットキ接合形成用金属
としては、そのショットキ特性、耐熱性、加工性等に優
れていることからAtが多く用いられてきた。Conventionally, At has been widely used as a metal for forming Schottky junctions in compound semiconductors because of its excellent Schottky properties, heat resistance, workability, and the like.
第1図は従来のGaA3”FETの一例の断面図である
。FIG. 1 is a cross-sectional view of an example of a conventional GaA 3'' FET.
GaAS基板1の上にゲート電極2、ソース及びドレイ
ン電極3,4を形成する。ソース及びドレイン電極3,
4にはオーミック接合を作る金属としてAu−Ge合金
とNi とが用いられる。例えばAu−Ge合金を1
50OAの厚さに、 Niを50OAの厚さに形成し、
熱処理して合金化する。A gate electrode 2 and source and drain electrodes 3 and 4 are formed on a GaAS substrate 1. source and drain electrodes 3,
In No. 4, an Au-Ge alloy and Ni are used as metals to form an ohmic contact. For example, 1 Au-Ge alloy
Form Ni to a thickness of 50OA,
Alloyed by heat treatment.
ゲート電極2にはショットキ接合を形成する金属として
Atが用いられる。For the gate electrode 2, At is used as a metal forming a Schottky junction.
しかしながら、Atはマイグレーシロンといって通電中
にAtの結晶粒が移動する現象を起しゃすく、断線など
を起し、長期寿命の点で問題があった。このマイグレー
シロンの問題を解決する手段として、Atの上にTi
、 Ni等の異なる金属を乗せることが考え出された。However, At tends to cause a phenomenon called migration, in which At crystal grains move during energization, resulting in wire breakage and other problems in terms of long life. As a means to solve this migration problem, Ti is added on top of At.
It was devised to place different metals such as , Ni, etc.
第2図は従来のGaAs−FETのゲート電極部分の一
例の断面図である。FIG. 2 is a cross-sectional view of an example of a gate electrode portion of a conventional GaAs-FET.
GaAs基板1の上にAt層11 、 Ti または
Niの異種金属層12を形成し、ゲート電極をボンディ
ングバットへ引出すための配線としてTi/Pt/Au
層゛13を設けて接続させる。An At layer 11 and a dissimilar metal layer 12 of Ti or Ni are formed on the GaAs substrate 1, and Ti/Pt/Au is formed as a wiring for leading out the gate electrode to the bonding butt.
Layer 13 is provided and connected.
このようにTi またはNiの異種金属層12を設ける
仁とによphtのマイグレーシロンの問題は解消される
が素子製造工程中に、Atより反応性の強いT1または
Ni が酸化され、絶縁体層14を作り、層12と層1
3とが高抵抗層で接続されるという欠点を生じた。In this way, by providing the dissimilar metal layer 12 of Ti or Ni, the problem of pht migration is solved, but during the device manufacturing process, T1 or Ni, which is more reactive than At, is oxidized and the insulating layer 14, layer 12 and layer 1
3 is connected through a high resistance layer.
本発明は上記欠点を除去し、アルミニウムのマイグレー
シロンを抑制し、ゲート電極と配線との間の接続を低抵
抗で実現できるショットキ接合を有する半導体装置を提
供するものである。The present invention eliminates the above drawbacks, suppresses migration of aluminum, and provides a semiconductor device having a Schottky junction that can realize a connection between a gate electrode and a wiring with low resistance.
本発明のショットキ接合を有する半導体装置は、化合物
半導体層に接触してショットキ接合を形成するアルミニ
ウム層と、該アルミニウム層の上に設けられるアルミニ
ウム以外の金属の層を少くとも一層と、該アルミニウム
以外の金属層の上に設けられるアルミニウム層とを含ん
で構成される。A semiconductor device having a Schottky junction of the present invention includes an aluminum layer that contacts a compound semiconductor layer to form a Schottky junction, and at least one layer of a metal other than aluminum provided on the aluminum layer. and an aluminum layer provided on the metal layer.
次に、本発明の実施例について図面を用いて説明する。Next, embodiments of the present invention will be described using the drawings.
第3図は本発明の一実施例の断面図である。FIG. 3 is a sectional view of one embodiment of the present invention.
GaAs基板1の上rAt層21.Ti またはNiの
異種金属層22.At層23を順次積層してゲート電極
を形成する。At層21がGaAs基板1とショットキ
接合を作ることは言う、までもない。Upper rAt layer 21 of GaAs substrate 1. Dissimilar metal layer 22 of Ti or Ni. A gate electrode is formed by sequentially stacking At layers 23. It goes without saying that the At layer 21 forms a Schottky junction with the GaAs substrate 1.
次に、ゲート電極をポンディングパッドへ接続するため
の配線としてTi層24 、 Pt層25 、Au層2
6を順次積層する。この発明では、異種金属層220表
面をAt層23で覆っているから、第2図に示したよう
な絶縁体層は形成されなく、ht層23とTi層24と
は低抵抗で接合する。一方、At層21.23のマイグ
レーシヨンは異種金属層22及びTi層24を設けたか
ら抑制され、断線などの問題を生じない。Next, as wiring for connecting the gate electrode to the bonding pad, a Ti layer 24, a Pt layer 25, and an Au layer 2 are formed.
6 are stacked one after another. In this invention, since the surface of the dissimilar metal layer 220 is covered with the At layer 23, an insulator layer as shown in FIG. 2 is not formed, and the HT layer 23 and the Ti layer 24 are bonded with low resistance. On the other hand, migration of the At layers 21 and 23 is suppressed by providing the dissimilar metal layer 22 and the Ti layer 24, and problems such as disconnection do not occur.
上記実施例では基板1にQaAsを用いたが、他の化合
物半導体を用いても本発明は同様に適用できる。Although QaAs was used for the substrate 1 in the above embodiment, the present invention can be similarly applied to other compound semiconductors.
以上詳細に説明したように、本発明によれば、アルミニ
ウムのマイグレーシロンを抑制し、しかもゲート電極と
ボンディングバットとを低抵抗で接続できるショットキ
接合型のゲート電極を有する半導体装置が得られるので
その効果は大きい。As described in detail above, according to the present invention, it is possible to obtain a semiconductor device having a Schottky junction type gate electrode that suppresses aluminum migration and can connect the gate electrode and the bonding butt with low resistance. The effect is great.
第1図は従来のGaAs*FETの一例の断面図、第2
図は従来のGaAs*FETのゲー)!極部分の一例の
断面図、第3図は本発明の一実施例の断面図である。
1・・・・・・QaAs基板、2・・・・・・ゲート電
極、3,4・・・・・・ソース及びドレイン電極、11
・・・・・・At層、12・・・・・・異種金属層、1
3・・・・・・Ti/Pt/Au層、14・・・・・・
絶縁体層、21・・・・・・At層、22・・・・・・
異種金属層、23・・・・・・At層、24・・・・・
・Ti層、25・・・・・・pt層、26・・・・・・
Au層。Figure 1 is a sectional view of an example of a conventional GaAs*FET, Figure 2 is a cross-sectional view of an example of a conventional GaAs*FET.
The figure shows a conventional GaAs*FET game)! FIG. 3 is a cross-sectional view of an example of the pole portion, and FIG. 3 is a cross-sectional view of an embodiment of the present invention. 1...QaAs substrate, 2...gate electrode, 3, 4...source and drain electrode, 11
...At layer, 12...Different metal layer, 1
3...Ti/Pt/Au layer, 14...
Insulator layer, 21... At layer, 22...
Different metal layer, 23... At layer, 24...
・Ti layer, 25...PT layer, 26...
Au layer.
Claims (1)
ルミニウム層と、該アルミニウム層の上に設けられるア
ルミニウム以外の金属の層を少くとも一層と、該アルミ
ニウム以外の金部層の上に設けられるアルミニウム層と
を含むことを特徴とする7目ットキ接合を有する半導体
装置。an aluminum layer that contacts a compound semiconductor layer to form a Schottky junction; at least one layer of a metal other than aluminum provided on the aluminum layer; and an aluminum layer provided on the metal layer other than aluminum. What is claimed is: 1. A semiconductor device having a 7-metal junction, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57205722A JPS5994866A (en) | 1982-11-24 | 1982-11-24 | Semiconductor device having schottky junction |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57205722A JPS5994866A (en) | 1982-11-24 | 1982-11-24 | Semiconductor device having schottky junction |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5994866A true JPS5994866A (en) | 1984-05-31 |
Family
ID=16511596
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57205722A Pending JPS5994866A (en) | 1982-11-24 | 1982-11-24 | Semiconductor device having schottky junction |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5994866A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5086450A (en) * | 1989-08-23 | 1992-02-04 | Mitsubishi Denki Kabushiki Kaisha | Emergency intercommunication system for elevator |
-
1982
- 1982-11-24 JP JP57205722A patent/JPS5994866A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5086450A (en) * | 1989-08-23 | 1992-02-04 | Mitsubishi Denki Kabushiki Kaisha | Emergency intercommunication system for elevator |
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