JPS59134874A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device using a semiconductor substrate having a zincblende crystal structure such as GaAp.

However, G9A8 (gallium arsenide) Schottky barrier gate field effect transistor (GaAs
-8BGFET) is generally known.

G-aAs-8B G previously developed by the inventor of the present application
Ohmic contact electrodes serving as the source and drain are provided on the surface (principal surface) of the active region of the FET element's n-conductivity type, and one or two Schottky junction electrodes are provided in the middle to serve as the gate, resulting in a single gate structure. Alternatively, it has a denial gate structure made of gold.

Further, in manufacturing the source/drain electrodes,
AuG@, N on the n-type GaAe epitaxial layer
1+ Au t'' is sequentially laminated and then alloyed (
It is formed by performing ohmic contact with the G and Afi epitaxial layers by performing a treatment at around 400° C. for several minutes.

By the way, it is generally known that a eutectic is formed at about 356° C. when AuGe is 5s% Au and 12% Ge.

Perhaps for this reason, the composition ratio of conventional AuGe is 12% by weight of Ge at most.

However, as a result of measurement and inspection conducted by the present applicant, it has become clear that AuGe having such a composition ratio cannot provide an oscillatory bond of T.

Considering this point, when creating an ohmic on a GaA3 compound semiconductor substrate, an AuGe electrode (AuGe eutectic [rod constituent layer]) is often used; , Ga is G
aA Diffuses into Fl7 and becomes a donor to GaAEI
The general interpretation is that as a result of increasing the surface concentration, a tunneling phenomenon occurs between this highly concentrated l- and Au, resulting in ohmic contact. Therefore, it can be inferred that by increasing the amount of Ge, the GaAs surface has a higher carrier concentration and has a lower resistance.

On the other hand, as mentioned above, since AuGe becomes eutectic at a 1296Ga concentration, if the Ge degree is about 12% or under a 12% odor, Ge is absorbed by Au (-i.e., AuGe
It can be assumed that Ga reacts only to form a eutectic and does not diffuse sufficiently into GaAs.

Therefore, the present inventor developed the present invention based on the idea that if the total Ge concentration is increased to 12% by weight, excess Ge other than the U'' eutectic will be diffused into GaAs, resulting in low ohmic resistance. accomplished.

On the other hand, the above-mentioned type GaAEI epitaxial layer (n-type GaAEI epitaxial layer)
When AuGe, Ni, and Au (AB substrate) are treated with Ao4, the AuGe locally swells as shown in FIG. 1, and a so-called pole-up phenomenon often occurs, which worsens the miniaturization of gate electrodes and wire bondability. This is because AuGe itself has a large surface tension.
It is generally said that this is due to the fact that there is a tendency to harden into a round shape when it is produced. In the figure, 1 is a GaAθ substrate, 2 is an AuGe layer, 3 is an AuGe eutectic layer, 4 is an N1 layer, and 5 is an Au layer.

By the way, the AuGe layer 2. Ni layer4. The thickness of the Au layer 50 is conventionally 1200A and 300A.

1.30OA, and the thickness ratio of the AuGe layer 2 and the Au layer 5 is approximately 1:1.
Considering that the Au layer 5, which is as thin as 300A, may not be able to resist the pole assopsis of the AuGe eutectic layer, the thickness of the Au layer is gradually increased to prevent the pole up phenomenon above a certain thickness. discovered that it is possible to suppress
The present invention has been accomplished.

Therefore, an object of the present invention is to provide a semiconductor device with low ohmic resistance.

Another object of the present invention is to provide a semiconductor device without polling up.

9 below, the present invention will be explained by way of examples.

FIG. 2 shows a GaAe-8BGFE according to one implementation of the present invention.
A plan view showing the main parts of the T element, Figure 3 is Ill of Figure 2.
FIG. 4 is a cross-sectional view taken along line -II (al to lcl are cross-sectional views at each step showing the manufacturing method of the element, and FIG. 5 is a schematic diagram showing the ohmic electrode structure.

The device of this example has two gate electrodes ff1 (G+) between the source electrode (S) and the drain electrode (D).

It has a so-called dual gate structure with os) and 'i. Note that the passivation film covering the surface of the element is omitted in FIG.

This element is made of GaAs that has become an insulator by diffusing Cr.
An n-type epitaxial layer 7 having a mesa structure is formed on the main surface of a substrate (GaAs base) 6 by mesa soching. The thickness of the GaAs substrate 6 is 350 to 400 μm.
The thickness of the n-type epitaxial layer 7 serving as the active layer is extremely thin at 0.3 μm.

The center of the main surface of the Jjl epitaxial layer 7 has a thickness of 1 μm to 1.5 μm.
Two gate electrodes with gate length grooves of 5μ are parallel (
They are arranged at intervals of 1 μm). The two gate electrodes are a first gate electrode (G1) 8 and a second gate electrode (G1), respectively.
Gz) forms 9.

Also, separate source electrodes (s) are placed between the two gate electrodes.
) io, a drain electrode (D) 11 is provided.

The first and second gate electrodes 8 and 9 are made of aluminum with a thickness of 6000λ and form a Schottky barrier junction. Sweet, source/drain electrode 1 (1,'1
1, as shown in FIG. 5, the bottom layer is an AuGe layer 12 with a thickness of +2oo'A (the composition ratio of Ge is over 12% by weight, for example, 20%), the middle layer is an N1 layer 1 with a thickness of 300A
3. 2400-4500 A u 414 in the upper layer
It has a multi-curve structure of /+・, and an ohmic and solid bonding with the nitride virtual layer 7 is achieved by an alloy treatment at 400° C. for 5 minutes to form frost poles.

On the other hand, one ends of the first gate electrode 8 and the second gate electrode 9 are separated from the type 0 pittaxial layer 7, so that Ga, A t
3 on the substrate 6, and is formed into a wide bonding pad 15, 16' at its tip. Further, the main surface of the element is covered with an insulating film (vanosivation film) 17.

In this gap, each of the gate, drain, and source bonding pads 15, 16.
18 and 19 are not covered with the passivation film 17. Then, using this element, GaAs-8B()FF
When assembling 2T (apparatus), wires are connected to the bonding pads and nodes 15, 16 and 18, 19.

Here, the method for manufacturing such an element will be explained as shown in Fig. 4 (
A brief explanation will be given with reference to al to tel'i. First, a GaA3 substrate 6 with a thickness of 350 to 400 pm is prepared, and then a 0.3 μm n-type epitaxial layer 7 is formed on its main surface.
After the entire structure is formed, mesa etching is carried out by conventional photoetching to form the n-type epitaxial layer 7 into a mesa structure.

Next, as shown in FIG. 1bl, Au() is deposited on the n-type epitaxial layer 7 that will become the active layer by a commonly used vapor deposition technique.
Source electrode 10 consisting of e layer/NL layer/Au layer
, the drain electrode 11 was formed in the pattern described above, and alloy treatment (400° C., 5 minutes) was performed to obtain ohmic properties.
go to

Next, aluminum is attached over the n-type epitaxial layer 7 and the GaAθ substrate 6 through the pattern described above using a commonly used partial vapor deposition technique, and as shown in FIG.・Second gate electrode 8,
9 to form.

Next, a bonding pad 15 not shown in FIG.
．． A passivation film 17 is formed over the entire main surface of the element except for areas 16, 18, and 19. This passivation film 17 is formed using a suitable material using various commonly used film forming methods.

Such an element has the following effects.

(1), the composition ratio of GO in the AuGe layer is AuGe
For example, 20% by weight exceeds 12 times of heating to cause eutectic
Therefore, even if Ge is absorbed into Au due to eutectic formation during alloying, since the amount of Ge is large,
Since there is a large amount of Ge that is not consumed in eutectic formation, G
A larger amount of e is diffused into the Kn type epitaxial layer 7 than in the conventional product. As a result, the ohmic resistance is lower than that of conventional products.

Therefore, characteristics such as gm and NF of the transistor are improved.

(2k As shown in Figure 5, A of the ohmic frost pole
The thickness of uu layer 4 is 240mm compared to 1309A of the conventional product.
It is as thick as 0 to 4500 mm, and is about twice as thick as the AuGe layer 12. Therefore, although it has been shown in the experiments of the present invention, due to the thickness structure of each layer, even when the AuGe layer 12 is eutectic, the pole-up phenomenon as in the conventional case does not occur.

Therefore, as shown in FIG. 5, even if the AuGe layer 12 is made eutectic, the surface of the Auu layer 40 remains flat. As a result, uneven fine patterning of the photoresist in the process of forming the first and second gate electrodes 8 and 9 can be prevented due to the unevenness of the Au7i1i surface caused by the pole-up phenomenon. Furthermore, the bondability of the wire (gold #J) is also improved because the surface of the Au layer is flat and the content of Ga, Ge, etc. in the surface layer of the Au layer is extremely small due to the thickness of the Au layer.

Note that the present invention is not limited to the above embodiments. That is,
The present invention is also applicable to other zinc blende semiconductor devices.

As described above, according to the present invention, it is possible to reduce the ohmic resistance and to suppress the pole-up specific gravity of the ohmic resistance.

Therefore, it is possible to improve the characteristics and improve the yield.
Cost reduction is also possible.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram showing the pole-up phenomenon of an ohmic electrode, and Figure 2 is a GaAs-8BGFI according to an embodiment of the present invention.
] A plan view showing the inspector of the LiT element, Figure 3 is 0 in Figure 2.
4+a+ to 1c1 are cross-sectional views taken along line 1 and 1c1 of the element.
! FIG. 5 is a cross-sectional view showing each step of the I manufacturing method. FIG. 5 is a schematic diagram showing an ohmic electrode structure according to the present invention. 1.6...GaAB substrate, 2,12...AuGe layer,
4゜13...81 layer, 5,14...Au layer, 7...
・N-type epitaxial layer, 8...first gate electrode, 9
. . . second gate electrode, 10 . . . source electrode, 11.
...Drain electrode, 15, 16, 18.19... Bonding panode, 17... Passivation film. Figure 1 Figure 2 Figure 3 Figure 4 [/7 Figure 5]

Claims (1)

[Scope of Claims] 1. In a semiconductor device W having a semiconductor crystal substrate made of zinc blende and an electrode constituent layer made of AuGo extruded on the substrate, the content of the AuGfJ tube electrode constituent anode constituent layer is A semiconductor device characterized in that the ratio of components exceeds that which forms a eutectic layer. 2, 'Ge in the AuGe electrode constituent layer is 12 weight 9K
2. The semiconductor device according to claim 1, wherein the content exceeds . 3 Zincblende type semiconductor crystal substrate and AuG on this substrate
In a semiconductor device having an electrode formed by stacking an e layer, a barrier layer, an Au layer, and an Ii layer in a primary layer, it is noted that the Au layer has a thickness approximately twice as thick as the buried layer of the A+1Ge layer. Characteristic Semiconductor Device 1.4 The semiconductor device according to claim 3, characterized in that the content of the AuGe eutectic layer is greater than Gθll''t121%.