JPS5992491A - Semiconductor memory integrated circuit device - Google Patents

Abstract

PURPOSE:To exclude the extra IC and single element and to improve the packing density of a memory by providing a power supply back-up circuit within a chip to back up a main power supply when it is cut off. CONSTITUTION:An IC memory chip 21 contains a switch circuit 2 which performs a switch between a main power supply and a battery power supply in addition to a memory 4. A power supply cut-off detecting circuit 1, a memory activation control circuit 3 and a battery power source VB of a back-up circuit are provided outside. The power supply VB is added by any one of connection to outside, lamination on the same chip 8 or incorporation into the same package. Thus it is possible to hold the memory information despite the cut-off of the power supply without adding a power supply back-up circuit to the outside of an IC device. An activating signal 122 of the memory in this example can vary the number of logic stages in accordance with a positive logic state or a negative logic state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory integrated circuit device, and particularly to a memory integrated circuit device in which a power backup circuit is provided within the same chip.

[Prior art]

Volatile semiconductor memory has the disadvantage that when the power is cut off, the information in the memory is lost. Therefore, conventionally, some static memories etc.
Memory so that information can be retained even if power is interrupted
A battery and power backup circuit are provided outside the chip.

FIG. 1 is a block diagram of a conventional power supply backup circuit. vM is the main power source that supplies power to the chip 2o from the outside, VB is the main power source that is connected when the main power source VM is cut off, and l is the power source that detects that the main power source is cut off. 2 is a detection circuit, 2 is a power supply switching circuit, δ is a memory activation control circuit, and 4 is a memory in the chip.

When the main power supply VM is cut off, a drop in the level of the power supply voltage is detected by a power cutoff detection circuit l. For example, when it is detected that the power supply voltage has decreased from 5V to a predetermined level of 3V, the switch of the power supply switching circuit 2 is switched from the main power supply VM lid to the battery 8 side based on this detection signal. At this time, the capacity of the power supply vA (side is large, and the time constant is about several 10 m5
Since the slope of the voltage level drop is slow, the memory power supply cannot retain information when switching the power supply.
Before the pressure level reaches, for example, 2■, the 'M reservoir can be switched to the VB side.

On the other hand, the memory activation control circuit 3 determines that the power supply of the memory building is at the normal voltage level (5V) based on the power cutoff detection signal.
The memory peripheral circuits such as the XY decoder and the write/read driver are rendered inactive while the voltage drops from 1 to 2 to the minimum voltage level (2V) required to retain information. by this,
It is possible to prevent erroneous data from being written to the memory raw due to malfunction due to interruption of the main power supply V.

However, as shown in FIG. 1, in the conventional method, a power supply backup circuit (1, 2, 3
and VB), these backup circuits must be mounted on the system or memory board, requiring extra area and reducing memory packaging density.

Further, in FIG. 1, extra ICs and single elements are required, making it difficult to design a backup circuit and making it difficult to use.

[Purpose of the invention]

The object of the present invention is, in order to improve such conventional drawbacks, to provide a power supply backup circuit when the main power supply is cut off, without requiring an extra IC or single element.
It is an object of the present invention to provide a semiconductor memory integrated circuit device that can be implemented as an LSI by increasing memory packaging density.

[Summary of the invention]

The semiconductor memory integrated circuit device of the present invention is a semiconductor memory integrated circuit device having a power supply terminal and a ground terminal, and includes a four-battery power supply terminal for connecting a battery power supply therein, and a battery power supply terminal and the above-mentioned power supply terminal. It is characterized by providing a switching circuit for switching and supplying power to the memory.

Further, the semiconductor memory integrated circuit of the present invention is characterized in that, in addition to the above-mentioned circuit, a battery power source and a power cutoff detection circuit are provided inside the semiconductor memory integrated circuit.

[Embodiments of the invention]

Hereinafter, the principle and embodiments of the present invention will be explained with reference to the drawings.

FIG. 2 is a block diagram illustrating the principle of the invention.

The present invention makes it easier to use by incorporating a battery-based power backup circuit into a semiconductor memory on-chip, and also increases memory packaging density to facilitate LSI integration. In addition to the memory 4, the IC memory chip 21 of the present invention is equipped with a switching circuit 2 for switching between a main power terminal and a battery power terminal. Among the backup circuits, power cutoff detection circuit 1. Memory activation control circuit 3 and battery power supply VB are provided externally. The functions of each circuit are exactly the same as those explained in FIG. Circuit 3 and battery power supply■
. All of the backup circuits consisting of the following are provided.

120 is the output of the switching circuit 2, which is the power supply voltage for the memory 4; 121 is the external signal input terminal for memory activation;
22 is the output of the memory activation +1ilJ control circuit 3;

FIG. 3 is a mounting diagram of a semiconductor memory integrated circuit device showing an embodiment of the present invention.

In FIG. 3, 8 is a semiconductor memory integrated circuit device. Inside this device, a power cutoff detection circuit 11 switching circuit 2 and a memory activation control circuit 3 are provided, as well as an iM terminal 6 for connecting the main power supply vM and a battery power supply vI.
A battery terminal 7 is provided to connect the battery terminal 3. Note that 5 is a ground terminal. In this case, the battery power source 8 is added either by being connected to the outside, by being stacked on the same chip δ, or by being built into the same package. This provides a power back-up external to the device.
Without adding an up circuit, it is possible to retain memory information even when the power is cut off.

Note that the tE source terminal 6 and the battery terminal 7 are terminals such as bonding pads, and when the battery VB is stacked inside the chip, the battery VB and the terminal 7 are connected by solder molding etc. ■If 3 is external, connect it via an external lead pin.

FIG. 4 is a diagram showing an embodiment in which the battery 'ε source is added to the outside of the device in FIG. 3.

9 is an external lead pin for power supply, and is connected to the main power supply. In addition, 10 is an external lead pin for the battery,
Connected to battery VB externally. 11 is a grounding lead pin. Note that the external power supply lead pin 9 is provided in all memory chips, and for example, in a 16-bit static memory, there is no vacant pin, so a new '1. i. IkegawaIt is necessary to provide an external sword pin 10, but since there is an empty pin at 64 in the bit static memory, this one can be used as the external lead pin 10 for the battery.

FIG. 5 is a diagram showing an embodiment in which the "battery" flood source in FIG. 3 is built into the device.

As a method of incorporating the battery into the device 8, there is a method of stacking the battery VB on a memory chip as shown in FIG.

In FIG. 5, the external lead pin 10 is not required, making it easier to use, and the user does not need to consider backing up information using a battery when disconnecting power. That is, volatile semiconductor memory transforms into nonvolatile semiconductor memory.

FIG. 6 is a specific circuit diagram of a power supply backup circuit showing an embodiment of the present invention, and FIG. 7 is a quadrature curve diagram of the inverter circuit of FIG. 6.

The symbols in Fig. 6 are the same as those in Figs. 1 to 5;
and memory activation'rli! l I'l once W! &3
Power is shown. Among these, a new configuration is used for the power cutoff detection circuit 11.

111, 114, 11.5 are p-channel MO8) transistors, 112 are n-channel /I/403) transistors, 113, 117 are inverter circuits, 116 &'
It is a 1Nand degree circuit.

In Figure 6, normally the memory power supply is
The main power supply V, = 5V is applied (.

Now, transistors 111 and 11 of power cutoff detection circuit 1
In the CMOS circuit configured by 2, the transition voltage (threshold pressure) is connected to the gate of the 'battery' 4 sources ■8
= Set to a level higher than 2 to 3V. As shown in Figure 7, for a CMO-8 circuit with a transition voltage of 424, the drain voltage is sequentially lowered by 1.
The transfer curve with the input voltage on the horizontal axis and the output j'-pressure on the vertical axis is the curve from the upper right blade to the lower left curve, gland A.
, B, ClclijI change next. Usually the drain voltage is the main source? The E pressure vM is 5v, and the transition is
If the tonic pressure is set to about 4■, the input voltage V I N I
Since the battery voltage is 2 V - 3 V, the output voltage follows the curve.
δV). As a result, the output of the input output 113 at the next stage is low level (OV) and the output from the output channel 113 is low level (OV).
'~408 The transistor 114 is in the operating state,
The main voltage I is supplied to the memory via the switching circuit 2 and the output line 120.

When the power source 1 is cut off (well, the drain 1 voltage changes to curve B (3V) in Fig. 7), but at this time as well, the transistor 111 is turned on, so the output 119 is
Hold Inbel. When the main power supply voltage Y further decreases to curve C in Fig. 7, the input voltage (V, = 2~3v) is at a higher level than the transition voltage (2), so transistor 111 or 112 is turned off. is turned on, and the output 119 changes to low level.

As a result, the transistor 114 of the switching circuit 2 is turned off, the transistor 115 is turned on, and the power source for the memory is replaced by the voltage source VB.

In addition, in the memory activation control circuit 3, since the memory activation external signal 121 is normally at a high level and the input 119 is at a high level, the output of the NAND circuit 116 is at a low level, and the output 122 via the inverter circuit 117 is is at a high level, activating memory.

Here, in the control circuit 3, the input 119 becomes low level and the output 122 becomes low level at the same time as the power supply is cut off, so that the peripheral circuits of the memory are rendered inactive and no error information is written. Do it like this.

This memory activation control wholesale circuit 3 is a circuit for preventing error information from being written to the memory as described above, but the circuit 3
There is no need to provide

Note that the number of logic stages can be changed depending on whether the activation signal 122 of the memory in this actual car example is in a positive logic or negative logic state. Further, the values of the main power supply voltage vM=5V or the battery voltage VM=2 to 3■ in this embodiment can be changed depending on the purpose of use. Furthermore, it is also possible to place the n-channel MOS transistor shown in FIG. 6 and the p-channel 1v108 transistor, and in this case, it is necessary to reverse all the potential relationships.

In addition, CM
When an OS circuit is introduced, the only current that flows through the circuit is the through current that flows during a transition when the power is cut off. In a normal state, the junction leakage current is about (10th A), and there is almost no increase in current consumption due to this embodiment.

In this embodiment, the line 120 is used as the output of the power supply switching circuit 2 as a supply line to the memory, but it may also be used only as a current supply line to the memory cells.

In this case, the power supply line used for the peripheral circuit of the memory will be connected to the main power supply (2).

〔Effect of the invention〕

As explained above, according to the present invention, a power supply backup circuit is provided inside the chip when the main power supply is cut off, which eliminates the need for extra ICs and single elements, and improves memory packaging density. I can do kotokidama. By providing a stacked battery on top of the chip, it is possible to further improve the packaging density.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional power supply backup circuit.
FIG. 2 is a block diagram showing the principle of the present invention, and FIG. 3 is a mounting diagram of a semiconductor memory integrated circuit device showing an embodiment of the present invention.
Figures 4 and 5 are the specific layout diagram of Figure 3 and Figure 6, respectively.
7 is a specific circuit diagram of a power supply backup circuit showing an embodiment of the present invention, and FIG. 7 is an operating characteristic curve diagram of the CMOS inverter circuit of FIG. 6. 1: Power cutoff detection circuit, 2: Switching circuit, 3: Memory activation control circuit, 4: Memory, 5: Ground terminal, 6: Power supply terminal, 7: Battery terminal, 8.20, 21° 22: Semiconductor memory integration Circuit devices, 111, 114. 119: p-channel MOS transistor, 112:
n-channel MOS) transistors, 113, 117:
Inverter circuit, 116 2nd circuit. Figure 1~'M Figure 2 ■M Figure 3 Figure 6 Figure 4 Figure 5 Figure 7

Claims (5)

[Claims] (1) In a semiconductor memory integrated circuit device equipped with a power supply terminal and a ground terminal, a battery power supply terminal for connecting a battery power source inside, and a power supply for connecting the battery power supply terminal to the memory when the main power supply is cut off. A semiconductor memory integrated circuit characterized by being provided with a backup circuit. (2) The semiconductor memory integrated circuit device according to claim 1, wherein only a 'i power supply switching circuit is provided therein as the power supply backup circuit. (3) The semiconductor memory integrated circuit device according to claim 1, wherein the power backup circuit includes an 'in switching circuit and a power cutoff detection circuit. (4) The semiconductor memory integrated circuit device according to claim 1, wherein the power supply backup circuit includes a power supply switching circuit, an IE source interruption detection circuit, and a battery power supply. (5) The power cutoff detection circuit is a CMO whose gate is connected to the Kuroike power supply voltage and whose drain is connected to the main power supply voltage.
5. The semiconductor memory integrated circuit device according to claim 3, wherein the semiconductor memory integrated circuit device is comprised of an S inverter.